ESD7451 [ONSEMI]
ESD Protection Diodes;
| 型号： | ESD7451 |
| 厂家： | 
ONSEMI |
| 描述： | ESD Protection Diodes |
| 文件： | 总5页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD7451, SZESD7451
ESD Protection Diodes
Micro−Packaged Diodes for ESD Protection
The ESD7451 is designed to protect voltage sensitive components
that require ultra−low capacitance from ESD and transient voltage
events. Excellent clamping capability, low capacitance, low leakage,
and fast response time, make these parts ideal for ESD protection on
designs where board space is at a premium. Because of its low
capacitance, the part is well suited for use in high frequency designs
such as USB 2.0 high speed and antenna line applications.
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1
2
Cathode
Anode
Features
• Ultra−Low Capacitance (0.35 pF Max)
• Low Clamping Voltage
• Stand−off Voltage: 3.3 V
• Low Leakage
• Response Time is < 1 ns
• Low Dynamic Resistance < 1 W
• IEC61000−4−2 Level 4 ESD Protection
MARKING
DIAGRAM
XDFN2
CASE 711AM
E M
G
E
M
= Specific Device Code
= Date Code
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
ORDERING INFORMATION
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
†
Device
Package
Shipping
Typical Applications
ESD7451N2T5G
XDFN2
(Pb−Free)
8000 / Tape &
Reel
• RF Signal ESD Protection
• RF Switching, PA, and Antenna ESD Protection
• Near Field Communications
SZESD7451N2T5G
XDFN2
(Pb−Free)
8000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
MAXIMUM RATINGS
Rating
IEC 61000−4−2 (ESD)
Symbol
Value
Unit
Contact
Air
25
25
kV
Total Power Dissipation on FR−5 Board
°P °
250
mW
D
(Note 1) @ T = 25°C
A
Thermal Resistance, Junction−to−Ambient
R
400
−55 to +150
260
°C/W
°C
q
JA
Junction and Storage Temperature Range T , T
J
stg
Lead Solder Temperature − Maximum
(10 Second Duration)
T
L
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
June, 2014 − Rev. 2
ESD7451/D
ESD7451, SZESD7451
ELECTRICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
A
I
I
PP
Symbol
Parameter
I
Maximum Reverse Peak Pulse Current
PP
I
T
I
V
R
BR RWM
V
Clamping Voltage @ I
V
C
V
C
PP
V
I
V
V
V
R
T
RWM BR C
V
RWM
Working Peak Reverse Voltage
I
I
R
Maximum Reverse Leakage Current @ V
RWM
V
Breakdown Voltage @ I
Test Current
BR
T
I
PP
I
T
Bi−Directional TVS
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
V
Reverse Working Voltage
Breakdown Voltage (Note 2)
Reverse Leakage Current
Clamping Voltage (Note 3)
Clamping Voltage (Note 3)
ESD Clamping Voltage
Junction Capacitance
V
RWM
3.3
V
BR
I = 1 mA
6.0
V
T
I
R
V
RWM
= 3.3 V
< 1.0
50
10
13
nA
V
V
I
PP
I
PP
= 1 A
C
C
C
V
V
= 3 A
V
Per IEC61000−4−2
C
V
R
V
R
= 0 V, f = 1 MHz
= 0 V, f = 1 GHz
0.25
0.22
0.35
0.35
pF
J
Dynamic Resistance
R
TLP Pulse
0.55
W
DYN
2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.
3. Non−repetitive current pulse at T = 25°C, per IEC61000−4−5 waveform.
A
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2
ESD7451, SZESD7451
1.E−03
1.E−04
1.E−05
1.E−06
1.E−07
1.E−08
1.E−09
1.E−10
1.E−11
1.E−12
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
−8
−6
−4
−2
0
2
4
6
8
−3
−2
−1
0
1
2
3
V (V)
VBias (V)
Figure 1. IV Characteristics
Figure 2. CV Characteristics
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2
0
−2
−4
−6
−8
−10
−12
−14
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
FREQUENCY (GHz)
1.E+08
1.E+09
FREQUENCY (Hz)
1.E+10
Figure 3. RF Insertion Loss
Figure 4. Capacitance over Frequency
16
8
6
4
2
0
−16
−14
−12
−10
−8
8
6
4
2
0
14
12
10
8
6
−6
4
−4
2
−2
0
0
0
2
4
6
8
10
12 14
16 18
20
0
2
4
6
8
10
12 14
16 18
20
VC, VOLTAGE (V)
VC, VOLTAGE (V)
Figure 5. Positive TLP I−V Curve
Figure 6. Negative TLP I−V Curve
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3
ESD7451, SZESD7451
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 7. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 8. Diagram of ESD Test Setup
ESD Voltage Clamping
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
100
t
r
PEAK VALUE I
@ 8 ms
RSM
90
80
70
60
50
40
30
20
PULSE WIDTH (t ) IS DEFINED
P
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I /2 @ 20 ms
RSM
t
P
10
0
0
20
40
t, TIME (ms)
60
80
Figure 9. 8 X 20 ms Pulse Waveform
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4
ESD7451, SZESD7451
PACKAGE DIMENSIONS
XDFN2 1.0x0.6, 0.65P (SOD−882)
CASE 711AM
ISSUE O
NOTES:
0.10
C
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. EXPOSED COPPER ALLOWED AS SHOWN.
A B
E
D
PIN 1
INDICATOR
MILLIMETERS
DIM MIN
MAX
0.44
0.05
0.53
A
A1
b
0.34
−−−
0.43
0.05
C
TOP VIEW
D
E
e
1.00 BSC
0.60 BSC
0.65 BSC
NOTE 3
A
0.10
0.10
C
L
0.20
0.30
C
RECOMMENDED
A1
SEATING
PLANE
C
SOLDER FOOTPRINT*
SIDE VIEW
1.20
2X
2X
0.47
e
0.60
b
e/2
PIN 1
M
0.05
C A B
1
DIMENSIONS: MILLIMETERS
2X
L
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
M
0.05
C A B
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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ESD7451/D
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