CAT6095VP2I-GT_技术文档

CAT6095

Digital Output Temperature

Sensor

Description

The CAT6095 is a JEDEC JC42.4 compliant Temperature Sensor

designed for general purpose temperature measurements requiring a

digital output.

http://onsemi.com

The CAT6095 measures temperature at least 10 times every second.

Temperature readings can be retrieved by the host via the serial

interface, and are compared to high, low and critical trigger limits

stored into internal registers. Over or under limit conditions can be

signaled on the open−drain EVENT pin.

TDFN−8

VP2 SUFFIX

CASE 511AK

The CAT6095 is packaged in space saving TDFN package with

exposed backside die attach pads (DAP). The exposed DAP reduces

overall thermal resistance, thus providing faster response to thermal

changes when compared to SOIC, TSSOP or SOT packages.

PIN CONFIGURATION

1

V

A

CC

0

1

2

EVENT

SCL

Features

• JEDEC JC42.4 Compliant Temperature Sensor

• Temperature Range: −40°C to +125°C

• Supply Range: 3.3 V 10%

SDA

V

SS

(Top View)

For the location of Pin 1, please consult the

corresponding package drawing.

2

• I C / SMBus Interface

• Schmitt Triggers and Noise Suppression Filters on SCL and SDA

Inputs

MARKING DIAGRAM

• Low Power CMOS Technology

HMC

ALL

YM

• 2 x 3 x 0.75 mm TDFN Package

• These Devices are Pb−Free and are RoHS Compliant

G

V

CC

HMC

= Specific Device Code

A

LL

Y

M

G

= Assembly Location Code

= Assembly Lot Number (Last Two Digits)

= Production Year (Last Digit)

= Production Month (1 − 9, O, N, D)

= Pb−Free Package

SCL

CAT6095

A , A , A

0

EVENT

2

1

PIN FUNCTIONS

SDA

Pin Name

Function

Device Address Input

Serial Data Input/Output

Serial Clock Input

A , A , A

0

1

2

V

SS

SDA

Figure 1. Functional Symbol

SCL

EVENT

Open−drain Event Output

Power Supply

V

CC

V

Ground

SS

DAP

Backside Exposed DAP at V

SS

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 15 of this data sheet.

1

Publication Order Number:

May, 2011 − Rev. 5

CAT6095/D

CAT6095

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter

Rating

Units

°C

Operating Temperature

−45 to +130

−65 to +150

−0.5 to +6.5

Storage Temperature

°C

Voltage on any pin with respect to Ground (Note 1)

V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. The A pin can be raised to a HV level compatible

CC

0

with the use of a DDR3 SPD device sharing the bus with the TS. SCL and SDA inputs can be raised to the maximum limit, irrespective of V

.

CC

Table 2. TEMPERATURE CHARACTERISTICS (V = 3.3 V 10%, T = −40°C to +125°C, unless otherwise specified)

CC

A

Parameter

Test Conditions/Comments

Max

1.0

Unit

°C

Temperature Reading Error

Class B, JC42.4 compliant

+75°C ≤ T ≤ +95°C, active range

A

+40°C ≤ T ≤ +125°C, monitor range

2.0

°C

A

−20°C ≤ T ≤ +125°C, sensing range

3.0

°C

A

ADC Resolution

12

Bits

°C

Temperature Resolution

Temperature Conversion Time

Thermal Resistance (Note 2) q

0.0625

100

92

ms

Junction−to−Ambient (Still Air)

°C/W

JA

2. Power Dissipation is defined as P = (T − T )/q , where T is the junction temperature and T is the ambient temperature. The thermal

J

A

JA

J

A

resistance value refers to the case of a package being used on a standard 2−layer PCB.

Table 3. D.C. OPERATING CHARACTERISTICS (V = 3.3 V 10%, T = −40°C to +125°C, unless otherwise specified)

CC

A

Symbol

Parameter

Supply Current

Test Conditions/Comments

TS active

TS shut−down; no bus activity

Pin at GND or V

Min

Max

200

Unit

mA

V

I

CC

I

10

SHDN

I

L

I/O Pin Leakage Current

Input Low Voltage

2

CC

V

−0.5

0.3 x V

IL

CC

V

Input High Voltage

Output Low Voltage

0.7 x V

V

+ 0.5

CC

V

IH

CC

V

I

OL

= 3 mA, V > 2.5 V

0.4

V

OL

CC

http://onsemi.com

2

CAT6095

Table 4. A.C. CHARACTERISTICS (V = 3.3 V 10%, T = −40°C to +125°C) (Note 3)

CC

A

Symbol

(Note 4)

Parameter

Min

10

Max

Units

kHz

ns

F

Clock Frequency

400

SCL

t

High Period of SCL Clock

Low Period of SCL Clock

SMBus SCL Clock Low Timeout

SDA and SCL Rise Time

SDA and SCL Fall Time

600

1300

25

HIGH

t

ns

LOW

t

(Note 4)

35

ms

ns

TIMEOUT

t

(Note 5)

300

R

t (Note 5)

F

ns

t

(Note 6)

Data Setup Time

100

0

ns

SU:DAT

HD:DAT

t

(Note 5)

Data Hold Time (for Input Data)

Data Hold Time (for Output Data)

START Condition Setup Time

START Condition Hold Time

STOP Condition Setup Time

ns

300

600

1300

900

ns

t

ns

SU:STA

t

ns

HD:STA

SU:STO

t

ns

t

Bus Free Time Between STOP and START

Noise Pulse Filtered at SCL and SDA Inputs

Power−up Delay to Valid Temperature Recording

ns

BUF

T

i

100

ns

t

(Note 7)

ms

PU

3. Timing reference points are set at 30%, respectively 70% of V , as illustrated in Figure 11. Bus loading must be such as to allow meeting

CC

the V , V as well as the various timing limits.

IL

OL

4. The TS interface will reset itself and will release the SDA line if the SCL line stays low beyond the t

limit. The time−out count is started

TIMEOUT

(and then re−started) on every negative transition of SCL in the time interval between START and STOP.

2

5. In a “Wired−OR” system (such as I C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be

able to sink the (external) bus pull−up current (in order to meet the V and/or V limits), it follows that SDA fall time is inherently faster than

IL

OL

SDA rise time. SDA rise time can exceed the standard recommended t limit, as long as it does not exceed t

− t

HD:DAT

− t , where

SU:DAT

R

LOW

t

and t

are actual values (rather than spec limits). A shorter t

leaves more room for a longer SDA t , allowing for a more

LOW

HD:DAT

HD:DAT R

capacitive bus or a larger bus pull−up resistor. At the minimum t

spec limit of 1300 ns, the maximum t

is <700 ns, thus allowing for an SDA t of up to 500 ns at minimum t

of 100 ns is a limit recommended by standards. The TS will accept a t

7. The first valid temperature recording can be expected after t at nominal supply voltage.

of 900 ns demands a

HD:DAT

LOW

maximum SDA t of 300 ns. The CAT6095’s maximum t

6. The minimum t

.

R

HD:DAT

R

LOW

of 0 ns.

SU:DAT

PU

Table 5. PIN CAPACITANCE (T = 25°C, V = 3.3 V, f = 1 MHz)

A

CC

Symbol

Parameter

Test Conditions/Comments

Min

Max

8

Unit

C

IN

SDA, EVENT Pin Capacitance

Input Capacitance (other pins)

V

= 0

pF

IN

6

http://onsemi.com

3

CAT6095

TYPICAL PERFORMANCE CHARACTERISTICS

(V = 3.3 V, T = −25°C to +125°C, unless otherwise specified.)

CC

A

300

250

200

150

100

5

4

3

2

1

50

0

−1

−25

0

25

50

(°C)

75

100

125

0

25

50

(°C)

75

100

125

T

AMB

Figure 2. Active Current (I²C−bus Idle)

Figure 3. Standby Current

(I²C−bus Idle, TS Shut−down)

4

3

2

1

80

70

60

50

40

Part # 2

Part # 1

0

−1

−2

30

20

−3

−4

−25

0

25

50

(°C)

75

100

−25

25

50

(°C)

75

100

T

AMB

Figure 4. Temperature Read−Out Error

Figure 5. A/D Conversion Time

3.0

2.6

2.2

1.8

40

35

30

25

20

1.4

1.0

−25

0

25

50

(°C)

75

100

−25

25

50

(°C)

75

100

T

AMB

Figure 6. POR Threshold Voltage

Figure 7. SMBus SCL Clock Low Timeout

http://onsemi.com

4

CAT6095

Pin Description

connect to the bus via their respective SCL and SDA pins.

The transmitting device pulls down the SDA line to

‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.

Data transfer may be initiated only when the bus is not

busy (see A.C. Characteristics).

During data transfer, the SDA line must remain stable

while the SCL line is HIGH. An SDA transition while SCL

is HIGH will be interpreted as a START or STOP condition

(Figure 8).

SCL: The Serial Clock input pin accepts the Serial Clock

generated by the Master (Host).

SDA: The Serial Data I/O pin receives input data and

transmits data stored in the internal registers. In transmit

mode, this pin is open drain. Data is acquired on the positive

edge, and is delivered on the negative edge of SCL.

A0, A1 and A2: The Address pins set the device address.

These pins have on−chip pull−down resistors.

START

EVENT: The open−drain EVENT pin can be programmed

The START condition precedes all commands. It consists

of a HIGH to LOW transition on SDA while SCL is HIGH.

The START acts as a ‘wake−up’ call to all Slaves. Absent a

START, a Slave will not respond to commands.

to signal over/under temperature limit conditions.

Power−On Reset

The CAT6095 incorporates Power−On Reset (POR)

circuitry which monitors the supply voltage, and then resets

(initializes) the internal state machine below a POR trigger

level of approximately 2.0 V, i.e. well below the minimum

STOP

The STOP condition completes all commands. It consists

of a LOW to HIGH transition on SDA while SCL is HIGH.

The STOP tells the Slave that no more data will be written

to or read from the Slave.

recommended V value.

CC

The temperature sensor (TS) powers-up into conversion

mode. The internal state machine will operate properly

above the POR trigger level, but valid temperature readings

can be expected only after the first conversion cycle started

and completed at nominal supply voltage.

Device Addressing

The Master initiates data transfer by creating a START

condition on the bus. The Master then broadcasts an 8−bit

serial Slave address. The first 4 bits of the Slave address (the

preamble) select the Temperature Sensor (TS preamble =

0011) as shown in Figure 9. The next 3 bits, A2, A1 and A0,

select one of 8 possible TS Slave devices. The last bit, R/W,

speciﬁes whether a Read (1) or Write (0) operation is being

performed.

Device Interface

The CAT6095 supports I C and SMBus data transmission

2

protocols. These protocols describe serial communication

between transmitters and receivers sharing a 2−wire data

bus. Data ﬂow is controlled by a Master device, which

generates the serial clock and the START and STOP

conditions. The CAT6095 acts as a Slave device. Master and

Slave alternate as transmitter and receiver. Up to 8 CAT6095

devices may be present on the bus simultaneously, and can

be individually addressed by matching the logic state of the

address inputs A0, A1, and A2.

Acknowledge

A matching Slave address is acknowledged (ACK) by the

th

Slave by pulling down the SDA line during the 9 clock

cycle (Figure 10). After that, the Slave will acknowledge all

data bytes sent to the bus by the Master. When the Slave is

the transmitter, the Master will in turn acknowledge data

2

I C/SMBus Protocol

th

bytes in the 9 clock cycle. The Slave will stop transmitting

2

The I C/SMBus uses two ‘wires’, one for clock (SCL) and

after the Master does not respond with acknowledge

(NoACK) and then issues a STOP. Bus timing is illustrated

in Figure 11.

one for data (SDA). The two wires are connected to the V

supply via pull−up resistors. Master and Slave devices

CC

http://onsemi.com

5

CAT6095

SDA

SCL

START BIT

STOP BIT

Figure 8. Start/Stop Timing

TEMPERATURE SENSOR

0

1

A

0

R/W

2

1

PREAMBLE

DEVICE ADDRESS

Figure 9. Slave Address Bits

SCL FROM

MASTER

1

8

9

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

Figure 10. Acknowledge Timing

t

F

HIGH

t

R

t

LOW

70%

30%

70%

30%

70%

SCL

SDA

t

HD:DAT

SU:STA

t

HD:STA

SU:STO

SU:DAT

70%

30%

70%

30%

t

BUF

Figure 11. Bus Timing

http://onsemi.com

6

CAT6095

Write Operations

Read Operations

Temperature Sensor Register Write

Immediate Read

To write data to a TS register the Master creates a START

condition on the bus, and then sends out the appropriate

Slave address (with the R/W bit set to ‘0’), followed by an

address byte and two data bytes. The matching Slave will

acknowledge the Slave address, TS register address and the

TS register data (Figure 12). The Master then ends the

session by creating a STOP condition on the bus. The STOP

completes the TS register update. Note that all registers in

the TS are ‘volatile’ meaning any data contained in them is

lost when power is removed from the chip.

Upon power-up, the Temperature Sensor (TS) address

counter is initialized to 00h. The TS address counter will

thus point to the Capability Register. This address counter

may be updated by subsequent operations.

A CAT6095 presented with a Slave address containing a

‘1’ in the R/W position will acknowledge the Slave address

and will then start transmitting data being pointed at by the

current TS register address counter. The Master stops this

transmission by responding with NoACK, followed by a

STOP (Figure 13).

Selective Read

The Read operation can be started at an address different

from the one stored in the address counter, by preceding the

Immediate Read sequence with a ‘data less’ Write operation.

The Master sends out a START, Slave address and address

byte, but rather than following up with data (as in a Write

operation), the Master then issues another START and

continuous with an Immediate Read sequence (Figure 14).

BUS ACTIVITY:

S

T

A

R

T

S

T

SLAVE

REGISTER

ADDRESS

O

MASTER

SDA LINE

ADDRESS

DATA (MSB)

DATA (LSB)

P

S

A

C

K

A

C

K

A

C

K

A

C

K

SLAVE

Figure 12. Temperature Sensor Register Write

BUS ACTIVITY:

S

N

O

A

C

K

T

A

R

T

S

T

A

C

K

SLAVE

O

P

MASTER

SDA LINE

ADDRESS

S

P

A

C

K

SLAVE

DATA (MSB)

DATA (LSB)

Figure 13. Immediate Read

BUS ACTIVITY:

S

T

S

T

A

N

O

A

C

K

S

T

A

REGISTER

ADDRESS

SLAVE

A

C

K

R

T

O

P

MASTER

SDA LINE

ADDRESS

T

S

P

A

C

K

A

C

K

A

C

K

DATA (MSB)

DATA (LSB)

SLAVE

Figure 14. Selective Read

http://onsemi.com

7

CAT6095

Temperature Sensor Operation

Registers

The CAT6095 temperature sensor (TS) combines a

Proportional to Absolute Temperature (PTAT) sensor with

a S−D modulator, yielding a 12 bit plus sign digital

temperature representation.

The CAT6095 contains eight 16−bit wide registers

allocated to TS functions, as shown in Table 6. Upon

power−up, the internal address counter points to the

capability register.

The TS runs on an internal clock, and starts a new

conversion cycle at least every 100 ms. The result of the

most recent conversion is stored in the Temperature Data

Register (TDR), and remains there following a TS

Shut−Down. Reading from the TDR does not interfere with

the conversion cycle.

The value stored in the TDR is compared against limits

stored in the High Limit Register (HLR), the Low Limit

Register (LLR) and/or Critical Temperature Register

(CTR). If the measured value is outside the alarm limits or

above the critical limit, then the EVENT pin may be

asserted. The EVENT output function is programmable, via

theConfiguration Register for interrupt mode, comparator

mode and polarity.

The temperature limit registers can be Read or Written by

the host, via the serial interface. At power−on, all the

(writable) internal registers default to 0x0000, and should

therefore be initialized by the host to the desired values. The

EVENT output starts out disabled (corresponding to

polarity active low); thus preventing irrelevant event bus

activity before the limit registers are initialized. While the

TS is enabled (not shut−down), event conditions are

normally generated by a change in measured temperature as

recorded in the TDR, but limit changes can also trigger

events as soon as the new limit creates an event condition,

i.e. asynchronously with the temperature sampling activity.

In order to minimize the thermal resistance between

sensor and PCB, it is recommended that the exposed

backside die attach pad (DAP) be soldered to the PCB

ground plane.

Capability Register (User Read Only)

This register lists the capabilities of the TS, as detailed in

the corresponding bit map.

Configuration Register (Read/Write)

This register controls the various operating modes of the

TS, as detailed in the corresponding bit map.

Temperature Trip Point Registers (Read/Write)

The CAT6095 features 3 temperature limit registers, the

HLR, LLR and CLR mentioned earlier. The temperature

value recorded in the TDR is compared to the various limit

values, and the result is used to activate the EVENT pin. To

avoid undesirable EVENT pin activity, this pin is

automatically disabled at power−up to allow the host to

initialize the limit registers and the converter to complete the

first conversion cycle under nominal supply conditions.

Data format is two’s complement with the LSB representing

0.25°C, as detailed in the corresponding bit maps.

Temperature Data Register (User Read Only)

This register stores the measured temperature, as well as

trip status information. B15, B14 and B13 are the trip status

bits, representing the relationship between measured

temperature and the 3 limit values; these bits are not affected

by EVENT status or by Configuration register settings.

Measured temperature is represented by bits B12 to B0. Data

format is two’s complement, where B12 represents the sign,

B11 represents 128°C, etc. and B0 represents 0.0625°C.

Manufacturer ID Register (Read Only)

The manufacturer ID assigned by the PCI−SIG trade

organization to the CAT6095 device is 0x1B09.

Device ID and Revision Register (Read Only)

This register contains manufacturer specific device ID

and device revision information.

http://onsemi.com

8

CAT6095

Table 6. TEMPERATURE SENSOR REGISTERS

Register Address

0x00

Register Name

Power−On Default

0x007F

Read/Write

Read

Capability Register

0x01

Configuration Register

High Limit Register

0x0000

Read/Write

Read

0x02

0x0000

0x03

Low Limit Register

0x0000

0x04

Critical Limit Register

Temperature Data Register

Manufacturer ID Register

Device ID/Revision Register

Reserved

0x0000

0x05

Undefined

0x1B09

0x0813

0x06

Read

0x07

Read

0x08 −

−

Table 7. CAPABILITY REGISTER

B15

RFU

B7

B14

RFU

B13

RFU

B5

B12

RFU

B4

B11

B10

RFU

B9

B8

RFU

B0

RFU

B1

B6

B3

B2

EVSD

TMOUT

RFU

TRES [1:0]

RANGE

ACC

EVENT

Bit

Description

Reserved for future use; can not be written; should be ignored; will typically read as 0

B15:B8

B7 (Note 8)

0:

1:

Configuration register bit 4 is frozen upon setting Configuration register bit 8

(i.e. a TS shut−down freezes the EVENT output)

Configuration register bit 4 is cleared upon setting Configuration register bit 8

(i.e. a TS shut−down de−asserts the EVENT output)

B6

B5

0:

1:

The TS implements SMBus time−out within the range 10 to 60 ms

The TS implements SMBus time−out within the range 25 to 35 ms

0:

1:

Pin A V compliance required for RSWP/SPD compatibility not explicitly stated

0 HV

Pin A V compliance required for RSWP/SPD compatibility explicitly stated

0

HV

B4:B3

00:

01:

10:

11:

LSB = 0.50°C (9 bit resolution)

LSB = 0.25°C (10 bit)

LSB = 0.125°C (11 bit)

LSB = 0.0625°C (12 bit)

B2

B1

B0

0:

1:

Positive Temperature Only

Positive and Negative Temperature

0:

1:

2°C over the active range and 3°C over the operating range (Class C)

1°C over the active range and 2°C over the monitor range (Class B)

0:

1:

Critical Temperature only

Alarm and Critical Temperature

8. Configuration Register bit 4 can be cleared (but not set) after Configuration Register bit 8 is set, by writing a “1” to Configuration Register

bit 5 (i.e. the EVENT output can be de-asserted during TS shut-down periods)

http://onsemi.com

9

CAT6095

Table 8. CONFIGURATION REGISTER

B15

RFU

B14

RFU

B13

RFU

B12

RFU

B4

B11

RFU

B3

B10

B2

B9

B8

SHDN

HYST [1:0]

B7

B6

B5

B1

B0

TCRIT_LOCK

EVENT_LOCK

CLEAR

EVENT_STS

EVENT_CTRL

TCRIT_ONLY

EVENT_POL

EVENT_MODE

Bit

Description

Reserved for future use; can not be written; should be ignored; will typically read as 0

B15:B11

B10:B9 (Note 9)

00:

01:

10:

11:

Disable hysteresis

Set hysteresis at 1.5°C

Set hysteresis at 3°C

Set hysteresis at 6°C

B8 (Note 13)

B7 (Note 12)

B6 (Note 12)

B5 (Note 11)

B4 (Note 10)

B3 (Note 9)

0:

1:

Thermal Sensor is enabled; temperature readings are updated at sampling rate

Thermal Sensor is shut down; temperature reading is frozen to value recorded before SHDN

0:

1:

Critical trip register can be updated

Critical trip register cannot be modified; this bit can be cleared only at POR

0:

1:

Alarm trip registers can be updated

Alarm trip registers cannot be modified; this bit can be cleared only at POR

0:

1:

Always reads as 0 (self−clearing)

Writing a 1 to this position clears an event recording in interrupt mode only

0:

1:

EVENT output pin is not being asserted

EVENT output pin is being asserted

0:

1:

EVENT output disabled; polarity dependent: open−drain for bit B1 = 0 and grounded for B1 = 1

EVENT output enabled

B2 (Note 15)

B1 (Notes 9, 14)

B0 (Note 9)

0:

1:

event condition triggered by alarm or critical temperature limit crossing

event condition triggered by critical temperature limit crossing only

0:

1:

EVENT output active low

EVENT output active high

0:

1:

Comparator mode

Interrupt mode

9. Can not be altered (set or cleared) as long as either one of the two lock bits, B6 or B7 is set.

10.This bit is a polarity independent ‘software’ copy of the EVENT pin, i.e. it is under the control of B3.

11. Writing a ‘1’ to this bit clears an event condition in Interrupt mode, but has no effect in comparator mode. When read, this bit always returns

0. Once the measured temperature exceeds the critical limit, setting this bit has no effect (see Figure 12).

12.Cleared at power-on reset (POR). Once set, this bit can only be cleared by a POR condition.

13.The TS powers up into active mode, i.e. this bit is cleared at power-on reset (POR). When the TS is shut down the ADC is disabled and the

temperature reading is frozen to the most recently recorded value. The TS can not be shut down (B8 can not be set) as long as either one

of the two lock bits, B6 or B7 is set. However, the bit can be cleared at any time.

14.The EVENT output is “open-drain” and requires an external pull-up resistor for either polarity. The “natural” polarity is “active low”, as it allows

“wired-or” operation on the EVENT bus.

15.Can not be set as long as lock bit B6 is set.

http://onsemi.com

10

CAT6095

Table 9. HIGH LIMIT REGISTER

B15

0

B14

0

B13

0

B12

Sign

B4

B11

B10

64°C

B2

B9

32°C

B1

B8

16°C

B0

128°C

B3

B7

8°C

B6

4°C

B5

2°C

1°C

0.5°C

0.25°C

0

Table 10. LOW LIMIT REGISTER

B15

0

B14

0

B13

0

B12

Sign

B4

B11

128°C

B3

B10

64°C

B2

B9

32°C

B1

B8

16°C

B0

B7

8°C

B6

4°C

B5

2°C

1°C

0.5°C

0.25°C

0

Table 11. TCRIT LIMIT REGISTER

B15

0

B14

0

B13

0

B12

Sign

B4

B11

128°C

B3

B10

64°C

B2

B9

32°C

B1

B8

16°C

B0

B7

8°C

B6

4°C

B5

2°C

1°C

0.5°C

0.25°C

0

Table 12. TEMPERATURE DATA REGISTER

B15

TCRIT

B7

B14

HIGH

B6

B13

LOW

B5

B12

Sign

B4

B11

128°C

B3

B10

64°C

B2

B9

32°C

B1

B8

16°C

B0

8°C

4°C

2°C

1°C

0.5°C

0.25°C

(Note 16)

0.125°C

(Note 16)

0.0625°C

(Note 16)

16.When applicable (as defined by Capability bit TRES), unsupported bits will read as 0

Bit

Description

B15

0: Temperature is below the TCRIT limit

1: Temperature is equal to or above the TCRIT limit

B14

B13

0: Temperature is equal to or below the High limit

1: Temperature is above the High limit

0: Temperature is equal to or above the Low limit

1: Temperature is below the Low limit

http://onsemi.com

11

CAT6095

Register Data Format

Event Pin Functionality

The values used in the temperature data register and the 3

temperature trip point registers are expressed in two’s

complement format. The measured temperature value is

expressed with 12−bit resolution, while the 3 trip

temperature limits are set with 10−bit resolution. The total

temperature range is arbitrarily defined as 256°C, thus

yielding an LSB of 0.0625°C for the measured temperature

and 0.25°C for the 3 limit values. Bit B12 in all temperature

registers represents the sign, with a ‘0’ indicating a positive,

and a ‘1’ a negative value. In two’s complement format,

negative values are obtained by complementing their

positive counterpart and adding a ‘1’, so that the sum of

opposite signed numbers, but of equal absolute value, adds

up to zero.

The EVENT output reacts to temperature changes as

illustrated in Figure 15, and according to the operating mode

defined by the Configuration register.

In Interrupt Mode, the enabled EVENT output will be

asserted every time the temperature crosses one of the alarm

window limits, and can be de−asserted by writing a ‘1’ to the

clear event bit (B5) in the configuration register. When the

temperature exceeds the critical limit, the event remains

asserted as long as the temperature stays above the critical

limit and can not be cleared.

In Comparator Mode, the EVENT output is asserted

outside the alarm window limits, while in Critical

Temperature Mode, EVENT is asserted only above the

critical limit. The exact trip limits are determined by the 3

temperature limit settings and the hysteresis offsets, as

illustrated in Figure 16.

Following a TS shut−down request, the converter is

stopped and the most recently recorded temperature value

present in the TDR is frozen; the EVENT output will continue

to reflect the state immediately preceding the shut−down

command. Therefore, if the state of the EVENT output

creates an undesirable bus condition, appropriate action must

be taken either before or after shutting down the TS. This may

require clearing the event, disabling the EVENT output or

perhaps changing the EVENT output polarity.

Note that trailing ‘0’ bits, are ‘0’ irrespective of polarity.

Therefore the don’t care bits (B1 and B0) in the 10−bit

resolution temperature limit registers, are always ‘0’.

Table 13. 12−BIT TEMPERATURE DATA FORMAT

Binary (B12 to B0)

1 1100 1001 0000

1 1100 1110 0000

1 1110 0111 0000

1 1111 1111 1111

0 0000 0000 0000

0 0000 0000 0001

0 0001 1001 0000

0 0011 0010 0000

0 0111 1101 0000

Hex

1C90

1CE0

1E70

1FFF

000

Temperature

−55°C

−50°C

−25°C

−0.0625°C

0°C

In normal use, events are triggered by a change in

recorded temperature, but the CAT6095 will also respond to

limit register changes. Whereas recorded temperature

values are updated at sampling rate frequency, limits can be

modified at any time. The enabled EVENT output will react

to limit changes as soon as the respective registers are

updated. This feature may be useful during testing.

001

+0.0625°C

+25°C

190

320

+50°C

7D0

+125°C

http://onsemi.com

12

CAT6095

TEMPERATURE

CRITICAL

HYSTERESIS AFFECTS

THESE TRIP POINTS

UPPER

ALARM

WINDOW

LOWER

TIME

SOFTWARE CLEARS EVENT

EVENT IN “INTERRUPT”

EVENT IN “COMPARATOR” MODE

EVENT IN “CRITICAL TEMP ONLY” MODE

*EVENT cannot be cleared once the DUT temperature is greater than the critical temperature

Figure 15. Event Detail

T

H

T

H − HYST

T

L

T

L − HYST

BELOW

WINDOW BIT

ABOVE

WINDOW BIT

Figure 16. Hysteresis Detail

http://onsemi.com

13

CAT6095

PACKAGE DIMENSIONS

TDFN8, 2x3

CASE 511AK−01

ISSUE A

D

A

e

b

E2

E

PIN#1

IDENTIFICATION

A1

PIN#1 INDEX AREA

D2

L

TOP VIEW

SIDE VIEW

BOTTOM VIEW

SYMBOL

MIN

0.70

0.00

0.45

NOM

MAX

0.80

0.05

0.65

A

A1

A2

A3

b

0.75

0.02

A2

0.55

0.20 REF

0.25

A3

0.20

1.90

1.30

2.90

1.20

0.30

2.10

1.50

3.10

1.40

D

2.00

FRONT VIEW

D2

E

1.40

3.00

E2

e

1.30

0.50 TYP

0.30

L

0.20

0.40

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MO-229.

http://onsemi.com

14

CAT6095

Example of Ordering Information

Prefix

Device #

Suffix

CAT

6095

VP2

G

T4

Package

Tape & Reel (Note 21)

Lead Finish

Company ID

VP2: TDFN

G: NiPdAu

T: Tape & Reel

4: 4,000/Reel

Product Number

6095

17.All packages are RoHS−compliant (Lead−free, Halogen−free)

18.The standard lead finish is NiPdAu.

19.This device used in the above example is a CAT6095, in TDFN, NiPdAu Lead Frame, Tape & Reel, 4,000/Reel.

20.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.

21.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

2

ON Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

CAT6095/D

http://onsemi.com

15


型号：	CAT6095VP2I-GT
厂家：	ONSEMI
描述：	Switch/Digital Output Temperature Sensor, DIGITAL TEMP SENSOR-SERIAL, 12BIT(s), RECTANGULAR, SURFACE MOUNT, 2 X 3 MM, 0.5 MM HEIGHT, ROHS COMPLIANT, TDFN, 8 PIN 输出元件传感器换能器
文件：	总15页 (文件大小：152K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CAT6095VP2I-GT [ONSEMI]

相关型号：

CAT6095VP2I-GT4

CAT6095_11

CAT6201

CAT6201VP2-GT3

CAT6201VP2.GT3

CAT6201VP2GT3

CAT6202

CAT6202VP2-GT3

CAT6202VP2.GT3

CAT6217

CAT6217

CAT6217-150TD-GT3