CAT6095VP2I-GT4 [ONSEMI]
Stand Alone Temp Sensor;
| 型号： | CAT6095VP2I-GT4 |
| 厂家： | 
ONSEMI |
| 描述： | Stand Alone Temp Sensor |
| 文件： | 总18页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT6095
Digital Output Temperature Sensor
FEATURES
DESCRIPTION
JEDEC JC42.4 Compliant Temperature Sensor
Temperature Range: - 40°C to 125°C
Supply Range: 3.3 V ± 10%
The CAT6095 is
Temperature Sensor designed for general purpose
temperature measurements requiring a digital output.
a
JEDEC JC42.4 compliant
I2C /SMBus Interface
The CAT6095 measures temperature at least 10
times every second. Temperature readings can be
retrieved by the host via the serial interface, and are
compared to high, low and critical trigger limits stored
into internal registers. Over or under limit conditions
Schmitt Triggers and Noise Suppression Filters
on SCL and SDA Inputs
Low Power CMOS Technology
RoHS-compliant 2 x 3 x 0.75 mm TDFN package
¯¯¯¯¯¯
can be signaled on the open-drain EVENT pin.
The CAT6095 is packaged in space saving TDFN
package with exposed backside die attach pads
(DAP). The exposed DAP reduces overall thermal
resistance, thus providing faster response to thermal
changes when compared to SOIC, TSSOP or SOT
packages.
For Ordering Information details, see page 17.
PIN CONFIGURATION
FUNCTIONAL SYMBOL
TDFN (VP2)
V
CC
A
A
A
V
CC
1
8
0
1
2
2
3
4
7
6
5
EVENT
SCL
SCL
V
SDA
SS
CAT6095
A , A , A
0
EVENT
2
1
Note: For the location of Pin 1, please consult the corresponding
SDA
package drawing.
PIN FUNCTIONS
V
SS
Name
Description
A0, A1, A2
Device Address Input
SDA
SCL
Serial Data Input/Output
Serial Clock Input
Open-drain Event Output
Power Supply
¯¯¯¯¯¯
EVENT
VCC
VSS
Ground
DAP
Backside exposed DAP at VSS
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-1124 Rev. D
CAT6095
ABSOLUTE MAXIMUM RATINGS(1)
Parameter
Rating
Unit
°C
°C
V
Operating Temperature
Storage Temperature
Voltage on any pin with respect to Ground(2)
-45 to +130
-65 to +150
-0.5 to +6.5
TEMPERATURE CHARACTERISTICS
VCC = 3.3 V ± 10%, TA = −40°C to +125°C, unless otherwise specified
Parameter
Test Conditions/Comments
75°C ≤ TA ≤ 95°C, active range
40°C ≤ TA ≤ 125°C, monitor range
-20°C ≤ TA ≤ 125°C, sensing range
Max
± 1.0
± 2.0
± 3.0
12
Unit
°C
Temperature Reading Error
Class B, JC42.4 compliant
°C
°C
ADC Resolution
Bits
°C
Temperature Resolution
Temperature Conversion Time
Thermal Resistance(3) θJA
0.0625
100
ms
Junction-to-Ambient (Still Air)
92
ºC/W
D.C. OPERATING CHARACTERISTICS
CC = 3.3 V ± 10%, TA = −40°C to +125°C, unless otherwise specified
V
Symbol Parameter
Test Conditions/Comments
TS active
Min
Max
Unit
μA
μA
μA
V
ICC
200
Supply Current
ISHDN
IL
TS shut-down; no bus activity
Pin at GND or VCC
5
5
I/O Pin Leakage Current
Input Low Voltage
VIL
-0.5
0.3 x VCC
VIH
VOL
Input High Voltage
Output Low Voltage
0.7 x VCC VCC + 0.5
0.4
V
IOL = 3 mA, VCC > 2.5 V
V
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. The A0 pin can be raised to a HV level
compatible with the use of a DDR3 SPD device sharing the bus with the TS. SCL and SDA inputs can be raised to the maximum limit,
irrespective of VCC
.
(3) Power Dissipation is defined as PJ = (TJ − TA)/θJA, where TJ is the junction temperature and TA is the ambient temperature. The thermal
resistance value refers to the case of a package being used on a standard 2-layer PCB.
Doc. No. MD-1124 Rev. D
2
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT6095
A.C. CHARACTERISTICS(1)
VCC = 3.3 V ± 10%, TA = −40°C to +125°C
Symbol Parameter
Min
10
Max
Units
kHz
ns
(2)
FSCL
tHIGH
tLOW
Clock Frequency
400
High Period of SCL Clock
600
1300
25
Low Period of SCL Clock
ns
(2)
tTIMEOUT
SMBus SCL Clock Low Timeout
SDA and SCL Rise Time
35
ms
ns
(3)
tR
300
300
(3)
tF
SDA and SCL Fall Time
ns
(4)
tSU:DAT
Data Setup Time
100
0
ns
Data Hold Time (for Input Data)
Data Hold Time (for Output Data)
START Condition Setup Time
START Condition Hold Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
Noise Pulse Filtered at SCL and SDA Inputs
Power-up Delay to Valid Temperature Recording
ns
(3)
tHD:DAT
300
600
600
600
1300
900
ns
tSU:STA
tHD:STA
tSU:STO
tBUF
ns
ns
ns
ns
Ti
100
100
ns
(5)
tPU
ms
PIN CAPACITANCE
V
CC = 3.3 V, TA = 25°C, f = 1 MHz
Symbol Parameter
¯¯¯¯¯¯
Test Conditions/Comments
Min
Max
Unit
pF
VIN = 0
VIN = 0
8
6
SDA, EVENT Pin Capacitance
CIN
Input Capacitance (other pins)
pF
Notes:
(1) Timing reference points are set at 30%, respectively 70% of VCC, as illustrated in Figure 4. Bus loading must be such as to allow meeting
the VIL, VOL as well as the various timing limits.
(2) The TS interface will reset itself and will release the SDA line if the SCL line stays low beyond the tTIMEOUT limit. The time-out count is
started (and then re-started) on every negative transition of SCL in the time interval between START and STOP.
(3) In a “Wired-OR” system (such as I2C or SMBus), SDA rise time is determined by bus loading. Since each bus pull-down device must be
able to sink the (external) bus pull-up current (in order to meet the VIL and/or VOL limits), it follows that SDA fall time is inherently faster
than SDA rise time. SDA rise time can exceed the standard recommended tR limit, as long as it does not exceed tLOW - tHD:DAT - tSU:DAT
,
where tLOW and tHD:DAT are actual values (rather than spec limits). A shorter tHD:DAT leaves more room for a longer SDA tR, allowing for a
more capacitive bus or a larger bus pull-up resistor. At the minimum tLOW spec limit of 1300 ns, the maximum tHD:DAT of 900 ns demands a
maximum SDA tR of 300 ns. The CAT6095’s maximum tHD:DAT is < 700 ns, thus allowing for an SDA tR of up to 500 ns at minimum tLOW
(4) The minimum tSU:DAT of 100 ns is a limit recommended by standards. The TS will accept a tSU:DAT of 0 ns.
(5) The first valid temperature recording can be expected after tPU at nominal supply voltage.
.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-1124 Rev. D
CAT6095
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, TA = −25°C to +125°C, unless otherwise specified.
Standby Current
(I²C-bus idle, TS shut-down)
TS Active Current
(I²C-bus idle)
300
250
200
150
100
50
5
4
3
2
1
0
0
-1
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TAMB (ºC)
TAMB (ºC)
SDA Output Current
¯¯¯¯¯¯
EVENT Output Current
60.0
50.0
40.0
30.0
20.0
10.0
0.0
100.0
VOL = 0.4 V
VOL = 0.6 V
80.0
60.0
40.0
20.0
0.0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TAMB (ºC)
TAMB (ºC)
Temperature Read-Out Error
A/D Conversion Time
4
3
80
70
60
50
40
30
20
2
1
Part # 2
0
Part # 1
-1
-2
-3
-4
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TAMB (ºC)
TAMB (ºC)
Doc. No. MD-1124 Rev. D
4
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT6095
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, TA = −25°C to +125°C, unless otherwise specified.
TS POR Threshold Voltage
SMBus SCL Clock Low Timeout
2.50
2.30
2.10
1.90
1.70
1.50
40
35
30
25
20
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
TAMB (ºC)
TAMB (ºC)
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-1124 Rev. D
CAT6095
PIN DESCRIPTION
I2C/SMBUS PROTOCOL
SCL: The Serial Clock input pin accepts the Serial
Clock generated by the Master (Host).
The I2C/SMBus uses two ‘wires’, one for clock (SCL)
and one for data (SDA). The two wires are
connected to the VCC supply via pull-up resistors.
Master and Slave devices connect to the bus via
their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
SDA: The Serial Data I/O pin receives input data
and transmits data stored in the internal registers. In
transmit mode, this pin is open drain. Data is
acquired on the positive edge, and is delivered on
the negative edge of SCL.
Data transfer may be initiated only when the bus is
not busy (see A.C. Characteristics).
A0, A1 and A2: The Address pins set the device
address. These pins have on-chip pull-down
resistors.
During data transfer, the SDA line must remain
stable while the SCL line is HIGH. An SDA transition
while SCL is HIGH will be interpreted as a START or
STOP condition (Figure 1).
¯¯¯¯¯¯
¯¯¯¯¯¯
EVENT: The open-drain EVENT pin can be
programmed to signal over/under temperature limit
conditions.
START
The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while
SCL is HIGH. The START acts as a ‘wake-up’ call to
all Slaves. Absent a START, a Slave will not
respond to commands.
POWER-ON RESET (POR)
The CAT6095 incorporates Power-On Reset (POR)
circuitry which monitors the supply voltage, and
then resets (initializes) the internal state machine
below (above) a POR trigger level of approximately
2.0 V, i.e. well below the minimum recommended
STOP
V
CC value.
The STOP condition completes all commands. It
consists of a LOW to HIGH transition on SDA while
SCL is HIGH. The STOP tells the Slave that no more
data will be written to or read from the Slave.
The TS powers-up into conversion mode. The
internal state machine will operate properly above
the POR trigger level, but valid temperature readings
can be expected only after the first conversion cycle
started and completed at nominal supply voltage.
DEVICE ADDRESSING
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. The first 4 bits of the Slave
address (the preamble) select the Temperature Sensor
(TS preamble = 0011) as shown in Figure 2. The next
3 bits, A2, A1 and A0, select one of 8 possible TS
DEVICE INTERFACE
The CAT6095 supports I2C and SMBus data
transmission protocols. These protocols describe
serial communication between transmitters and
receivers sharing a 2-wire data bus. Data flow is
controlled by a Master device, which generates the
serial clock and the START and STOP conditions.
The CAT6095 acts as a Slave device. Master and
Slave alternate as transmitter and receiver. Up to 8
CAT6095 devices may be present on the bus
simultaneously, and can be individually addressed
by matching the logic state of the address inputs A0,
A1, and A2.
¯¯
Slave devices. The last bit, R/W, specifies whether a
Read (1) or Write (0) operation is being performed
ACKNOWLEDGE
A matching Slave address is acknowledged (ACK)
by the Slave by pulling down the SDA line during the
9th clock cycle (Figure 3). After that, the Slave will
acknowledge all data bytes sent to the bus by the
Master. When t he Slave is the transmitter, the
Master will in turn acknowledge data bytes in the 9th
clock cycle. The Slave will stop transmitting after the
Master does not respond with acknowledge
(NoACK) and then issues a STOP. Bus timing is
illustrated in Figure 4.
Doc. No. MD-1124 Rev. D
6
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT6095
Figure 1. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 2. Slave Address Bits
TEMPERATURE SENSOR
0
0
1
1
A
A
A
0
R/W
2
1
PREAMBLE
DEVICE ADDRESS
Figure 3. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 4. Bus Timing
tF
tHIGH
tR
tLOW
70%
30%
70%
70%
70%
30%
SCL
SDA
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
70%
30%
70%
30%
70%
70%
30%
tBUF
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
7
Doc. No. MD-1124 Rev. D
CAT6095
WRITE OPERATIONS
Temperature Sensor Register Write
To write data to a TS register the Master creates a
START condition on the bus, and then sends out the
¯¯
appropriate Slave address (with the R/W bit set to
‘0’), followed by an address byte and two data bytes.
The matching Slave will acknowledge the Slave
address, TS register address and the TS register
data (Figure 5). The Master then ends the session
by creating a STOP condition on the bus. The STOP
completes the TS register update. Note that all
registers in the TS are ‘volatile’ meaning any data
contained in them is lost when power is removed
from the chip.
READ OPERATIONS
Immediate Read
Upon power-up, the Temperature Sensor (TS)
address counter is initialized to 00h. The TS address
counter will thus point to the Capability Register.
This address counter may be updated by
subsequent operations.
A CAT6095 presented with a Slave address
¯¯
containing a ‘1’ in the R/W position will acknowledge
the Slave address and will then start transmitting
data being pointed at by the current TS register
address counter. The Master stops this transmission
by responding with NoACK, followed by a STOP
(Figure 6).
Selective Read
The Read operation can be started at an address
different from the one stored in the address counter,
by preceeding the Immediate Read sequence with a
‘data less’ Write operation. The Master sends out a
START, Slave address and address byte, but rather
than following up with data (as in a Write operation),
the Master then issues another START and
continuous with an Immediate Read sequence
(Figure 7).
Doc. No. MD-1124 Rev. D
8
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT6095
Figure 5. Temperature Sensor Register Write
BUS ACTIVITY:
S
T
A
R
T
S
T
SLAVE
ADDRESS
REGISTER
ADDRESS
O
P
MASTER
SDA LINE
DATA (MSB)
DATA (LSB)
S
P
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
Figure 6. Immediate Read
BUS ACTIVITY:
S
T
A
R
T
N
O S
A
C
K
A
C
K
T
O
P
SLAVE
ADDRESS
MASTER
SDA LINE
S
P
A
C
K
SLAVE
DATA (MSB)
DATA (LSB)
Figure 7. Selective Read
BUS ACTIVITY:
S
T
A
R
T
S
T
A
R
T
N
S
T
O
A
C
K
REGISTER
ADDRESS
SLAVE
ADDRESS
SLAVE
ADDRESS
A
C
K
O
P
MASTER
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
DATA (MSB)
DATA (LSB)
SLAVE
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
9
Doc. No. MD-1124 Rev. D
CAT6095
TEMPERATURE SENSOR OPERATION
REGISTERS
The CAT6095 temperature sensor (TS) combines a
Proportional to Absolute Temperature (PTAT) sensor
with a ∑-Δ modulator, yielding a 12 bit plus sign digital
temperature representation.
The CAT6095 contains eight 16-bit wide registers
allocated to TS functions, as shown in Table 1. Upon
power-up, the internal address counter points to the
capability register.
Capability Register (User Read Only)
The TS runs on an internal clock, and starts a new
conversion cycle at least every 100 ms. The result of
the most recent conversion is stored in the
Temperature Data Register (TDR), and remains
there following a TS Shut-Down. Reading from the
TDR does not interfere with the conversion cycle.
This register lists the capabilities of the TS, as
detailed in the corresponding bit map.
Configuration Register (Read/Write)
This register controls the various operating modes of
the TS, as detailed in the corresponding bit map.
The value stored in the TDR is compared against
limits stored in the High Limit Register (HLR), the
Low Limit Register (LLR) and/or Critical
Temperature Register (CTR). If the measured value
is outside the alarm limits or above the critical limit,
Temperature Trip Point Registers (Read/Write)
The CAT6095 features 3 temperature limit registers,
the HLR, LLR and CLR mentioned earlier. The
temperature value recorded in the TDR is compared
to the various limit values, and the result is used to
¯¯¯¯¯¯
¯¯¯¯¯¯
then the EVENT pin may be asserted. The EVENT
output function is programmable, via the
Configuration Register for interrupt mode,
comparator mode and polarity.
¯¯¯¯¯¯
¯¯¯¯¯¯
activate the EVENT pin. To avoid undesirable EVENT
pin activity, this pin is automatically disabled at power-
up to allow the host to initialize the limit registers and
the converter to complete the first conversion cycle
under nominal supply conditions. Data format is two’s
complement with the LSB representing 0.25°C, as
detailed in the corresponding bit maps .
The temperature limit registers can be Read or
Written by the host, via the serial interface. At power-
on, all the (writable) internal registers default to
0x0000, and should therefore be initialized by the
¯¯¯¯¯¯
host to the desired values.The EVENT output starts
out disabled (corresponding to polarity active low);
thus preventing irrelevant event bus activity before the
limit registers are initialized. While the TS is enabled
(not shut-down), event conditions are normally
generated by a change in measured temperature as
recorded in the TDR, but limit changes can also
trigger events as soon as the new limit creates an
event condition, i.e. asynchronously with the
temperature sampling activity.
Temperature Data Register (User Read Only)
This register stores the measured temperature, as well
as trip status information. B15, B14 and B13 are the trip
status bits, representing the relationship between
measured temperature and the 3 limit values; these bits
are not affected by EVENT status or by Configuration
register settings. Measured temperature is represented
by bits B12 to B0. Data format is two’s complement,
where B12 represents the sign, B11 represents 128°C,
etc. and B0 represents 0.0625°C.
In order to minimize the thermal resistance between
sensor and PCB, it is recommended that the exposed
backside die attach pad (DAP) be soldered to the
PCB ground plane.
Manufacturer ID Register (Read Only)
The manufacturer ID assigned by the PCI-SIG trade
organization to the CAT6095 device is 0x1B09.
Device ID and Revision Register (Read Only)
This register contains manufacturer specific device ID
and device revision information.
Doc. No. MD-1124 Rev. D
10
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT6095
Table 1. Temperature Sensor Registers
Register Address Register Name
Power-On Default
0x005F
0x0000
Read/Write
Read
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08 –
Capability Register
Configuration Register
High Limit Register
Read/Write
Read/Write
Read/Write
Read/Write
Read
0x0000
Low Limit Register
0x0000
Critical Limit Register
Temperature Data Register
Manufacturer ID Register
Device ID/Revision Register
Reserved
0x0000
Undefined
0x1B09
0x0812
Read
Read
–
–
CAPABILITY REGISTER
B15
RFU
B7
B14
RFU
B13
RFU
B5
B12
RFU
B4
B11
RFU
B3
B10
RFU
B9
B8
RFU
B1
RFU
B6
B2
B0
EVSD
TMOUT
RFU
TRES [1:0]
RANGE
ACC
EVENT
Bit
Description
Reserved for future use; can not be written; should be ignored; will typically read as 0
B15:B8, B5
0: Configuration register bit 4 is frozen upon setting Configuration register bit 8 (i.e. a TS shut-
¯¯¯¯¯¯
down freezes the EVENT output)
B7(1)
B6
1: Configuration register bit 4 is cleared upon setting Configuration register bit 8 (i.e. a TS
¯¯¯¯¯¯
shut-down de-asserts the EVENT output)
0: The TS implements SMBus time-out within the range 10 to 60 ms
1: The TS implements SMBus time-out within the range 25 to 35 ms
00: LSB = 0.50°C (9 bit resolution)
01: LSB = 0.25°C (10 bit)
10: LSB = 0.125°C (11 bit)
11: LSB = 0.0625°C (12 bit)
B4:B3
0: Positive Temperature Only
1: Positive and Negative Temperature
B2
B1
B0
0: ±2°C over the active range and ±3°C over the operating range (Class C)
1: ±1°C over the active range and ±2°C over the monitor range (Class B)
0: Critical Temperature only
1: Alarm and Critical Temperature
Notes:
(1) Configuration Register bit 4 can be cleared (but not set) after Configuration Register bit 8 is set, by writing a “1” to Configuration Register
¯¯¯¯¯¯
bit 5 (i.e. the EVENT output can be de-asserted during TS shut-down periods)
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
11
Doc. No. MD-1124 Rev. D
CAT6095
CONFIGURATION REGISTER
B15
RFU
B7
B14
RFU
B6
B13
RFU
B5
B12
RFU
B4
B11
RFU
B3
B10
B2
B9
B1
B8
HYST [1:0]
SHDN
B0
TCRIT_LOCK EVENT_LOCK CLEAR EVENT_STS EVENT_CTRL TCRIT_ONLY EVENT_POL EVENT_MODE
Bit
Description
B15:B11 Reserved for future use ; can not be written ; should be ignored; will typically read as 0
00: Disable hysteresis
01: Set hysteresis at 1.5°C
B10:B9(1)
10: Set hysteresis at 3°C
11: Set hysteresis at 6°C
0: Thermal Sensor is enabled; temperature readings are updated at sampling rate
B8 (5)
1: Thermal Sensor is shut down; temperature reading is frozen to value recorded before SHDN
0: Critical trip register can be updated
1: Critical trip register cannot be modified; this bit can be cleared only at POR
B7 (4)
0: Alarm trip registers can be updated
1: Alarm trip registers cannot be modified; this bit can be cleared only at POR
B6 (4)
0: Always reads as 0 (self-clearing)
1: Writing a 1 to this position clears an event recording in interrupt mode only
B5 (3)
0: EVENT output pin is not being asserted
B4 (2)
1: EVENT output pin is being asserted
0: EVENT output disabled; polarity dependent: open-drain for bit B1 = 0 and grounded for B1 = 1
1: EVENT output enabled
B3 (1)
0: event condition triggered by alarm or critical temperature limit crossing
B2 (7)
1: event condition triggered by critical temperature limit crossing only
0: EVENT output active low
B1 (1), (6)
1: EVENT output active high
0: Comparator mode
B0 (1)
1: Interrupt mode
Notes:
(1) Can not be altered (set or cleared) as long as either one of the two lock bits, B6 or B7 is set.
¯¯¯¯¯¯
(2) This bit is a polarity independent ‘software’ copy of the EVENT pin, i.e. it is under the control of B3.
(3) Writing a ‘1’ to this bit clears an event condition in Interrupt mode, but has no effect in comparator mode. When read, this bit always
returns 0. Once the measured temperature exceeds the critical limit, setting this bit has no effect (see Figure 5).
(4) Cleared at power-on reset (POR). Once set, this bit can only be cleared by a POR condition.
(5) The TS powers up into active mode, i.e. this bit is cleared at power-on reset (POR). When the TS is shut down the ADC is disabled and
the temperature reading is frozen to the most recently recorded value. The TS can not be shut down (B8 can not be set) as long as either
one of the two lock bits, B6 or B7 is set. However, the bit can be cleared at any time.
¯¯¯¯¯¯
(6) The EVENT output is “open-drain” and requires an external pull-up resistor for either polarity. The “natural” polarity is “active low”, as it
allows “wired-or” operation on the EVENT bus.
(7) Can not be set as long as lock bit B6 is set.
Doc. No. MD-1124 Rev. D
12
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT6095
HIGH LIMIT REGISTER
B15
0
B14
0
B13
0
B12
Sign
B4
B11
128°C
B3
B10
64°C
B2
B9
32°C
B1
B8
16°C
B0
B7
8°C
B6
4°C
B5
2°C
1°C
0.5°C
0.25°C
0
0
LOW LIMIT REGISTER
B15
0
B14
0
B13
0
B12
Sign
B4
B11
128°C
B3
B10
64°C
B2
B9
32°C
B1
B8
16°C
B0
B7
8°C
B6
4°C
B5
2°C
1°C
0.5°C
0.25°C
0
0
TCRIT LIMIT REGISTER
B15
0
B14
0
B13
0
B12
Sign
B4
B11
128°C
B3
B10
64°C
B2
B9
32°C
B1
B8
16°C
B0
B7
8°C
B6
4°C
B5
2°C
1°C
0.5°C
0.25°C
0
0
TEMPERATURE DATA REGISTER
B15
TCRIT
B7
B14
HIGH
B6
B13
LOW
B5
B12
Sign
B4
B11
128°C
B3
B10
64°C
B2
B9
32°C
B1
B8
16°C
B0
8°C
4°C
2°C
1°C
0.5°C
0.25°C*
0.125°C* 0.0625°C*
* When applicable (as defined by Capability bit TRES), unsupported bits will read as 0
Bit
Description
0: Temperature is below the TCRIT limit
1: Temperature is equal to or above the TCRIT limit
B15
0: Temperature is equal to or below the High limit
1: Temperature is above the High limit
B14
B13
0: Temperature is equal to or above the Low limit
1: Temperature is below the Low limit
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
13
Doc. No. MD-1124 Rev. D
CAT6095
REGISTER DATA FORMAT
EVENT PIN FUNCTIONALITY
¯¯¯¯¯¯
The values used in the temperature data register and
the 3 temperature trip point registers are expressed in
two’s complement format. The measured temperature
value is expressed with 12-bit resolution, while the 3
trip temperature limits are set with 10-bit resolution. The
total temperature range is arbitrarily defined as 256°C,
thus yielding an LSB of 0.0625°C for the measured
temperature and 0.25°C for the 3 limit values. Bit B12 in
all temperature registers represents the sign, with a ‘0’
indicating a positive, and a ‘1’ a negative value. In two’s
complement format, negative values are obtained by
complementing their positive counterpart and adding a
‘1’, so that the sum of opposite signed numbers, but of
equal absolute value, adds up to zero.
The EVENT output reacts to temperature changes as
illustrated in Figure 8, and according to the operating
mode defined by the Configuration register.
¯¯¯¯¯¯
In Interrupt Mode, the enabled EVENT output will be
asserted every time the temperature crosses one of
the alarm window limits, and can be de-asserted by
writing a ‘1’ to the clear event bit (B5) in the
configuration register. When the temperature exceeds
the critical limit, the event remains asserted as long as
the temperature stays above the critical limit and can
not be cleared.
¯¯¯¯¯¯
In Comparator Mode, the EVENT output is asserted
outside the alarm window limits, while in Critical
¯¯¯¯¯¯
Note that trailing ‘0’ bits, are ‘0’ irrespective of polarity.
Therefore the don’t care bits (B1 and B0) in the 10-bit
resolution temperature limit registers, are always ‘0’.
Temperature Mode, EVENT is asserted only above
the critical limit. The exact trip limits are determined by
the 3 temperature limit settings and the hystersis
offsets, as illustrated in Figure 9.
12-Bit Temperature Data Format
Following a TS shut-down request, the converter is
stopped and the most recently recorded temperature
Binary (B12 to B0)
1 1100 1001 0000
1 1100 1110 0000
1 1110 0111 0000
1 1111 1111 1111
0 0000 0000 0000
0 0000 0000 0001
0 0001 1001 0000
0 0011 0010 0000
0 0111 1101 0000
Hex
1C90
1CE0
1E70
1FFF
000
Temperature
−55°C
¯¯¯¯¯¯
value present in the TDR is frozen; the EVENT output
will continue to reflect the state immediatelly
preceding the shut-down command. Therefore, if the
−50°C
−25°C
¯¯¯¯¯¯
state of the EVENT output creates an undesirable bus
−0.0625°C
0°C
condition, appropriate action must be taken either
before or after shutting down the TS. This may require
¯¯¯¯¯¯
clearing the event, disabling the EVENT output or
001
+0.0625°C
+25°C
¯¯¯¯¯¯
perhaps changing the EVENT output polarity.
190
320
+50°C
In normal use, events are triggered by a change in
recorded temperature, but the CAT6095 will also
respond to limit register changes. Whereas recorded
temperature values are updated at sampling rate
frequency, limits can be modified at any time. The
7D0
+125°C
¯¯¯¯¯¯
enabled EVENT output will react to limit changes as
soon as the respective registers are updated.This
feature may be useful during testing.
Doc. No. MD-1124 Rev. D
14
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT6095
Figure 8. Event Detail
TEMPERATURE
CRITICAL
HYSTERESIS AFFECTS
THESE TRIP POINTS
UPPER
ALARM
WINDOW
LOWER
TIME
SOFTWARE CLEARS EVENT
EVENT IN “INTERRUPT”
EVENT IN “COMPARATOR” MODE
EVENT IN “CRITICAL TEMP ONLY” MODE
1. EVENT CANNOT BE CLEARED ONCE THE DUT TEMPERATURE IS GREATER THAN
THE CRITICAL TEMPERATURE
Figure 9. Hysteresis Detail
T
H
T
H – HYST
T
L
T
L – HYST
BELOW
WINDOW BIT
ABOVE
WINDOW BIT
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
15
Doc. No. MD-1124 Rev. D
CAT6095
PACKAGE OUTLINE DRAWING
TDFN 8-Pad 2 x 3 x 0.75 mm (VP2) (1)(2)
D
A
e
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A2
A3
FRONT VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC standard MO-229.
Doc. No. MD-1124 Rev. D
16
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT6095
EXAMPLE OF ORDERING INFORMATION (1) - (4)
Prefix
Device # Suffix
CAT
6095
VP2
– G
T4
Optional
Group ID
Package
VP2: TDFN
Tape & Reel
T: Tape & Reel
4: 4,000/Reel
Product Number
Lead Finish
6095
G: NiPdAu
TOP MARKING
TDFN 8-Pad 2 x 3 x 0.75 mm
H
M
1
2
3
6
8
4
5
7
Top Mark Legend (Position)
1
5
2
6
7
8
Mark “HM”
3
4
Mark for traceability.
Production Year:
A 1 digit mark.
Production Month:
A 1 digit mark (1 - 9, A, B, C).
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT6095VP2-GT4 (i.e. TDFN, NiPdAu lead finish, Tape & Reel, 4,000/Reel).
(4) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
17
Doc. No. MD-1124 Rev. D
CAT6095
REVISION HISTORY
Date
Revision Description
16-Sep-08
3-Nov-08
A
B
Initial Release
Change logo and fine print to ON Semiconductor
Update Features, Description, Parametric Tables, TS functionality description, Add
Top Marking, Ordering Information, Align to JC42.4 TS3000 Standard terminology
01-May-09
05-Oct-09
C
D
Update Parametric Tables, Add Typical Performance Characteristics, Update
Package Outline Drawing, Update Example of Ordering Information
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to
any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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LITERATURE FULFILLMENT:
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For additional information, please contact your local
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Doc. No. MD-1124 Rev. D
18
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
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