CAT5411W-50-TE13_技术文档

CAT5411

Dual Digital

Potentiometer (POT)

with 64 Taps

and SPI Interface

Description

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The CAT5411 is two digital potentiometers (POTs) integrated with

control logic and 16 bytes of NVRAM memory. Each digital POT

consists of a series of 63 resistive elements connected between two

externally accessible end points. The tap points between each resistive

element are connected to the wiper outputs with CMOS switches. A

separate 6-bit control register (WCR) independently controls the

wiper tap switches for each digital POT. Associated with each wiper

control register are four 6-bit non-volatile memory data registers (DR)

used for storing up to four wiper settings. Writing to the wiper control

register or any of the non-volatile data registers is via a SPI serial bus.

On power-up, the contents of the first data register (DR0) for each of

the two potentiometers is automatically loaded into its respective

wiper control register.

TSSOP24

Y SUFFIX

CASE 948AR

SOIC−24

W SUFFIX

CASE 751BK

PIN CONNECTIONS

NC

V

CC

1

R

L0

The CAT5411 can be used as a potentiometer or as a two terminal,

variable resistor. It is intended for circuit level or system level

adjustments in a wide variety of applications.

R

H0

R

W0

A

0

CS

WP

SI

SO

CAT5411

Features

HOLD

SCK

NC

 Two Linear-taper Digital Potentiometers

 64 Resistor Taps per Potentiometer

A

1

R

L1

 End to End Resistance 2.5 kW, 10 kW, 50 kW or 100 kW

 Potentiometer Control and Memory Access via SPI Interface:

Mode (0, 0) and (1, 1)

NC

R

H1

NC

W1

NC

GND

 Low Wiper Resistance, Typically 80 W

 Nonvolatile Memory Storage for up to Four Wiper Settings for Each

Potentiometer

 Automatic Recall of Saved Wiper Settings at Power Up

 2.5 to 6.0 Volt Operation

 Standby Current less than 1 mA

 24-lead SOIC and 24-lead TSSOP

 Industrial Temperature Ranges

 These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS

Compliant

SOIC−24 (W)

(Top View)

SI

WP

CS

1

A

1

R

L1

H1

R

W0

R

H0

R

L0

R

W1

GND

NC

V

CC

CAT5411

NC

SCK

HOLD

A

SO

0

TSSOP24 (Y)

(Top View)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 12 of this data sheet.

 Semiconductor Components Industries, LLC, 2013

1

Publication Order Number:

July, 2013 − Rev. 13

CAT5411/D

CAT5411

MARKING DIAGRAMS

(SOIC−24)

(TSSOP−24)

L3B

CAT5411WT

−RRYMXXXX

RLB

CAT5411YT

3YMXXX

L = Assembly Location

3 = Lead Finish − Matte-Tin

B = Product Revision (Fixed as “B”)

CAT = Fixed as “CAT”

5411W = Device Code

T = Temperature Range (I = Industrial)

− = Dash

RR = Resistance

25 = 2.5 KW

10 = 10 KW

50 = 50 KW

R = Resistance

1 = 2.5 KW

2 = 10 KW

4 = 50 KW

5 = 100 KW

L = Assembly Location

B = Product Revision (Fixed as “B”)

CAT5411Y = Device Code

T = Temperature Range (I = Industrial)

3 = Lead Finish − Matte-Tin

Y = Production Year (Last Digit)

M = Production Month (1−9, O, N, D)

XXX = Last Three Digits of Assembly Lot Number

00 = 100 KW

Y = Production Year (Last Digit)

M = Production Month (1−9, O, N, D)

XXXX = Last Four Digits of Assembly Lot Number

R

H1

H0

CS

WIPER

CONTROL

REGISTERS

SCK

SI

SPI BUS

INTERFACE

R

W0

SO

W1

WP

A0

A1

NONVOLATILE

DATA

REGISTERS

CONTROL

LOGIC

R

L1

L0

Figure 1. Functional Diagram

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2

CAT5411

PIN DESCRIPTIONS

SI: Serial Input

HOLD: Hold

SI is the serial data input pin. This pin is used to input all

opcodes, byte addresses and data to be written to the

CAT5411. Input data is latched on the rising edge of the

serial clock.

The HOLD pin is used to pause transmission to the

CAT5411 while in the middle of a serial sequence without

having to re-transmit entire sequence at a later time. To

pause, HOLD must be brought low while SCK is low. The

SO pin is in a high impedance state during the time the part

is paused, and transitions on the SI pins will be ignored. To

resume communication, HOLD is brought high, while SCK

is low. (HOLD should be held high any time this function is

SO: Serial Output

SO is the serial data output pin. This pin is used to transfer

data out of the CAT5411. During a read cycle, data is shifted

out on the falling edge of the serial clock.

not being used.) HOLD may be tied high directly to V or

CC

tied to V through a resistor.

CC

SCK: Serial Clock

SCK is the serial clock pin. This pin is used to synchronize

the communication between the microcontroller and the

CAT5411. Opcodes, byte addresses or data present on the SI

pin are latched on the rising edge of the SCK. Data on the SO

pin is updated on the falling edge of the SCK.

Table 1. PIN CONNECTIONS

SOIC

TSSOP

Name

Function

Supply Voltage

1

2

19

20

V

CC

R

Low Reference Terminal

for Potentiometer 0

L0

H0

W0

A0, A1: Device Address Inputs

These inputs set the device address when addressing

multiple devices. A total of four devices can be addressed on

a single bus. A match in the slave address must be made with

the address input in order to initiate communication with the

CAT5411.

3

4

21

22

R

High Reference Terminal

for Potentiometer 0

R

Wiper Terminal for

Potentiometer 0

5

6

7

8

9

23

24

1

CS

WP

SI

Chip Select

Write Protection

Serial Input

R_H, R_L: Resistor End Points

The four sets of R and R pins are equivalent to the

H

L

terminal connections on a mechanical potentiometer.

2

A

1

Device Address

3

R

Low Reference Terminal

for Potentiometer 1

L1

R_W: Wiper

The four R pins are equivalent to the wiper terminal of

W

10

11

4

5

R

High Reference Terminal

for Potentiometer 1

H1

a mechanical potentiometer.

Wiper Terminal for

Potentiometer 1

CS: Chip Select

W1

CAT5251 and CS high disables the CAT5411. CS high

takes the SO output pin to high impedance and forces the

devices into a Standby mode (unless an internal write

operation is underway). The CAT5411 draws ZERO current

in the Standby mode. A high to low transition on CS is

required prior to any sequence being initiated. A low to high

transition on CS after a valid write sequence is what initiates

an internal write cycle.

12

13

14

15

16

17

18

19

20

21

22

23

24

6

GND

NC

Ground

7

No Connect

Bus Serial Clock

Hold

8

NC

9

NC

10

11

12

13

14

15

16

17

18

NC

SCK

HOLD

SO

WP: Write Protect

Serial Data Output

Device Address, LSB

No Connect

WP is the Write Protect pin. The Write Protect pin will

allow normal read/write operations when held high. When

WP is tied low, all non-volatile write operations to the Data

registers are inhibited (change of wiper control register is

allowed). WP going low while CS is still low will interrupt

a write to the registers. If the internal write cycle has already

been initiated, WP going low will have no effect on any write

operation.

A

0

NC

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3

CAT5411

DEVICE OPERATION

The CAT5411 is two resistor arrays integrated with SPI

transistor switch. Only one tap point for each potentiometer

is connected to its wiper terminal at a time and is determined

by the value of the wiper control register. Data can be read or

written to the wiper control registers or the non-volatile

memory data registers via the SPI bus. Additional instructions

allow data to be transferred between the wiper control

registers and each respective potentiometer’s non-volatile

data registers. Also, the device can be instructed to operate in

an “increment/decrement” mode.

serial interface logic, two 6-bit wiper control registers and

eight 6-bit, non-volatile memory data registers. Each resistor

array contains 63 separate resistive elements connected in

series. The physical ends of each array are equivalent to the

fixed terminals of a mechanical potentiometer (R and R ).

H

L

R and R are symmetrical and may be interchanged. The tap

H

L

positions between and at the ends of the series resistors are

connected to the output wiper terminals (R ) by a CMOS

W

SERIAL BUS PROTOCOL

The CAT5041 supports the SPI bus data transmission

protocol. The synchronous Serial Peripheral Interface (SPI)

helps the CAT5411 to interface directly with many of

today’s popular microcontrollers. The CAT5041 contains an

8-bit instruction register. The instruction set and the

operation codes are detailed in the instruction set Table 12.

After the device is selected with CS going low the first

byte will be received. The part is accessed via the SI pin, with

data being clocked in on the rising edge of SCK. The first

byte contains one of the six op-codes that define the

operation to be performed.

Table 2. RELIABILITY CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Symbol

(Note 1)

Parameter

Endurance

Reference Test Method

MIL−STD−883, Test Method 1033

MIL−STD−883, Test Method 1008

MIL−STD−883, Test Method 3015

JEDEC Standard 17

Min

1,000,000

100

Typ

Max

Units

Cycles/Byte

Years

N

END

TDR (Note 1)

Data Retention

ESD Susceptibility

Latch-up

V

(Note 1)

2000

Volts

ZAP

LTH

I

100

mA

1. This parameter is tested initially and after a design or process change that affects the parameter.

Table 3. ABSOLUTE MAXIMUM RATINGS

Parameters

Ratings

Units

C

V

Temperature Under Bias

−55 to +125

−65 to +150

Storage Temperature Range

Voltage to any Pins with Respect to V (Notes 2, 3)

−2.0 to V +2.0

SS

CC

V

with Respect to GND

−2.0 to +7.0

1.0

V

CC

Package Power Dissipation Capability (T = 25C)

W

A

Lead Soldering Temperature (10 s)

Wiper Current

300

C

mA

12

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

2. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC

voltage on output pins is V +0.5 V, which may overshoot to V +2.0 V for periods of less than 20 ns.

CC

3. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V +1 V.

CC

Table 4. RECOMMENDED OPERATING CONDITIONS

Parameters

Ratings

Units

V

CC

+2.5 to 6.0

Industrial Temperature

−40 to +85

C

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4

CAT5411

Table 5. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Symbol

Parameter

Test Conditions

Min

Typ

100

50

Max

Units

kW

%

R

Potentiometer Resistance (−00)

Potentiometer Resistance (−50)

Potentiometer Resistance (−10)

Potentiometer Resistance (−25)

Potentiometer Resistance Tolerance

POT

10

2.5

+20

1

R

Matching

%

POT

Power Rating

25C, each pot

50

mW

mA

W

I

W

Wiper Current

+6

R

Wiper Resistance

I

= +3 mA @ V = 3 V

300

150

W

CC

R

= +3 mA @ V = 5 V

80

W

CC

V

TERM

Voltage on any R or R Pin

V

SS

= 0 V

GND

V

CC

V

H

L

V

N

Noise

(Note 4)

nV/Hz

%

Resolution

1.6

Absolute Linearity (Note 5)

Relative Linearity (Note 6)

Temperature Coefficient of R

R

−R

+1

LSB

W(n)(actual)

(n)(expected)

(Note 8)

(Note 7)

R

W(n+1)

−[R ]

W(n)+LSB

+0.2

LSB

(Note 7)

(Note 8)

(Note 4)

TC

+300

ppm/C

pF

RPOT

POT

TC

Ratiometric Temp. Coefficient

Potentiometer Capacitances

Frequency Response

20

RATIO

C /C /C

H

10/10/25

0.4

L

W

fc

R

= 50 kW (Note 4)

MHz

POT

4. This parameter is tested initially and after a design or process change that affects the parameter.

5. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

6. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.

It is a measure of the error in step size.

7. LSB = R

/ 63 or (R − R ) / 63, single pot

TOT

H L

8. n = 0, 1, 2, ..., 63

Table 6. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Symbol

Parameter

Test Conditions

= 2 MHz, SO

SCK

Min

Max

Units

I

Power Supply Current

f

1

mA

CC

Open Inputs = GND

I

Standby Current (V = 5 V)

V

= GND or V ; SO Open

1

mA

V

SB

CC

IN

CC

I

Input Leakage Current

Output Leakage Current

Input Low Voltage

= GND to V

CC

10

LI

IN

I

LO

= GND to V

CC

OUT

V

−1

V

x 0.3

IL

CC

V

Input High Voltage

V

x 0.7

V

+ 1.0

V

IH

CC

V

OL1

Output Low Voltage (V = 3 V)

I = 3 mA

OL

0.4

V

CC

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5

CAT5411

Table 7. PIN CAPACITANCE (Note 9)

(Applicable over recommended operating range from T = 25C, f = 1.0 MHz, V = +5.0 V (unless otherwise noted).)

A

CC

Symbol

Test Conditions

Output Capacitance (SO)

Input Capacitance (CS, SCK, SI, WP, HOLD)

Min

Typ

Max

8

Units

pF

Conditions

= 0 V

C

V

OUT

C

6

pF

V

IN

= 0 V

IN

Table 8. POWER UP TIMING (Note 9) (Over recommended operating conditions unless otherwise stated.)

Symbol Parameter Min Typ

Power-up to Read Operation

Power-up to Write Operation

Max

1

Units

t

(Note 10)

ms

PUR

t

1

PUW

9. This parameter is tested initially and after a design or process change that affects the parameter.

10.t and t are the delays required from the time V is stable until the specified operation can be initiated.

PUR

PUW

CC

Table 9. ELECTRICAL CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Symbol

Parameter

Data Setup Time

Test Conditions

Min

50

Typ

Max

Units

ns

t

SU

t

H

Data Hold Time

50

ns

t

SCK High Time

125

DC

ns

WH

t

SCK Low Time

ns

WL

f

Clock Frequency

HOLD to Output Low Z

Input Rise Time

3

50

2

MHz

ns

SCK

t

LZ

t

RI

(Note 11)

ms

t

FI

Input Fall Time

2

ms

t

HOLD Setup Time

HOLD Hold Time

Write Cycle Time

Output Valid from Clock Low

Output Hold Time

Output Disable Time

HOLD to Output High Z

CS High Time

C = 50 pF

L

100

ns

HD

CD

ns

t

5

ms

ns

WC

t

V

250

t

0

ns

HO

t

250

100

ns

DIS

t

ns

HZ

t

250

ns

CS

t

CS Setup Time

ns

CSS

CSH

t

CS Hold Time

ns

11. This parameter is tested initially and after a design or process change that affects the parameter.

Table 10. POTENTIOMETER AC CHARACTERISTICS

Symbol

Parameter

Max

10

5

Units

ms

t

Wiper response time after instruction issued (all load instructions)

Wiper response time from an active SCK edge (Increment/decrement instruction)

WRL

t

ms

WRID

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6

CAT5411

t

CS

V

IH

CS

V

IL

t

CSH

CSS

V

IH

t

SCK

SI

WL

WH

V

IL

t

H

t

SU

V

IH

VALID IN

V

IL

t

RI

FI

t

V

t

DIS

HO

V

OH

HI−Z

SO

V

OL

Figure 2. Synchronous Data Timing

CS

t

CD

SCK

t

HD

t

HD

HOLD

SO

t

HZ

HIGH IMPEDANCE

t

LZ

Figure 3. HOLD Timing

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7

CAT5411

INSTRUCTION AND REGISTER DESCRIPTION

Instruction Byte

Device Type/Address Byte

The first byte sent to the CAT5411 from the master/

processor is called the Device Address Byte. The most

significant four bits of the Device Type address are a device

type identifier. These bits for the CAT5411 are fixed at

0101[B] (refer to Figure 4).

The two least significant bits in the slave address byte, A1

− A0, are the internal slave address and must match the

physical device address which is defined by the state of the A1

− A0 input pins for the CAT5411 to successfully continue the

command sequence. Only the device which slave address

matches the incoming device address sent by the master

executes the instruction. The A1 − A0 inputs can be actively

The next byte sent to the CAT5411 contains the instruction

and register pointer information. The four most significant

bits used provide the instruction opcode I [3:0]. The R1 and

R0 bits point to one of the four data registers of each

associated potentiometer. The least two significant bits point

to one of two Wiper Control Registers. The format is shown

in Figure 5.

Table 11. DATA REGISTER SELECTION

Data Register Selected

R1

0

R0

0

DR0

DR1

DR2

DR3

0

1

driven by CMOS input signals or tied to V or V . The

CC

SS

1

0

remaining two bits in the device address byte must be set to 0.

1

Device Type Identifier

Slave Address

ID3

0

ID2

1

ID1

ID0

0

A1

A0

0

1

(MSB)

(LSB)

Figure 4. Identification Byte Format 0101 Device Type Identifier (MSB)

Instruction Opcode

I2 I1

WCR/Pot Selection

Data Register Selection

R1 R0

I3

I0

0

P0

(MSB)

(LSB)

Figure 5. Instruction Byte Format

CS

SCK

. . .

t

WRL

MSB

LSB

SI

V /R

W

High Impedance

SO

Figure 6. Potentiometer Timing (for All Load Instructions)

WIPER CONTROL AND DATA REGISTERS

Wiper Control Register (WCR)

transferring the contents of one of four associated Data

Registers via the XFR Data Register instruction, it can be

modified one step at a time by the Increment/Decrement

instruction (see Instruction section for more details).

Finally, it is loaded with the content of its data register zero

(DR0) upon power-up.

The CAT5411 contains two 6-bit Wiper Control

Registers, one for each potentiometer. The Wiper Control

Register output is decoded to select one of 64 switches along

its resistor array. The contents of the WCR can be altered in

four ways: it may be written by the host via Write Wiper

Control Register instruction; it may be written by

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CAT5411

The Wiper Control Register is a volatile register that loses

Registers and the associated Wiper Control Register. Any

data changes in one of the Data Registers is a non-volatile

operation and will take a maximum of 5 ms.

its contents when the CAT5411 is powered-down. Although

the register is automatically loaded with the value in DR0

upon power-up, this may be different from the value present

at power-down.

Write in Process

The contents of the Data Registers are saved to

nonvolatile memory when the CS input goes HIGH after a

write sequence is received. The status of the internal write

cycle can be monitored by issuing a Read Status command

to read the Write in Process (WIP) bit.

Data Registers (DR)

Each potentiometer has four 6-bit non-volatile Data

Registers. These can be read or written directly by the host.

Data can also be transferred between any of the four Data

INSTRUCTIONS

Four of the ten instructions are three bytes in length. These

instructions are:

 Read Data Register – read the contents of the selected

Data Register

 Read Wiper Control Register – read the current wiper

position of the selected potentiometer in the WCR

 Write Data Register – write a new value to the

selected Data Register

 Write Wiper Control Register – change current wiper

 Read Status – Read the status of the WIP bit which

when set to “1” signifies a write cycle is in progress.

position in the WCR of the selected potentiometer

Table 12. INSTRUCTION SET (Note: 1/0 = data is one or zero)

Instruction Set

I3

I2 I1 I0

R1

R0

0

WCR / P0

Instruction

Operations

0

Read Wiper Control Register

1

0

1

0

1

0

1

0

1

0

1

0

1/0

Read the contents of the Wiper Control

Register pointed to by P0

Write Wiper Control Register

Read Data Register

1

0

Write new value to the Wiper Control Register

pointed to by P0

1/0

Read the contents of the Data Register pointed

to by P0 and R1−R0

Write Data Register

Write new value to the Data Register pointed

to by P0 and R1−R0

XFR Data Register to Wiper

Control Register

Transfer the contents of the Data Register

pointed to by P0 and R1−R0 to its associated

Wiper Control Register

XFR Wiper Control Register

to Data Register

1

0

1

0

1

0

1

0

1/0

0

1/0

0

Transfer the contents of the Wiper Control

Register pointed to by P0 to the Data Register

pointed to by R1−R0

Global XFR Data Registers

to Wiper Control Registers

Transfer the contents of the Data Registers

pointed to by R1−R0 of all four pots to their

respective Wiper Control Registers

Global XFR Wiper Control

Registers to Data Register

0

Transfer the contents of both Wiper Control

Registers to their respective data Registers

pointed to by R1−R0 of all four pots

Increment/Decrement

Wiper Control Register

0

1

0

1

0

1/0

1

Enable Increment/decrement of the Control

Latch pointed to by P0

Read Status

Read WIP bit to check internal write cycle

status

The basic sequence of the three byte instructions is

illustrated in Figure 8. These three-byte instructions

exchange data between the WCR and one of the Data

Registers. The WCR controls the position of the wiper. The

associated registers; or the transfer can occur between all

potentiometers and one associated register.

Four instructions require a two-byte sequence to

complete, as illustrated in Figure 7. These instructions

transfer data between the host/processor and the CAT5411;

either between the host and one of the data registers or

directly between the host and the Wiper Control Register.

These instructions are:

response of the wiper to this action will be delayed by t

.

WRL

A transfer from the WCR (current wiper position), to a Data

Register is a write to non-volatile memory and takes a

minimum of t

to complete. The transfer can occur

WR

between one of the four potentiometers and one of its

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9

CAT5411

Increment/Decrement Command

 XFR Data Register to Wiper Control Register

This transfers the contents of one specified Data

Register to the associated Wiper Control Register.

 XFR Wiper Control Register to Data Register

This transfers the contents of the specified Wiper

Control Register to the specified associated Data

Register.

 Global XFR Data Register to Wiper Control

Register

This transfers the contents of all specified Data

Registers to the associated Wiper Control Registers.

 Global XFR Wiper Counter Register to Data

Register

The final command is Increment/Decrement (Figures 9

and 10). The Increment/Decrement command is different

from the other commands. Once the command is issued the

master can clock the selected wiper up and/or down in one

segment steps; thereby providing a fine tuning capability to

the host. For each SCK clock pulse (t

HIGH, the selected wiper will move one resistor segment

) while SI is

HIGH

towards the R terminal. Similarly, for each SCK clock

H

pulse while SI is LOW, the selected wiper will move one

resistor segment towards the R terminal.

L

See Instructions format for more detail.

This transfers the contents of all Wiper Control Registers

to the specified associated Data Registers.

SI

0

1

0

1

0

ID3 ID2 ID1 ID0

A2 A1 A0

A3

I3 I2 I1

I0 R1 R0

P0

0

Internal

Address

Instruction

Opcode

Register

Address

Pot/WCR

Address

Device ID

Figure 7. Two-byte Instruction Sequence

0

1

0

1

0

SI

0

P0 D7 D6 D5 D4 D3 D2 D1 D0

I3 I2 I1 I0 R1 R0

ID3 ID2 ID1 ID0 A3 A2 A1 A0

Internal

Address

Device ID

Instruction

Opcode

Data

Register

Address

WCR[7:0]

or

Pot/WCR

Address

Data Register D[7:0]

Figure 8. Three-byte Instruction Sequence

0

1

0

1

0

SI

ID3 ID2 ID1 ID0

I1

A3 A2 A1 A0 I3 I2

I0

R1 R0

0

P0

I

D

E

C

1

I

D

E

C

n

N

C

1

N

C

2

N

C

n

Instruction

Opcode

Data

Register

Address

Pot/WCR

Address

Internal

Address

Device ID

Figure 9. Increment/Decrement Instruction Sequence

INC/DEC

Command

Issued

t

WRL

SCK

SI

Voltage Out

R

W

Figure 10. Increment/Decrement Timing Limits

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10

CAT5411

INSTRUCTION FORMAT

Table 13. READ WIPER CONTROL REGISTER (WCR)

CS

DEVICE ADDRESS

A1 A0

INSTRUCTION

DATA

CS

0

1

0

1

0

1

0

1

0

P0

1

7

0

6

0

5

4

3

2

1

0

Table 14. WRITE WIPER CONTROL REGISTER (WCR)

CS

DEVICE ADDRESS

A1 A0

INSTRUCTION

DATA

0

1

0

1

0

1

0

1

0

7

0

6

0

4

3

Table 15. READ DATA REGISTER (DR)

CS

DEVICE ADDRESS

A1 A0

INSTRUCTION

R1 R0

DATA

0

1

0

1

0

1

7

6

4

3

Table 16. WRITE DATA REGISTER (DR)

CS

DEVICE ADDRESS

A1 A0

INSTRUCTION

R1 R0

DATA

High

Voltage

Write

0

1

0

1

0

1

0

4

3

Cycle

Table 17. READ STATUS (WIP)

CS

DEVICE ADDRESS

A1 A0

INSTRUCTION

DATA

0

1

0

1

0

1

0

7

0

6

0

4

3

W

I

P

Table 18. GLOBAL TRANSFER DATA REGISTER (DR) TO WIPER CONTROL REGISTER (WCR)

CS

DEVICE ADDRESS

A1 A0

INSTRUCTION

R1 R0

CS

0

1

0

1

0

1

0

Table 19. GLOBAL TRANSFER WIPER CONTROL REGISTER (WCR) TO DATA REGISTER (DR)

CS

DEVICE ADDRESS

A1 A0

INSTRUCTION

R1 R0

CS

High

Voltage

Write

0

1

0

1

0

1

0

Cycle

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11

CAT5411

Table 20. TRANSFER WIPER CONTROL REGISTER (WCR) TO DATA REGISTER (DR)

CS

DEVICE ADDRESS

A1 A0

INSTRUCTION

R1 R0

CS

High

Voltage

Write

0

1

0

1

0

1

0

P0

Cycle

Table 21. TRANSFER DATA REGISTER (DR) TO WIPER CONTROL REGISTER (WCR)

CS

DEVICE ADDRESS

A1 A0

INSTRUCTION

R1 R0

CS

0

1

0

1

0

1

0

1

0

P0

Table 22. INCREMENT (I)/DECREMENT (D) WIPER CONTROL REGISTER (WCR)

CS

DEVICE ADDRESS

A1 A0

INSTRUCTION

DATA

. . .

CS

0

1

0

1

0

1

0

P0

I/D

NOTE: Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after CS goes high.

Table 23. ORDERING INFORMATION

†

Orderable Part Number

CAT5411WI-25-T1

CAT5411WI-10-T1

CAT5411WI-50-T1

CAT5411WI-00-T1

CAT5411YI-25-T2

CAT5411YI-10-T2

CAT5411YI-50-T2

CAT5411YI-00-T2

CAT5411WI25

Resistance (kW)

Lead Finish

Package

Shipping

2.5

10

SOIC−24

(Pb-Free)

1,000 / Tape & Reel

2,000 / Tape & Reel

31 Units / Tube

50

100

2.5

10

TSSOP24

(Pb-Free)

50

100

2.5

10

Matte-Tin

CAT5411WI10

SOIC−24

(Pb-Free)

CAT5411WI50

50

CAT5411WI00

100

2.5

10

CAT5411YI25

CAT5411YI10

TSSOP24

(Pb-Free)

62 Units / Tube

CAT5411YI50

50

CAT5411YI00

100

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

12.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device

Nomenclature document, TND310/D, available at www.onsemi.com.

13.All packages are RoHS-compliant (Pb-Free, Halogen Free).

14.The standard lead finish is Matte-Tin.

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12

CAT5411

PACKAGE DIMENSIONS

SOIC−24, 300 mils

CASE 751BK

ISSUE O

SYMBOL

MIN

NOM

MAX

2.65

0.30

2.55

0.51

0.33

15.40

10.51

7.60

2.35

A

A1

A2

b

0.10

2.05

0.31

0.20

15.20

10.11

7.34

E1

E

c

D

E

E1

e

1.27 BSC

h

0.25

0.40

0º

0.75

1.27

8º

L

b

e

θ

PIN#1 IDENTIFICATION

5º

15º

θ1

TOP VIEW

h

D

h

q1

A2

q

A

q1

L

c

A1

SIDE VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-013.

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13

CAT5411

PACKAGE DIMENSIONS

TSSOP24, 4.4x7.8

CASE 948AR

ISSUE A

b

SYMBOL

MIN

NOM

MAX

A

A1

A2

b

1.20

0.15

1.05

0.30

0.20

7.90

6.55

4.50

0.05

0.80

0.19

0.09

7.70

6.25

4.30

c

E1

E

D

7.80

6.40

E

E1

e

4.40

0.65 BSC

0.60

L

0.50

0.70

L1

1.00 REF

0º

8º

θ

e

TOP VIEW

D

c

A2

A

θ1

L

A1

L1

SIDE VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-153.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where

personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,

any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture

of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

CAT5411/D

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14


型号：	CAT5411W-50-TE13
厂家：	ONSEMI
描述：	DUAL 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, 0.300 INCH, SOIC-24 光电二极管转换器电阻器
文件：	总14页 (文件大小：189K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CAT5411W-50-TE13 [ONSEMI]

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