CAT5411WI-10 [ONSEMI]
Dual Digitally Programmable Potentiometers with 64 Taps and SPI Interface; 双数字可编程电位计与64丝锥和SPI接口
| 型号： | CAT5411WI-10 |
| 厂家： | 
ONSEMI |
| 描述： | Dual Digitally Programmable Potentiometers with 64 Taps and SPI Interface |
| 文件： | 总16页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT5411
Dual Digitally Programmable Potentiometers (DPP™)
with 64 Taps and SPI Interface
FEATURES
DESCRIPTION
The CAT5411 is two Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists
of a series of 63 resistive elements connected
between two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DPP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the two potentiometers is
automatically loaded into its respective wiper control
register.
Two linear-taper digitally programmable
potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5kΩ, 10kΩ, 50kΩ or
100kΩ
Potentiometer control and memory access via
SPI interface: Mode (0, 0) and (1, 1)
Low wiper resistance, typically 80
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
24-lead SOIC and 24-lead TSSOP
Industrial temperature ranges
The CAT5411 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
SOIC (W)
(top view)
TSSOP (Y)
(top view)
R
R
H1
H0
VCC
RL0
1
2
3
4
5
6
7
8
9
24 NC
¯¯¯
WP
SI
A1
1
2
3
4
5
6
7
8
9
24
23
CS
SCK
SI
WIPER
CONTROL
REGISTERS
SPI BUS
INTERFACE
23 NC
22 NC
21 NC
20 A0
¯¯¯
CS
R
R
W0
W1
RH0
RW0
SO
RL1
22 RW0
21 RH0
20 RL0
19 VCC
RH1
RW1
GND
NC
¯¯¯
CS
¯¯¯
WP
19 SO
CAT
CAT
5411 18
WP
A0
NONVOLATILE
DATA
REGISTERS
CONTROL
LOGIC
5411 18
¯¯¯¯¯
HOLD
NC
SI
A1
A1
NC
17 NC
16 NC
15 NC
14 A0
17 SCK
NC
RL1
16 NC
15 NC
14 NC
13 NC
R
R
L1
L0
NC 10
RH1 10
RW1 11
SCK 11
For Ordering Information details, see page 15.
¯¯¯¯¯
HOLD
12
13 SO
GND 12
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-2114 Rev. K
CAT5411
PIN DESCRIPTIONS
SI: Serial Input
Pin
Pin
Name Function
SOIC TSSOP
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses and data to be written to the
CAT5411. Input data is latched on the rising edge of the
serial clock.
1
2
19
20
VCC
RL0
Supply Voltage
Low Reference Terminal for
Potentiometer 0
High Reference Terminal for
Potentiometer 0
SO: Serial Output
3
4
21
22
RH0
SO is the serial data output pin. This pin is used to transfer
data out of the CAT5411. During a read cycle, data is
shifted out on the falling edge of the serial clock.
Wiper Terminal for
Potentiometer 0
RW0
¯¯¯
CS
5
6
7
8
23
24
1
Chip Select
SCK: Serial Clock
¯¯¯
WP
Write Protection
Serial Input
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT5411. Opcodes, byte addresses or data present on
the SI pin are latched on the rising edge of the SCK. Data
on the SO pin is updated on the falling edge of the SCK.
SI
A1
2
Device Address
Low Reference Terminal for
Potentiometer 1
9
3
4
5
RL1
RH1
RW1
High Reference Terminal for
Potentiometer 1
10
11
A0, A1: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of four devices can be addressed
on a single bus. A match in the slave address must be
made with the address input in order to initiate
communication with the CAT5411.
Wiper Terminal for
Potentiometer 1
12
13
14
15
16
17
18
19
20
21
22
23
24
6
GND Ground
7
NC
NC
No Connect
8
No Connect
RH, RL: Resistor End Points
The four sets of RH and RL pins are equivalent to the
terminal connections on a mechanical potentiometer.
9
NC
No Connect
10
11
12
13
14
15
16
17
18
NC
No Connect
SCK
Bus Serial Clock
Hold
RW: Wiper
¯¯¯¯¯
HOLD
The four RW pins are equivalent to the wiper terminal of a
mechanical potentiometer.
SO
A0
Serial Data Output
Device Address, LSB
No Connect
¯C¯S¯: Chip Select
CAT5251 and ¯C¯S¯ high disables the CAT5411. CS high
takes the SO output pin to high impedance and forces the
devices into a Standby mode (unless an internal write
operation is underway). The CAT5411 draws ZERO
current in the Standby mode. A high to low transition on
NC
NC
NC
NC
¯¯¯
No Connect
No Connect
No Connect
¯¯¯
CS is required prior to any sequence being initiated. A low
¯¯¯¯¯
HOLD: Hold
¯¯¯
to high transition on CS after a valid write sequence is
what initiates an internal write cycle.
¯¯¯¯¯
The HOLD pin is used to pause transmission to the
CAT5411 while in the middle of a serial sequence without
having to re-transmit entire sequence at a later time. To
¯¯¯
WP: Write Protect
¯¯¯
WP is the Write Protect pin. The Write Protect pin will
¯¯¯¯¯
pause, HOLD must be brought low while SCK is low. The
allow normal read/write operations when held high.
SO pin is in a high impedance state during the time the part
is paused, and transitions on the SI pins will be ignored. To
¯¯¯¯¯
resume communication, HOLD is brought high, while SCK
¯¯¯¯¯
is low. (HOLD should be held high any time this function is
not being used.) HOLD may be tied high directly to VCC or
¯¯¯
When WP is tied low, all non-volatile write operations to
the Data registers are inhibited (change of wiper control
¯¯¯
¯¯¯
register is allowed). WP going low while CS is still low will
interrupt a write to the registers. If the internal write cycle
¯¯¯¯¯
¯¯¯
has already been initiated, WP going low will have no
tied to VCC through a resistor.
effect on any write operation.
Doc. No. MD-2114 Rev. K
2
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT5411
DEVICE OPERATION
SERIAL BUS PROTOCOL
The CAT5411 is two resistor arrays integrated with
SPI serial interface logic, two 6-bit wiper control
registers and eight 6-bit, non-volatile memory data
registers. Each resistor array contains 63 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL).
RH and RL are symmetrical and may be interchanged.
The tap positions between and at the ends of the
series resistors are connected to the output wiper
terminals (RW) by a CMOS transistor switch. Only one
tap point for each potentiometer is connected to its
wiper terminal at a time and is determined by the
value of the wiper control register. Data can be read
or written to the wiper control registers or the non-
volatile memory data registers via the SPI bus.
Additional instructions allow data to be transferred
between the wiper control registers and each
respective potentiometer's non-volatile data registers.
Also, the device can be instructed to operate in an
"increment/decrement" mode.
The CAT5041 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5411 to interface directly with
many
of
today's
popular
microcontrollers.
The CAT5041 contains an 8-bit instruction register.
The instruction set and the operation codes are
detailed in the instruction set table 3.
¯¯¯
After the device is selected with CS going low the first
byte will be received. The part is accessed via the SI
pin, with data being clocked in on the rising edge of
SCK. The first byte contains one of the six op-codes
that define the operation to be performed.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Reference Test Method
Min
1,000,000
100
Typ
Max
Units
Cycles/Byte
Years
(1)
NEND
Endurance
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
TDR(1)
Data Retention
ESD Susceptibility
Latch-Up
(1)
VZAP
2000
Volts
(1)
ILTH
100
mA
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-2114 Rev. K
CAT5411
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDITIONS
Parameters
Ratings
Units
Parameters
Ratings
+2.5 to 6.0
-40 to +85
Units
V
Temperature Under Bias
Storage Temperature
Range
-55 to +125
ºC
VCC
Industrial Temperature
ºC
-65 to +150
ºC
Notes:
(1) Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions outside of those listed in the
operational sections of this specification is not implied.
Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Voltage to any Pins with
Respect to VSS
-2.0 to VCC
+2.0
V
V
(2) (3)
VCC with Respect to GND
-2.0 to +7.0
Package Power Dissipa-
tion Capability (TA = 25°C)
1.0
W
Lead Soldering
Temperature (10s)
(2) The minimum DC input voltage is –0.5V. During transitions,
inputs may undershoot to –2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is VCC +0.5V, which may
overshoot to VCC +2.0V for periods of less than 20 ns.
300
±12
ºC
Wiper Current
mA
(3) Latch-up protection is provided for stresses up to 100 mA on
address and data pins from –1V to VCC +1V.
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Test Conditions
Min
Typ
100
50
Max
Units
kΩ
RPOT
RPOT
RPOT
RPOT
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance (-10)
Potentiometer Resistance (-2.5)
kΩ
10
kΩ
2.5
kΩ
Potentiometer Resistance
Tolerance
+20
%
RPOT Matching
1
%
mW
Power Rating
25°C, each pot
50
IW
RW
Wiper Current
+6
mA
Wiper Resistance
Wiper Resistance
Voltage on any RH or RL Pin
Noise
IW = +3mA @ VCC = 3V
IW = +3mA @ VCC = 5V
300
150
VCC
Ω
RW
80
1.6
Ω
VTERM
VN
VSS = 0V
(1)
GND
V
nV/√Hz
%
Resolution
(5)
Absolute Linearity (2)
Relative Linearity (3)
Temperature Coefficient of RPOT
Ratiometric Temp. Coefficient
RW(n)(actual)-R(n)(expected)
+1
LSB (4)
LSB (4)
ppm/°C
ppm/°C
pF
(5)
RW(n+1)-[RW(n)+LSB
]
+0.2
(1)
TCRPOT
TCRATIO
+300
(1)
(1)
20
CH/CL/CW Potentiometer Capacitances
fc Frequency Response
10/10/25
0.4
RPOT = 50kΩ(1)
MHz
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(4) LSB = RTOT / 63 or (RH - RL) / 63, single pot
(5) n = 0, 1, 2, ..., 63
Doc. No. MD-2114 Rev. K
4
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT5411
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Test Conditions
SCK = 2MHz, SO
Open Inputs = GND
Min
Max
Units
f
ICC
Power Supply Current
1
mA
ISB
ILI
Standby Current (VCC = 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND or VCC; SO Open
1
µA
µA
µA
VIN = GND to VCC
VOUT = GND to VCC
10
10
ILO
VIL
VIH
VOL1
-1
VCC x 0.3
V
V
V
Input High Voltage
VCC x 0.7 VCC + 1.0
0.4
Output Low Voltage (VCC = 3.0V) IOL = 3 mA
PIN CAPACITANCE(1)
Applicable over recommended operating range from TA = 25˚C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol Test Conditions
Min
Typ
Max
8
Units Conditions
COUT
CIN
Output Capacitance (SO)
¯¯¯
pF
pF
VOUT = 0V
VIN = 0V
¯¯¯ ¯¯¯¯¯
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
POWER UP TIMING (1)
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Min
Typ
Max
1
Units
ms
(2)
tPUR
Power-up to Read Operation
Power-up to Write Operation
(2)
tPUW
1
ms
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
t
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-2114 Rev. K
CAT5411
ELECTRICAL CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
tSU Data Setup Time
tH
Min
50
Typ
Max
Units
ns
Test Conditions
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
50
ns
tWH
tWL
fSCK
tLZ
125
125
DC
ns
ns
3
50
2
MHz
ns
¯¯¯¯¯
HOLD to Output Low Z
(1)
tRI
Input Rise Time
Input Fall Time
µs
(1)
tFI
2
µs
¯¯¯¯¯
tHD
tCD
tWC
tV
100
100
ns
CL = 50pF
HOLD Setup Time
¯¯¯¯¯
HOLD Hold Time
ns
Write Cycle Time
5
ms
ns
Output Valid from Clock Low
Output Hold Time
250
tHO
tDIS
tHZ
0
ns
Output Disable Time
250
100
ns
¯¯¯¯¯
HOLD to Output High Z
ns
¯¯¯
tCS
tCSS
tCSH
250
250
250
ns
CS High Time
¯¯¯
ns
CS Setup Time
¯¯¯
CS Hold Time
ns
POTENTIOMETER AC CHARACTERISTICS
Symbol Parameter
Max Units
tWRL
Wiper response time after instruction issued (all load instructions)
Wiper response time from an active SCK edge (Increment/decrement instruction)
10
5
µs
µs
tWRID
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-2114 Rev. K
6
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT5411
Figure 1: Synchronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
H
t
SU
VIH
VALID IN
V
IL
t
RI
t
FI
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
¯¯¯¯¯
Figure 2: HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
7
Doc. No. MD-2114 Rev. K
CAT5411
INSTRUCTION AND REGISTER
DESCRIPTION
INSTRUCTION BYTE
The next byte sent to the CAT5411 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I [3:0]. The R1 and R0 bits point to one of the
four data registers of each associated potentiometer.
The least two significant bits point to one of two Wiper
Control Registers. The format is shown in Table 2.
DEVICE TYPE / ADDRESS BYTE
The first byte sent to the CAT5411 from the master/
processor is called the Device Address Byte. The
most significant four bits of the Device Type address
are a device type identifier. These bits for the
CAT5411 are fixed at 0101[B] (refer to Table 1).
Data Register Selection
The two least significant bits in the slave address
byte, A1 - A0, are the internal slave address and must
match the physical device address which is defined by
the state of the A1 - A0 input pins for the CAT5411 to
successfully continue the command sequence. Only
the device which slave address matches the incoming
device address sent by the master executes the
instruction. The A1 - A0 inputs can be actively driven
by CMOS input signals or tied to VCC or VSS. The
remaining two bits in the device address byte must be
set to 0.
Data Register Selected
R1
0
R0
0
DR0
DR1
DR2
DR3
0
1
1
0
1
1
Table 1. Identification Byte Format 0101 Device Type Identifier (MSB)
Device Type
Identifier
Slave Address
ID3
0
ID2
1
ID1
0
ID0
0
0
A1
A0
1
(MSB)
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
WCR/Pot
Selection
Data Register
Selection
I3
I2
I1
I0
R1
R0
0
P0
(MSB)
(LSB)
Figure 3. Potentiometer Timing (for All Load Instructions)
CS
SCK
• • •
t
WRL
• • •
MSB
LSB
SI
V
/R
W
W
High Impedance
SO
Doc. No. MD-2114 Rev. K
8
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT5411
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
Write in Process
The contents of the Data Registers are saved to
The CAT5411 contains two 6-bit Wiper Control
Registers, one for each potentiometer. The Wiper
Control Register output is decoded to select one of 64
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written by
the host via Write Wiper Control Register instruction; it
may be written by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction, it can be modified one step at a
time by the Increment/decrement instruction (see
Instruction section for more details). Finally, it is
loaded with the content of its data register zero (DR0)
upon power-up.
¯¯¯
nonvolatile memory when the CS input goes HIGH
after a write sequence is received. The status of the
internal write cycle can be monitored by issuing a
Read Status command to read the Write in Process
(WIP) bit.
INSTRUCTIONS
Four of the ten instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register – read the current
wiper position of the selected potentiometer in
the WCR
The Wiper Control Register is a volatile register that
loses its contents when the CAT5411 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
— Write Wiper Control Register – change current
wiper position in the WCR of the selected
potentiometer
— Read Data Register – read the contents of the
selected Data Register
Data Registers (DR)
— Write Data Register – write a new value to the
Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data
Registers is a non-volatile operation and will take a
maximum of 5ms.
selected Data Register
— Read Status – Read the status of the WIP bit
which when set to "1" signifies a write cycle is in
progress.
Table 3. Instruction Set
Note: 1/0 = data is one or zero
Instruction Set
Instruction
Read Wiper Control Register 1
Operations
I3
I2 I1 I0 R1 R0
0
WCR0/ P0
Read the contents of the Wiper Control Register
pointed to by P0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
1/0
Write new value to the Wiper Control Register
pointed to by P0
Write Wiper Control Register
Read Data Register
1
1
1
0
0
0
1/0
1/0
1/0
Read the contents of the Data Register pointed to by
P0 and R1-R0
1 1/0 1/0
0 1/0 1/0
Write new value to the Data Register pointed to by
P0 and R1-R0
Write Data Register
Transfer the contents of the Data Register pointed to
by P0 and R1-R0 to its associated Wiper Control
Register
XFR Data Register to Wiper
Control Register
1
1
0
1
1
1
0
0
0
1
0
0
1 1/0 1/0
0 1/0 1/0
1 1/0 1/0
0 1/0 1/0
0
0
0
0
1/0
1/0
0
Transfer the contents of the Wiper Control Register
pointed to by P0 to the Data Register pointed to by
R1-R0
XFR Wiper Control Register
to Data Register
Transfer the contents of the Data Registers pointed to
by R1-R0 of all four pots to their respective Wiper
Control Registers
Global XFR Data Registers
to Wiper Control Registers
Transfer the contents of both Wiper Control Registers
to their respective data Registers pointed to by
R1-R0 of all four pots
Global XFR Wiper Control
Registers to Data Register
0
Increment/Decrement Wiper
Control Register
Read Status
Enable Increment/decrement of the Control Latch
pointed to by P0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
1/0
1
Read WIP bit to check internal write cycle status
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
9
Doc. No. MD-2114 Rev. K
CAT5411
The basic sequence of the three byte instructions is
illustrated in Figure 5. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be
delayed by tWRL. A transfer from the WCR (current
wiper position), to a Data Register is a write to non-
volatile memory and takes a minimum of tWR to
complete. The transfer can occur between one of the
four potentiometers and one of its associated
registers; or the transfer can occur between all
potentiometers and one associated register.
— Global XFR Data Register to Wiper Control
Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
— Global XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 6
and 7). The Increment/Decrement command is
different from the other commands. Once the com-
mand is issued the master can clock the selected
wiper up and/or down in one segment steps; thereby
providing a fine tuning capability to the host. For each
SCK clock pulse (tHIGH) while SI is HIGH, the selected
wiper will move one resistor segment towards the RH
terminal. Similarly, for each SCK clock pulse while SI
is LOW, the selected wiper will move one resistor
segment towards the RL terminal.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 4. These instructions
transfer data between the host/processor and the
CAT5411; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
See Instructions format for more detail.
Figure 4. Two-Byte Instruction Sequence
SI
0
1
0
1
0
0
ID3 ID2 ID1 ID0
A2 A1 A0
A3
I3 I2 I1
I0
R1 R0
0
P0
Internal
Address
Instruction
Opcode
Register
Address
Pot/WCR
Address
Device ID
Figure 5. Three-Byte Instruction Sequence
0
1
0
1
0
0
SI
I3
I1
0 P0 D7 D6 D5 D4 D3 D2 D1 D0
I2
I0 R1 R0
ID3 ID2
ID0 A3 A2 A1 A0
Internal
ID1
Device ID
Instruction
Opcode
Data
Pot/WCR
Register Address
Address
WCR[7:0]
or
Address
Data Register D[7:0]
Figure 6. Increment/Decrement Instruction Sequence
0
1
0
1
0
0
SI
ID3 ID2 ID1 ID0
Device ID
I1
A3 A2 A1 A0 I3
I2
I0
R1 R0
0
P0
I
N
C
I
D
E
C
1
I
D
E
C
n
N
C
2
N
C
n
Instruction
Opcode
Pot/WCR
Address 1
Data
Register
Address
Internal
Address
Doc. No. MD-2114 Rev. K
10
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT5411
Figure 7. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
t
WRL
SCK
SI
Voltage Out
R
W
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
DEVICE ADDRESS
INSTRUCTION
DATA
0 P0 7 6 5 4 3 2 1
0 0
0 1 0 1 0 0 A1 A0 1 0 0 1
0
0
0
0
0
0
¯¯¯
CS
¯¯¯
CS
Write Wiper Control Register (WCR)
DEVICE ADDRESS
INSTRUCTION
DATA
0 P0 7 6 5 4 3 2 1
0 0
0 1 0 1 0 0 A1 A0 1 0 1 0
0
0
¯¯¯
CS
¯¯¯
CS
Read Data Register (DR)
DEVICE ADDRESS
INSTRUCTION
DATA
0 1 0 1 0 0 A1 A0 1 0 1 1 R1 R0 0 P0 7 6 5 4 3 2 1
¯¯¯
CS
¯¯¯
CS
Write Data Register (DR)
DEVICE ADDRESS
INSTRUCTION
DATA
0 1 0 1 0 0 A1 A0 1 1 0 0 R1 R0 0 P0 7 6 5 4 3 2 1
High Voltage
Write Cycle
¯¯¯
CS
¯¯¯
CS
Read Status (WIP)
DEVICE ADDRESS
0 1 0 1 0 0 A1 A0 0 1 0 1
INSTRUCTION
DATA
7 6 5 4 3 2 1 W
0
0
0
1
¯¯¯
CS
¯¯¯
CS
0 0
I
P
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
11
Doc. No. MD-2114 Rev. K
CAT5411
INSTRUCTION FORMAT (CONTINUED)
Global Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESS
A1 A0
INSTRUCTION
R1 R0
0
1
0
1
0
0
0
0
0
1
0
0
¯¯¯
CS
¯¯¯
CS
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESS INSTRUCTION
A1 A0 R1 R0
0
1
0
1
0
0
1
0
0
0
0
0
High Voltage
Write Cycle
¯¯¯
CS
¯¯¯
CS
Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESS INSTRUCTION
A1 A0 R1 R0
0
1
0
1
0
0
1
1
1
0
0
P0
P0
High Voltage
Write Cycle
¯¯¯
CS
¯¯¯
CS
Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESS INSTRUCTION
A1 A0 R1 R0
0
1
0
1
0
0
1
1
0
1
0
0
¯¯¯
CS
¯¯¯
CS
Increment (I)/Decrement (D) Wiper Control Register (WCR)
DEVICE ADDRESS INSTRUCTION
A1 A0
DATA
0
1
0
1
0
0
0
0
1
0
0
0
P0 I/D I/D
I/D I/D
¯¯¯
CS
¯¯¯
CS
• • •
Note:
¯¯¯
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after CS goes high.
Doc. No. MD-2114 Rev. K
12
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT5411
PACKAGE OUTLINE DRAWINGS
SOIC 24-LEAD 300 mil (W)(1)(2)
SYMBOL
MIN
2.35
0.10
2.05
0.31
0.20
15.20
10.11
7.34
NOM
MAX
2.65
0.30
2.55
0.51
0.33
15.40
10.51
7.60
A
A1
A2
b
E1
E
c
D
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.75
1.27
8°
b
e
L
θ
PIN#1 IDENTIFICATION
θ1
5°
15°
TOP VIEW
h
D
h
θ1
A2
A
θ
θ1
L
c
A1
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
13
Doc. No. MD-2114 Rev. K
CAT5411
TSSOP 24-LEAD (Y) (1)(2)
b
SYMBOL
MIN
NOM
MAX
1.20
0.15
1.05
0.30
0.20
7.90
6.55
4.50
A
A1
A2
b
0.05
0.80
0.19
0.09
7.70
6.25
4.30
c
E1
E
D
7.80
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
θ1
0.50
0°
0.70
8°
e
TOP VIEW
D
c
A2
A1
A
θ1
L1
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
Doc. No. MD-2114 Rev. K
14
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT5411
EXAMPLE OF ORDERING INFORMATION(1)
Prefix
Device #
Suffix
CAT
5411
W
I
-10
–
T1
Temperature Range
I = Industrial (-40ºC to 85ºC)
Tape & Reel
T: Tape & Reel
Company ID
1: 1,000/Reel - SOIC
2: 2,000/Reel - TSSOP
Product Number
Resistance
-25: 2.5kꢀ
-10: 10kꢀ
-50: 50kꢀ
-00: 100kꢀ
Package
W: SOIC
Y: TSSOP
Ordering Part Number
CAT5411WI-25
CAT5411WI-10
CAT5411WI-50
CAT5411WI-00
CAT5411YI-25
CAT5411YI-10
CAT5411YI-50
CAT5411YI-00
Resistor [kꢀ]
2.5
10
50
100
2.5
10
50
100
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is Matte-Tin.
(3) The device used in the above example is a CAT5411WI-10-T1 (SOIC, Industrial Temperature, 10kꢀ, Tape & Reel, 1,000/Reel).
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
15
Doc. No. MD-2114 Rev. K
CAT5411
REVISION HISTORY
Date
Rev.
Description
01-Apr-04
G
Eliminate data sheet designation
Update Features
Update Description
Update Pin Description
Update Absolute Maximum Ratings
Update Recommended Operating Conditions
Update Potentiometer Characteristics Update Reliability Characteristics
Update Ordering Information
22-May-07
31-Oct-07
H
I
Update Package Outline Drawings
Update Example of Ordering Information
Add MD- to document number
Update Package Outline Drawings
Update Example of Ordering Information
27-Aug-08
25-Nov-08
J
Update Tables 2 and 3 and Figures 5 and 6
K
Change logo and fine print to ON Semiconductor
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to
any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800-282-9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center:
Phone: 81-3-5773-3850
ON Semiconductor Website: www.onsemi.com
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
Doc. No. MD-2114 Rev. K
16
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
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