B300W35A102XXG [ONSEMI]
IC,AUDIO PROCESSOR,BGA,35PIN,PLASTIC;
| 型号： | B300W35A102XXG |
| 厂家： | 
ONSEMI |
| 描述： | IC,AUDIO PROCESSOR,BGA,35PIN,PLASTIC 商用集成电路 |
| 文件： | 总28页 (文件大小：660K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BelaSigna 300
Audio Processor for Portable Communication Devices
1.0 General Overview
1.1 Introduction
BelaSigna 300 is a DSP-based mixed-signal audio processing system that delivers superior audio clarity without compromising size or
battery life. The processor is specifically designed for monaural portable communication devices requiring high performance audio
processing capabilities and programming flexibility when form-factor and power consumption are key design constraints.
The efficient dual-MAC 24-bit CFX DSP core, together with the HEAR configurable accelerator signal processing engine, high speed
debugging interface, advanced algorithm security system, state-of-the-art analog front end, Class D output stage and much more,
constitute an entire system on a single chip, which enables manufacturers to create a range of advanced and unique products. The
system features a high level of instructional parallelism, providing highly efficient computing capability. It can simultaneously execute
multiple advanced adaptive noise reduction and echo cancellation algorithms, and uses an asymmetric dual-core patented architecture
to allow for more processing in fewer clock cycles, resulting in reduced power consumption.
BelaSigna 300 is supported by a comprehensive suite of development tools, hands-on training, full technical support and a network of
solution partners offering software and engineering services to help speed product design and shorten time to market.
1.2 Key Features
.
Flexible DSP-based system: a complete DSP-based, mixed-signal audio system consisting of the CFX core, a fully
programmable, highly cycle-efficient, dual-Harvard architecture 24-bit DSP utilizing explicit parallelism; the HEAR configurable
accelerator for optimized signal processing; and an efficient input/output controller (IOC) along with a full complement of
peripherals and interfaces, which optimize the architecture for audio processing at extremely low power consumption
Excellent audio fidelity: up to 110dB input dynamic range, exceptionally low system noise and low group delay
Ultra-low-power: typically 1-5mA
.
.
.
.
Miniature Form Factor: available in a miniature 3.63mm x 2.68mm x 0.92mm (including solder balls) WLCSP package
Multiple audio input sources: four input channels from four input sources can be used simultaneously for multiple
microphones or direct analog audio inputs
.
Full range of configurable interfaces: including a fast I2C-based interface for download, debug and general communication, a
highly configurable PCM interface to stream data into and out of the device, a high-speed UART, an SPI port and 5 GPIOs
Integrated A/D converters and powered output: minimize need for external components
.
.
.
.
Flexible clocking architecture: supports speeds up to 40MHz
“Smart” power management: including low current standby mode requiring only 0.05mA
Diverse memory architecture: 4864x48-bit words of shared memory between the CFX core and the HEAR accelerator plus
8-Kword DSP core data memory, 12-Kwords of 32-bit DSP core program memory as well as other memory banks
Data security: sensitive program data can be encrypted for storage in external NVRAM to prevent unauthorized parties from
gaining access to proprietary software intellectual property, 128-bit AES encryption
Development tools: interface hardware with USB support as well as a full IDE that can be used for every step of program
development including testing and debugging
.
.
1.3 Contents
1.0 General Overview.................................................................................................................................................................................1
2.0 Mechanical Information and Circuit Design Guidelines ........................................................................................................................2
3.0 Architecture Overview ..........................................................................................................................................................................7
4.0 Figures and Data................................................................................................................................................................................20
5.0 Assembly Information.........................................................................................................................................................................25
6.0 Miscellaneous.....................................................................................................................................................................................28
©2009 SCILLC. All rights reserved.
January 2009 – Rev. 3
Publication Order Number:
BELASIGNA300/D
BelaSigna® 300
2.0 Mechanical Information and Circuit Design Guidelines
2.1 Mechanical Information
BelaSigna 300 is available in an ultra-miniature wafer-level chip scale package (WLCSP) measuring only 3.63mm x 2.68mm.
The BelaSigna 300 WLCSP option is Green (RoHS-compliant). Contact ON Semiconductor for supporting documentation.
All measurements are in millimeters
Figure 1: WLCSP Mechanical Information
Rev. 3 | Page 2 of 28 | www.onsemi.com
BelaSigna® 300
A total of 35 active pins are present on the BelaSigna 300 WLCSP package. They are organized in a staggered array. A description of
these pins is given in Table 1.
Table 1: Pad Descriptions
Pad
Index
BelaSigna 300 Pad Name
Description
I/O
A/D
A1
A5
B2
C3
GNDRCVR
VBATRCVR
RCVR_HP+
RCVR+
Ground for output driver
N/A
I
O
A
A
A
A
Power supply for output stage
Extra output driver pad for high power mode
Output from output driver
O
A3
RCVR-
Output from output driver
O
A
B4
C5
B6
A7
RCVR_HP-
CAP1
CAP0
Extra output driver pad for high power mode
Charge pump capacitor pin 0
Charge pump capacitor pin 1
Doubled voltage
O
A
A
A
A
N/A
N/A
O
VDBL
B8
VBAT
Power supply
I
A
B10
A9
VREG
AGND
AI4
Regulated supply voltage
Analog ground
Audio signal input 4
O
N/A
I
I
I
A
A
A
A
A
A
A/D
A/D
A/D
A/D
A/D
A
D
D
D
A
A11
B12
A13
B14
D14
E13
C13
D12
E11
C9
AI2/LOUT2
AI1/LOUT1
AI0/LOUT0
GPIO[4]/LSAD[4]
GPIO[3]/LSAD[3]
GPIO[2]/LSAD[2]
GPIO[1]/LSAD[1]/UART-RX
GPIO[0]/UART-TX
GNDC
SDA
SCL
EXT_CLK
VDDC
Audio signal input 2/output signal from preamp 2
Audio signal input 1/output signal from preamp 1
Audio signal input 0/output signal from preamp 0
General-purpose I/O 4/low speed AD input 4
General-purpose I/O 3/low speed AD input 3
General-purpose I/O 2/low speed AD input 2
General-purpose I/O 1/low speed AD input 1/and UART RX
General-purpose I/O 0/UART TX
Digital ground
I
I/O
I/O
I/O
I/O
I/O
N/A
I/O
I/O
I/O
O
C11
D10
E9
I2C data
I2C clock
External clock input/internal clock output
Core logic power
D8
E7
C7
D6
E5
D4
E3
D2
C1
SPI_CLK
SPI_SERI
SPI_CS
SPI_SERO
PCM_FR
PCM_SERI
PCM_SERO
PCM_CLK
Reserved
Serial peripheral interface clock
Serial peripheral interface input
Serial peripheral interface chip select
Serial peripheral interface output
PCM interface frame
PCM interface input
PCM interface output
PCM interface clock
Reserved
O
I
O
O
I/O
I
O
D
D
D
D
D
D
D
D
I/O
E1
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BelaSigna® 300
2.2 Recommended Design Guidelines
BelaSigna 300 is designed to allow both digital and analog processing in a single system. Due to the mixed-signal nature of this
system, the careful design of the printed circuit board (PCB) layout is critical to maintain the high audio fidelity of BelaSigna 300. To
avoid coupling noise into the audio signal path, keep the digital traces away from the analog traces. To avoid electrical feedback
coupling, isolate the input traces from the output traces.
2.2.1. Recommended Ground Design Strategy
The ground plane should be partitioned into two: the analog ground plane (AGND) and the digital ground plane (DGND). These two
planes should be connected together at a single point, known as the star point. The star point should be located at the ground terminal
of a capacitor on the output of the power regulator as illustrated in Figure 2.
Figure 2: Schematic of Ground Scheme
The DGND plane is used as the ground return for digital circuits and should be placed under digital circuits. The AGND plane should be
kept as noise-free as possible. It is used as the ground return for analog circuits and it should surround analog components and pins. It
should not be connected to or placed under any noisy circuits such as RF chips, switching supplies or digital pads of BelaSigna 300
itself. Analog ground returns associated with the audio output stage should connect back to the star point on separate individual traces.
For details on which signals require special design consideration, see Table 2 and Table 3.
In some designs, space constraints may make separate ground planes impractical. In this case a star configuration strategy should be
used. Each analog ground return should connect to the star point with separate traces.
2.2.2. Internal Power Supplies
Power management circuitry in BelaSigna 300 generates separate digital (VDDC) and analog (VREG, VDBL) regulated supplies. Each
supply requires an external decoupling capacitor, even if the supply is not used externally. Decoupling capacitors should be placed as
close as possible to the power pads. Further details on these critical signals are provided in Table 2. Non-critical signals are outlined in
Table 3.
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BelaSigna® 300
Table 2: Critical Signals
Pin Name
Description
Routing Guideline
Place 1μF (min) decoupling capacitor close to pin.
Connect negative terminal of capacitor to DGND plane.
Place separate 1μF decoupling capacitors close to each pin.
Connect negative capacitor terminal to AGND.
Keep away from digital traces and output traces.
VREG may be used to generate microphone bias.
VDBL shall not be used to supply external circuitry.
VBAT
Power supply
Internal regulator for analog
sections
VREG, VDBL
AGND
VDDC
GNDC
Analog ground return
Connect to AGND plane.
Place 10μF decoupling capacitor close to pin.
Connect negative terminal of capacitor to DGND.
Internal regulator for digital core
Digital ground return
Connect to digital ground.
Keep as short as possible.
AI0/LOUT0, AI1/LOUT1,
AI2/LOUT2, AI4
Audio inputs
Keep away from all digital traces and audio outputs.
Avoid routing in parallel with other traces.
Connect unused inputs to AGND.
Keep away from analog traces, particularly audio inputs.
Corresponding traces should be of approximately the same length.
Ideally, route lines parallel to each other.
Connect to star point.
Keep away from all analog audio inputs.
Minimize trace length. Keep away from analog signals. If possible,
surround with digital ground.
RCVR+, RCVR-,
RCVR_HP+, RCVR_HP-
Direct digital audio output
Output stage ground return
GNDRCVR
EXT_CLK
External clock input / internal
clock output
Table 3: Non-Critical Signals
Pin Name
Description
Routing Guideline
CAP0, CAP1
SDA, SCL
Internal charge pump - capacitor connection
Place 100nF capacitor close to pins
Keep as short as possible
Not critical
I2C port
GPIO[3..0]
General-purpose I/O
General-purpose UART
UART_RX, UART_TX
Not critical
PCM_FRAME, PCM_CLK, PCM_OUT,
PCM_IN
Pulse code modulation port
Keep away from analog input lines
Not critical
LSAD[4..1]
Low-speed A/D converters
Serial peripheral interface port
Connect to EEPROM
SPI_CLK, SPI_CS, SPI_SERI,
SPI_SERO
Keep away from analog input lines
2.2.3. Audio Inputs
The audio input traces should be as short as possible. The input impedance of each audio input pad (e.g., AI0, AI1, AI2, AI4) is high
(approximately 500kΩ); therefore a 10nF capacitor is sufficient to decouple the DC bias. This capacitor and the internal resistance form
a first-order analog high pass filter whose cutoff frequency can be calculated by f3dB (Hz) = 1/(RC2), which results with ~30Hz for
10nF capacitor. This 10nF capacitor value applies when the preamplifier is being used, in other words, when a non-unity gain is applied
to the signals. When the preamplifier is by-passed, the impedance is reduced; hence, the cut-off frequency of the resulting high-pass
filter could be too high. In such a case, the use of a 30-40nF serial capacitor is recommended. In cases where line-level analog inputs
without DC bias are used, the capacitor may be omitted for transparent bass response.
BelaSigna 300 provides microphone power supply (VREG) and ground (AGND). Keep audio input traces strictly away from output
traces.
Digital outputs (RCVR) MUST be kept away from microphone inputs to avoid cross-coupling.
2.2.4. Audio Outputs
The audio output traces should be as short as possible. The trace length of RCVR+ and RCVR- should be approximately the same to
provide matched impedances.
Rev. 3 | Page 5 of 28 | www.onsemi.com
BelaSigna® 300
2.2.5. PCB Manufacturing
For PCB manufacture with BelaSigna 300 WLCSP, ON Semiconductor recommends solder-on-pad (SoP) surface finish. With SoP, the
solder mask opening should be non-solder mask-defined (NSMD) and copper pad geometry will be dictated by the PCB vendor’s
design requirements.
Alternative surface finishes are ENiG and OSP; volume of screened solder paste (#5) should be less than 0.0008mm^3. If no pre-
screening of solder paste is used, then following conditions must be met:
(i) the solder mask opening should be >0.3mm in diameter,
(ii) the copper pad will have 0.25mm diameter, and
(iii) soldermask thickness should be less than 1mil thick above the copper surface.
ON Semiconductor can provide BelaSigna 300 WLCSP land pattern CAD files to assist your PCB design upon request.
Rev. 3 | Page 6 of 28 | www.onsemi.com
BelaSigna® 300
3.0 Architecture Overview
The architecture of BelaSigna 300 is shown in Figure 3.
Figure 3: BelaSigna 300 Architecture: A Complete Audio Processing System
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BelaSigna® 300
3.1 CFX DSP Core
The CFX DSP is a user-programmable general-purpose DSP core that uses a 24-bit fixed-point, dual-MAC, dual-Harvard architecture.
It is able to perform two MACs, two memory operations and two pointer updates per cycle, making it well-suited to computationally
intensive algorithms.
The CFX features:
Dual-MAC 24-bit load-store DSP core
Four 56-bit accumulators
Four 24-bit input registers
Support for hardware loops nested up to 4 deep
Combined XY memory space (48-bits wide)
Dual address generator units
Wide range of addressing modes:
o
o
o
o
Direct
Indirect with post-modification
Modulo addressing
Bit reverse
3.1.1. CFX DSP Architecture
The CFX architecture encompasses various memory types and sizes, peripherals, interrupt controllers, and interfaces. Figure 4
illustrates the basic architecture of the CFX. The control lines shown exiting the PCU indicate that control signals go from the PCU to
essentially all other parts of the CFX.
The CFX employs a parallel instruction set for simultaneous control of multiple computation units. The DSP can execute up to four
computation operations in parallel with two data transfers (including rounding and/or saturation as well as complex address updates),
while simultaneously changing control flow.
Rev. 3 | Page 8 of 28 | www.onsemi.com
BelaSigna® 300
Internal Routing
Interrupts
X0
X1
Instruction Bus
SR
LR
PMEM
CTRL
CTRL
Direct Addr
SP Offset
Hardware Loop
Stack
ILSR
ILPC
Pre-adder
P Bus
PC
PCU
X Multiplier
CTRL
X ALU and
Shifter
XMEM
X AGU
A Accumulators
Immediate
Y0
Y1
X Bus
Y Multiplier
YMEM
Y AGU
Y ALU
B Accumulators
DCU
X Data
Y Data
X Round/
Saturate
X Sign/Zero
Extend
Y Bus
Y Bus
Y Round/
Saturate
Y Sign/Zero
Extend
X Bus
P Bus
DMU
Internal Routing
Data registers
Address and Control registers
Figure 4: CFX DSP Core Architecture
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BelaSigna® 300
3.2 CFX DSP Instruction Set
Table 4 shows the list of all general CFX instructions and their description. Many instructions have multiple variations not shown in the
table. Please refer to the CFX DSP Architecture Manual for more details.
Table 4: CFX Summary Instruction Set
Instruction
ABS
Description
Calculate the absolute value of a data register or accumulator
ADD
Add values (various combinations of accumulators, pointers and data registers)
Add two XY data registers, multiply the result by a third XY data register, and store the result in an accumulator
Add two XY data registers, multiply the result by a third XY data register, and add the result to an accumulator
Add two XY data registers, multiply the result by a third XY data register, negate the result and store it in an accumulator
Add two XY data registers, multiply the result by a third XY data register, and subtract the result from an accumulator
Add two data registers or accumulators and shift right one bit, storing the result
Perform a bitwise AND operation on the two operands
ADDMUL
ADDMULADD
ADDMULNEG
ADDMULSUB
ADDSH
AND
BITCLR
BITSET
BITTGL
BITTST
BREAKPOINT
CALL
Clear a bit in the register
Set a bit in the register
Toggle a bit in a data register
Test a bit in a data register
Halts the DSP for debugging if software breakpoints are enabled through the debug port
Call a subroutine
CLR
Clear a word of X memory specified by an X pointer, with update
CMP
CMPU
DIVST
ENDLOOP
GOTO
Compare a data register or accumulator to another data register or accumulator or a value
Compare a data register to a value or another data register as unsigned values or compare two accumulators as unsigned values
Division step for dividing data register by data register and stores the result to a data register
End a hardware loop before the count has reached zero
Branch to an address or label
INTERRUPT
LOAD
LOG2ABS
LOOP
Software interrupt
Load a register, accumulator or a memory location with another register, accumulator or data
Calculate the logarithm base 2 of the absolute value of a data register, storing the result in a data register
Loop with a specified count
MAX
MIN
MOVE
Determine the maximum value of two data registers or accumulators and store the result in a data register or accumulator
Determine the minimum value of two data registers or accumulators and store the result in a data register or accumulator
Move a register or accumulator to a register or accumulator
MUL
Multiply two XY data registers, storing the result in an accumulator
MULADD
MULNEG
MULSUB
NEG
NLOG2ABS
NOP
Multiply two XY data registers, and add the result to an accumulator
Multiply two XY data registers, negate the result and store it in an accumulator
Multiply two XY data registers, and subtract the result from an accumulator
Negate a data register or accumulator, storing the result in a data register or accumulator
Calculate the logarithm base 2 of the absolute value of a data register, negate the result, and store the result in a data register
No operation
Perform a bitwise OR operation on two accumulators storing the result in an accumulator or on two data registers or a data register
and value, storing the result in a data register
OR
RETURN
RETURNI
SHLL
Return from a subroutine
Return from an interrupt
Shift a data register left logically
SHRA
Shift a data register right arithmetically
SHRL
Shift a data register right logically
SLEEP
STORE
SUB
SUBMUL
SUBMULADD
SUBMULNEG
SUBMULSUB
SUBSH
SUBSTEP
SWAP
Enter sleep mode and wait for an interrupt and then wake up from sleep mode
Store data, a register or accumulator in a register, accumulator or memory location
Subtract two data registers or accumulators, storing the result in a data register or accumulator
Subtract two XY data registers, multiply the result by a third XY data register, and store the result in an accumulator
Subtract two XY data registers, multiply the result by a third XY data register, and add the result to an accumulator
Subtract two XY data registers, multiply the result by a third XY data register, negate the result and store it in an accumulator
Subtract two XY data registers, multiply the result by a third XY data register, and subtract the result from an accumulator
Subtract two data registers or two accumulators and shift right one bit, storing the result in a data register or accumulator
Subtract a step register from the corresponding pointer
Swap the contents of two data registers, conditionally
XOR
Perform a bitwise XOR operation on two data registers or a data register and a value, storing the result in a data register
Rev. 3 | Page 10 of 28 | www.onsemi.com
BelaSigna® 300
3.3 HEAR Configurable Accelerator
The HEAR Configurable Accelerator is a highly optimized signal processing engine that is configured through the CFX. It offers high
speed, high flexibility and high performance, while maintaining low power consumption. For added computing precision, the HEAR
supports block floating point processing. Configuration of the HEAR is performed using the HEAR configuration tool (HCT). For further
information on the usage of the HEAR and the HCT, please refer to the HEAR Configurable Accelerator Reference Manual.
The HEAR is optimized for advanced audio algorithms, including but not limited to the following:
Dynamic range compression
Directional processing
Acoustic echo cancellation
Noise reduction
To provide the ability for these algorithms to be executed efficiently, the HEAR excels at the following:
Processing using a weighted overlap add (WOLA) filterbank or FFT
Time domain filtering
Subband filtering
Attack/release filtering
Vector addition/subtraction/multiplication
Signal statistics (such as average, variance and correlation)
3.4 Input/Output Controller (IOC)
The IOC is responsible for the automated data moves of all audio samples transferred in the system. The IOC can manage any system
configuration and route the data accordingly. It is an advanced audio DMA unit.
3.5 Memory
3.5.1. RAM & ROM
The size and width of each of the RAM and ROM structures are shown in Table 5:
Table 5:RAM and ROM Structure
Memory Structure
Data Width
Memory Size
2048
Program memory (ROM)
Program memory (RAM)
X memory (RAM)
32
32
24
24
24
12288
6144
Math library LUT (ROM)
Y memory (RAM)
128
2048
3.5.2. Shared Memories
The shared CFX/HEAR memories include the following:
Table 6: Shared Memories
Type
Name
Size
H0MEM, H1MEM, H2MEM,
H3MEM, H4MEM, H5MEM
Data memory (RAM)
Each 128x48-bit words
FIFO memory (RAM)
Coefficient memory (RAM)
Data ROM
AMEM, BMEM
CMEM, DMEM
SIN/COS LUT
Each 1024x48-bit words
Each 1024x48-bit words
512x48-bit words containing the 512 point sin/cos look up table
2048x32-bit words
Microcode memory (RAM)
MICROCODE_MEM
Rev. 3 | Page 11 of 28 | www.onsemi.com
BelaSigna® 300
3.5.3. Memories Structure
Figure 5 shows the system memory structure. The individual blocks are described in the sections that follow.
Figure 5: System Memory Architecture
3.5.4. FIFO Controller
The FIFO controller handles the moving of data to and from the FIFOs, after being initially configured. Up to eight FIFOs can be created
by the FIFO controller, four in A memory (AMEM) and four in B memory (BMEM). Each FIFO has a block counter that counts the
number of samples read or written by the IOC. It creates a dedicated interrupt signal, updates the block counter and updates the FIFO
pointers when a new block has been read or written.
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BelaSigna® 300
3.5.5. Memory Maps
The structure of the XMEM and YMEM address spaces are shown in Figure 6.
Figure 6: XMEM and YMEM Memory Maps
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BelaSigna® 300
The structure of the PMEM address space is shown in Figure 7.
Figure 7: PMEM Memory Map
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BelaSigna® 300
3.6 Other Digital Blocks and Functions
3.6.1. General-Purpose Timer
The CFX DSP system contains two general-purpose timers. These can be used for scheduling tasks that are not part of the sample-
based signal-processing scheme, such as checking the battery voltage, and periodically asserting the available analog and digital
inputs for purposes such as reading the value of a volume control potentiometer or detecting input from a push button.
3.6.2. Watchdog Timer
The watchdog timer is a programmable hardware timer that operates from the system clock and is used to ensure system sanity. It is
always active and must be periodically acknowledged as a check that an application is still running. Once the watchdog times out, it
generates an interrupt. If left to time out a second consecutive time without acknowledgement, a system reset will occur.
3.6.3. Interrupts
The interrupt flow of the system handles interrupts generated by the CFX DSP core and the HEAR accelerator. The CFX interrupt
controller receives interrupts from the various blocks within the system. The FIFO controller can send interrupts to the CFX. The HEAR
can generate events which are interrupts in the CFX.
3.6.4. Hear Function Chain Controller
The HEAR function chain controller responds to commands from the CFX, and events from the FIFO controller. It must be configured
by the CFX to enable the triggering of particular function chains within a microcode configuration. This is accomplished through the
appropriate setting of control registers as described in the Hardware Reference Manual for BelaSigna 300.
The interaction between the interrupt controller, the HEAR function chain controller and the rest of the system are shown in Figure 8.
Figure 8: Interrupt Flow
Rev. 3 | Page 15 of 28 | www.onsemi.com
BelaSigna® 300
3.6.5. Algorithm and Data Security
Algorithm software code and user data that requires permanent retention is stored off the BelaSigna 300 chip in separate non-volatile
memory. To support this, the BelaSigna 300 chip can gluelessly interface to an external SPI EEPROM.
To prevent unauthorized access to the sensitive intellectual property (IP) stored in the EEPROM, a comprehensive system is in place to
protect manufacturer’s application code and data. When locked the system implements an access restriction layer that prevents access
to both volatile and non-volatile system memory. When unlocked, both memory and EEPROM are accessible.
To protect the IP in the non-volatile memory the system supports decoding algorithm and data sections belonging to an application that
have been encrypted using the advanced encryption standard (AES) and stored in non-volatile memory. While system access
restrictions are in place, the keys used in the decryption of these sections will be secured from external access by the regular access
restrictions. When the system is externally "unlocked" these keys will be cleared, preventing their use in decoding an application by
non-authorized parties. After un-restricting access in this way the system may then be restored by re-programming the decryption keys.
3.7 Analog Blocks
3.7.1. Input Stage
The analog audio input stage is comprised of four individual channels. For each channel, one input can be selected from any of the four
possible input sources and is then routed to the input of the programmable preamplifier that can be configured for bypass or gain values
of 12 to 30dB (3dB steps). The input stage is shown in Figure 9.
A built-in feature allows a sampling delay to be configured for any one or more channels. This is useful in beam-forming applications.
Conversion
and filtering
Preamp
AI0
M
U
Channel 0
Conversion
and filtering
AI1
Preamp
X
Channel 1
Channel 2
Channel 3
IOC
M
U
X
Conversion
and filtering
AI2
AI4
Preamp
Preamp
Conversion
and filtering
Figure 9: Input Stage
3.7.2. Input Dynamic Range Extension (IDRX)
To increase the input dynamic range for a particular application, it is possible to pair-wise combine the four AD converters found on
BelaSigna 300. This will increase the dynamic range up to 110dB. When this technique is used, the device handles the preamplifier
gain configuration based on the input level and sets it in such a way as to give the maximum possible dynamic range. This avoids
having to make the design trade-off between sufficient amplification for low-level signals and avoiding saturation for high-level signals.
Rev. 3 | Page 16 of 28 | www.onsemi.com
BelaSigna® 300
3.7.3. Output Stage
The first part of the output stage interpolates the signal for highly oversampled D/A conversion and automatically selects the
oversampling rate. The signal is then routed to the differential direct-digital output driver.
The low-impedance direct-digital output is driven by a pulse-density modulated output and can be used to directly drive an output
transducer without the need for a separate power amplifier. The output stage is shown in Figure 10.
BelaSigna 300 has an option for high-power mode that decreases the impedance of the output stage, thus permitting higher possible
acoustic output levels. To use this feature, RCVR_HP+ and RCVR+ should be tied together before connecting to the output transducer,
and RCVR_HP- and RCVR- should be tied together. The appropriate registers must also be configured (as specified in the Hardware
Reference Manual for BelaSigna 300).
RCVR_HP+
RCVR+
Output
driver
Output
from IOC
Upsampling and
conversion
RCVR-
RCVR_HP-
Figure 10: Output Stage
3.7.4. Clock Generation Circuitry
BelaSigna 300 is equipped with an un-calibrated internal RC oscillator that will provide clock support for booting and stand-by mode
operations. This internal clocking circuitry cannot be used during normal operation. An external clock signal must be present on the
EXT_CLK pin to allow BelaSigna 300 to operate. All other needed clocks in the system are derived from this external clock frequency.
3.8 Power Supply Unit
3.8.1. Voltage Mode
BelaSigna 300 operates in: Low voltage (LV) power supply mode. This mode allows integration into a wide variety of devices with a
range of voltage supplies and communications levels. BelaSigna 300 operates from a nominal supply of 1.8V on VBAT, but this can
scale depending on available supply. The digital logic runs on an internally generated regulated voltage, in the range of 0.9V to 1.2V. All
digital I/O pads including the SPI port run from the same voltage as supplied on VBAT.
The power management on BelaSigna 300 includes the power-on-reset (POR) functionality as well as power supervisory circuitry.
These two components work together to ensure proper device operation under all battery conditions.
The power supervisory circuitry monitors both the battery supply voltage (VBAT) and the internal digital supply voltage (VDDC). This
circuit is used to start the system when VBAT reaches a safe startup voltage, and to reset the system when either of the VBAT or
Architecture Overview
VDDC voltages drops below a relevant voltage threshold. The relevant threshold voltages are shown in Table 7.
Table 7: Power Management Thresholds
Voltage Level
Threshold
VBAT monitor startup
VBAT startup
0.70V
0.82V +/- 50mV
0.80V +/- 50mV
VBAT and VDDC shutdown
Rev. 3 | Page 17 of 28 | www.onsemi.com
BelaSigna® 300
3.8.2. Power-on-Reset (POR) and Booting Sequence
BelaSigna 300 uses a POR sequence to ensure proper system behavior during start-up and proper system configuration after start-up.
At the start of the POR sequence, the audio output is disabled and all configuration and control registers are asynchronously reset to
their default values (as specified in the Hardware Reference Manual for BelaSigna 300). All CFX DSP registers are cleared and the
contents of all RAM instances are unspecified at this point.
The POR sequence consists of two phases: voltage supply stabilization and boot ROM initialization. During the voltage supply
stabilization phase, the following steps are performed:
1. The internal regulators are enabled and allowed to stabilize.
2. The internal charge pump is enabled and allowed to stabilize.
3. SYSCLK is connected to all of the system components.
4. The system switches to external clocking mode
3.8.3. Power Management Strategy
BelaSigna 300 has a built-in power management unit that guarantees valid system operation under any voltage supply condition to
prevent any unexpected audio output as the result of any supply irregularity. The unit constantly monitors the power supply and shuts
down all functional units (including all units in the audio path) when the power supply voltage goes below a level at which point valid
operation can no longer be guaranteed.
Once the supply voltage rises above the startup voltage of the internal regulator that supplies the digital subsystems (VDDCSTARTUP
)
and remains there for the length of time TPOR, a POR will occur. If the supply is consistent, the internal system voltage will then remain
at a fixed nominal voltage (VDDCNOMINAL). If a spike occurs that causes the voltage to drop below the shutdown internal system voltage
(VDDCSHUTDOWN), the system will shut down. If the voltage rises again above the startup voltage and remains there for the length of time
TPOR, a POR will occur. If operating directly off a battery, the system will not power down until the voltage drops below the
VDDCSHUTDOWN voltage as the battery dies. This prevents unwanted resets when the voltage is just on the edge of being too low for the
system to operate properly because the difference between VDDCSTARTUP and VDDCSHUTDOWN prevents oscillation around the
VDDCSHUTDOWN point.
3.9 Other Analog Support Blocks and Functions
3.9.1. Low-Speed A/D Converters (LSAD)
The BelaSigna 300 chip has four LSAD channels that connect to external analog inputs for purposes such as for reading the value of a
potentiometer or an analog sensor (LSAD[1..4]). The native data format for the LSAD is 10-bit two's-complement. However, a total of
eight operation modes are provided that allow a configurable input dynamic range in cases where certain minimum and maximum
values for the converted inputs are desired, such as in the case of a volume control where only input values up to a certain magnitude
are allowed. Each LSAD channel is sampled at a nominal frequency of 1.6kHz when using the default settings. Each LSAD pin is
multiplexed with a GPIO function (see 3.10.1) as such the functionality of the pin can be either a GPIO or an LSAD depending on the
configuration.
3.9.2. Battery Monitor
A programmable on-chip battery monitor is available for overall system power management. The battery monitor works by incrementing
a counter value every time the battery voltage goes below a desired, configurable threshold value. This counter value can be used in an
application-specific power-management algorithm running on the CFX. The CFX can initiate any desired actions once the battery hits a
predetermined value.
3.10 Digital Interfaces
3.10.1. General-Purpose Input Output (GPIO) Ports
BelaSigna 300 has five GPIO ports that can connect to external digital inputs such as push buttons, or digital outputs such as the
control or trigger of an external companion chip (GPIO[0..4]). The direction of these ports (input or output) is configurable and each pin
has an internal pull-up resistor when configured as a GPIO. A read from an unconnected pin will give a value of logic 1. Four of the five
GPIO pins are multiplexed with an LSAD (see 3.9.1) and as such the functionality of the pin can be either a GPIO or an LSAD
depending on the configuration. Note that GPIO0 cannot be used as an LSAD.
Rev. 3 | Page 18 of 28 | www.onsemi.com
BelaSigna® 300
3.10.2. Inter-IC Communication (I2C) Interfaces
The I2C interface is an industry-standard interface that can be used for high-speed transmission of data between BelaSigna 300 and an
external device. The interface operates at speeds up to 400Kbit/sec for system clocks (EXT_CLK) higher than 1.28MHz. In product
development mode, the I²C interface is used for application debugging purposes, communicating with the BelaSigna 300 development
tools. The interface can be configured to operate in either master mode or slave mode.
3.10.3. Serial Peripheral Interface (SPI) Port
An SPI port is available on BelaSigna 300 for applications such as communication with a non-volatile memory (EEPROM). The I/O
levels on this port are defined by the voltage on the VBAT pin. The SPI port operates in master mode only, which supports
communications with slave SPI devices.
3.10.4. PCM Interface
BelaSigna 300 includes a highly configurable pulse code modulation (PCM) interface that can be used to stream signal, control and
configuration data into and out of the device. The I/O levels on this port are defined by the voltage on the VBAT pin.
3.10.5. UART Interface
A general-purpose two-pin UART interface is available for RS-232 compatible communications. The baud rate (bits/second) of this
interface is typically configurable within a range of 0.4 to 320 kbps, depending on the application's system clock. The I/O levels on this
port are defined by the voltage on the VBAT pin.
Rev. 3 | Page 19 of 28 | www.onsemi.com
BelaSigna® 300
4.0 Figures and Data
4.1 Absolute Maximum Ratings
Table 8: Absolute Maximum Ratings
Parameter
Min.
-0.3
0.9
Max.
2.0
2.0
85
Unit
V
Voltage at any input pin
Operating supply voltage
Operating temperature range
Storage temperature range
V
-40
°C
°C
-40
85
Caution: Class 2 ESD Sensitivity, JESD22-A114-B (2000V)
4.2 Electrical Performance Specifications
The tests were performed at 20ºC with a clean 1.8V supply voltage. BelaSigna 300 was running in low voltage mode (VDDC=1.3V).
The system clock (SYS_CLK) was set to 5.12MHz and the sampling frequency is 16kHz unless otherwise noted.
Parameters marked as screened are tested on each chip. Other parameters are qualified but not tested on every part.
Table 9: Electrical Specifications
Overall
Description
Symbol
Conditions
Min.
Typ.
Max.
Units
Screened
Supply voltage
VBAT
0.9
1.8
2.0
V
Filterbank, 100% CFX usage,
5.12MHz, 16kHz
WDRC, 1.8V
Excludes output drive current
AEC, 1.8V
Excludes output drive current
Theoretical maximum
Excludes output drive current
Deep Sleep current
Current consumption
IBAT
-
-
-
-
-
-
-
μA
μA
√
600
2.1
10
-
mA
mA
μA
-
26
40
Ambient room temperature
VREG (1μF External Capacitor)
Description
Symbol
VREG
Conditions
Min.
Typ.
1.00
55
Max.
1.05
-
Units
V
Screened
Regulated voltage output
Regulator PSRR
0.95
√
VREG_PSRR
ILOAD
1kHz
50
-
dB
Load current
-
2
mA
Load regulation
LOADREG
LINEREG
-
6.1
2
6.5
5
mV/mA
mV/V
Line regulation
-
Rev. 3 | Page 20 of 28 | www.onsemi.com
BelaSigna® 300
Table 10: Electrical Specification (Continued)
VDBL (1μF External Capacitor)
Description
Symbol
Conditions
Min.
Typ.
2.0
41
-
Max.
2.1
-
Units
V
Screened
Regulated doubled voltage output VDBL
1.9
√
Regulator PSRR
Load current
VDBLPSRR
1kHz
35
-
dB
ILOAD
2.5
10
mA
Load regulation
Line regulation
LOADREG
LINEREG
-
7
mV/mA
mV/V
√
-
10
20
VDDC (1μF External Capacitor)
Description
Symbol
VDDC
Conditions
Min.
Typ.
0.95
29
25.5
-
Max.
1.2
31
Units
V
Screened
Digital supply voltage output
VDDC output level adjustment
Regulator PSRR
Configured by a control register
0.79
√
VDDCSTEP
VDDCPSRR
ILOAD
27
25
-
mV
1kHz
26
dB
Load current
3.5
12
mA
Load regulation
LOADREG
LINEREG
-
3
mV/mA
mV/V
√
Line regulation
-
3
8
Power-on-Reset (POR)
Description
Symbol
Conditions
Min.
0.775
0.755
13.8
Typ.
0.803
0.784
19.1
Max.
0.837
0.821
22.0
Units
V
Screened
POR startup voltage
POR shutdown voltage
POR hysteresis
VDDCSTARTUP
VDDCSHUTDOWN
PORHYSTERESIS
TPOR
V
mV
ms
POR duration
11.0
11.6
12.3
Rev. 3 | Page 21 of 28 | www.onsemi.com
BelaSigna® 300
Table 10: Electrical Specification (Continued)
Input Stage
Description
Symbol
VIN
Conditions
Min.
0
Typ.
-
Max.
Units
V
Screened
Analog input voltage
Preamplifier gain tolerance
2
1
PAG
1kHz
-1
0
dB
√
√
0dB preamplifer gain
Non-zero preamplifier gains
-
239
578
-
kΩ
kΩ
Input impedance
RIN
550
615
Unweighted, 100Hz to 10kHz
BW
Preamplifier setting:
0dB
-
-
-
-
-
-
-
-
39
10
7
6
4.5
4
50
12
9
8
5.5
5
12dB
15dB
18dB
21dB
24dB
27dB
30dB
Input referred noise
INIRN
μVrms
3.5
3
4.5
4
1 kHz, 20Hz to 8kHz BW
Preamplifier setting:
0dB
85
84
84
83
82
81
80
78
89
88
88
87
86
85
83
81
-
-
-
-
-
-
-
-
12dB
15dB
18dB
21dB
24dB
27dB
30dB
Input dynamic range
Input peak THD+N
INDR
dB
dB
INTHDN
Any valid preamplifier gain, 1kHz
-
-70
-63
√
Direct Digital Output
Description
Symbol
IDO
Conditions
Normal mode
Normal mode
Min.
Typ.
Max.
50
Units
mA
Ω
Screened
Maximum load current
Output impedance
-
-
-
-
RDO
5.5
Unweighted, 100Hz to
8kHz BW, mono
Unweighted, 100Hz to
22kHz BW, mono
Output dynamic range
DODR
92
-
95
-
dB
Output THD+N
Output voltage
DOTHDN
DOVOUT
-79
-76
dB
V
-VBATRCVR
VBATRCVR
Anti-Aliasing Filters (Input and Output)
Description
Symbol
Conditions
Min.
Typ.
Max.
Units
Screened
Preamplifier filter cut-off
frequency
Digital anti-aliasing filter cut-off
frequency
Preamp not bypassed
-
-
20
-
kHz
fs/2
-
Passband flatness
-1
-
-
1
-
dB
dB
Input stopband attenuation
60kHz (12kHz cut-off)
60
Rev. 3 | Page 22 of 28 | www.onsemi.com
BelaSigna® 300
Table 10: Electrical Specification (Continued)
Low-Speed A/D
Description
Input voltage
INL
Symbol
Conditions
Min.
Typ.
Max.
2.0
10
Units
V
Screened
Peak input voltage
From GND to 2*VREG
From GND to 2*VREG
0
-
-
4
-
√
LSB
LSB
DNL
-
2
Maximum variation over
temperature (0C to 50C)
-
-
5
LSB
Sampling frequency
All channels sequentially
8 channels
-
-
12.8
1.6
-
-
kHz
kHz
Channel sampling frequency
Digital Pads
Description
Symbol
Conditions
Min.
Typ.
Max.
Units
Screened
VBAT
* 0.8
Voltage level for high input
Voltage level for low input
Voltage level for high output
Voltage level for low output
VIH
-
-
V
√
VBAT
* 0.2
VIL
-
-
V
V
√
√
√
VBAT VBAT *
* 0.8
VOH
VOL
2mA source current
2mA sink current
-
0.87
VBAT * VBAT
0.08
-
V
* 0.2
Input capacitance for digital pads CIN
Pull-up resistance for digital input
pads
-
-
4
-
pF
kΩ
RUP_IN
270
-
√
√
Pull-down resistance for digital
input pads
RDOWN_IN
-
275
+/-0
-
kΩ
Sample rate tolerance
Rise and fall time
ESD
FS
Sample rate of 16kHz or 32kHz
Digital output pad
-1
+1
%
ns
kV
V
Tr, Tf
Human Body Model
Machine Model
2
200
200
Latch-up
V<GNDC, V>VBAT
mA
Oscillation Circuitry
Description
Symbol
Conditions
Min.
Typ.
Max.
Units
Screened
Internal oscillator frequency
SYS_CLK
0.5
-
10.24
MHz
Calibrated internal clock
frequency
SYS_CLK
-1
+/-0
+1
%
√
Internal oscillator jitter
System clock: 1.28MHz
Duty cycle
-
45
-
0.4
50
-
1
ns
%
55
External oscillator tolerances
EXT_CLK
CLKMAX
System clock: 30MHz
External clock; VBAT: 1.8V
300
40
ps
Maximum working frequency
-
MHz
Digital Interfaces
Description
Symbol
Conditions
Min.
Typ.
Max.
400
-
Units
kbps
Screened
I2C baud rate
System clock ≥ 1.28MHz
System clock ≥ 5.12MHz
-
-
-
General-purpose UART baud rate
1
Mbps
Rev. 3 | Page 23 of 28 | www.onsemi.com
BelaSigna® 300
4.3 Environmental Characteristics
Parts supplied against this specification will have been qualified as follows:
Table 10: Environmental Characteristics
Characteristics
Packaging Level
Moisture sensitivity level
JEDEC Level 3
30°C / 60% RH for 192 hours
121°C / 100% RH / 2 atm for 168 hours
-65°C to 150°C for 1000 cycles
130°C / 85% RH for 100 hours
150°C for 1000 hours
Pressure cooker test (PCT)
Thermal cycling test (TCT)
Highly accelerated stress test (HAST)
High temperature stress test (HTST)
Board Level
Temperature
Drop
-40°C to 125°C for 2500 cycles with no failures
1m height with no failures
Bending
1mm deflection / 2Hz
Rev. 3 | Page 24 of 28 | www.onsemi.com
BelaSigna® 300
5.0 Assembly Information
5.1 Carrier Details
ON Semiconductor offers tape and reel packing for BelaSigna 300 WLCSP. The packing consists of a pocketed carrier tape, a cover
tape, and a molded anti-static polystyrene reel. The carrier and cover tape create an ESD safe environment, protecting the components
from physical and electrostatic damage during shipping and handling.
TBD
Figure 11: Package Orientation on Tape
Notes:
1. 10 sprockets hole pitch cumulative tolerance ±0.1.
2. Camber in compliance with EIA 763.
3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
Rev. 3 | Page 25 of 28 | www.onsemi.com
BelaSigna® 300
Figure 12: CABGA Carrier Tape Drawing
5.1.1. Sample Label Standard
Sample Label will be available Q1 2009.
5.2 Re-Flow Information
The re-flow profile depends on the equipment that is used for the re-flow and the assembly that is being re-flowed. Use the following
table from the JEDEC Standard 22-A113D and J-STD-020C as a guideline:
Table 11: Re-flow Information
Profile Feature
Pb-free Assembly
Average Ramp-Up Rate (TL to TP)
Preheat
3°C/second maximum
Temperature minimum (TSMIN)
Temperature maximum (TSMAX)
Time (min. to max.) (ts)
TSMAX to TL
150°C
200°C
60-180 seconds
Ramp-up rate
3°C/second maximum
Time Maintained Above
Temperature (TL)
217°C
Time (tL)
60-150 seconds
260 +0/-5°C
Peak Temperature (TP)
Time within 5°C of Actual Peak Temperature
Ramp-Down Rate
20-40 seconds
6°C/second maximum
8 minutes maximum
Time 25°C to Peak Temperature
Rev. 3 | Page 26 of 28 | www.onsemi.com
BelaSigna® 300
A typical re-flow profile is shown in Figure 13.
Figure 13: Typical Reflow Profile
5.3 Electrostatic Discharge (ESD) Sensitive Device
CAUTION: ESD sensitive device. Permanent damage may occur on devices subjected to high-energy electrostatic discharges.
Proper ESD precautions in handling, packaging and testing are recommended to avoid performance degradation or loss of
functionality. Device is 2kV HBM ESD qualified.
5.4 Moisture Sensitivity Level
This device will be qualified MSL 3 or better.
Rev. 3 | Page 27 of 28 | www.onsemi.com
BelaSigna® 300
6.0 Miscellaneous
6.1 Ordering Information
To order BelaSigna 300 WLCSP, please contact your account manager and ask for part number B300W35A102XXG.
6.2 Chip Identification
Chip identification information can be retrieved by using the Communications Accelerator Adaptor (CAA) tool along with the protocol
software provided by ON Semiconductor (see CAA instruction manual). For BelaSigna 300, the key identifier components and values
are as follows:
Chip Family: 0x03
Chip Version: 0x02
Chip Revision: 0x0100
6.3 Support Software
A full suite of comprehensive tools is available to assist software developers from the initial concept and technology assessment
through to prototyping and product launch. Simulation, application development and communication tools as well as an Evaluation and
Development Kit (EDK) facilitate the development of advanced algorithms on BelaSigna 300.
6.4 Training
To facilitate development on the BelaSigna 300 platform, training is available upon request. Contact your account manager for more
information.
6.5 Revision History
Date
Revision Change
January 2008
March 2008
January 2009
1
2
3
Initial Release (Preliminary)
Launch Release (Preliminary), Conversion to ON Semiconductor
Updated assembly information and carrier details
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any
products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical”
parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the
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Rev. 3 | Page 28 of 28 | www.onsemi.com
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