B300W35A109A1G [ONSEMI]
Audio Processor for AfterMaster HD;
| 型号： | B300W35A109A1G |
| 厂家： | 
ONSEMI |
| 描述： | Audio Processor for AfterMaster HD 商用集成电路 |
| 文件： | 总9页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BelaSigna 300 with
AfterMaster HD
Audio Processor for
AfterMaster HD
Introduction
®
BelaSigna 300 AM is a DSP−based audio processor which is able
www.onsemi.com
to execute the AfterMaster HD algorithm within a system that also
includes a host processor and/or external 12S− based mono or stereo
A/D converters and D/A converters.
AfterMaster HD is an algorithm which processes audio signals in
real−time to provide a significant increase in loudness, clarity, depth,
and fullness.
BelaSigna 300 AM is specifically designed for use in applications
requiring a solution to overcome the limitations of small or
downward−facing speakers, including flat−screen televisions or
headphones.
WLCSP−35
W SUFFIX
CASE 567AG
This datasheet describes only the specific information required to
integrate BelaSigna 300 AM into an audio system.
For a more general description of the programmable BelaSigna 300
device from ON Semiconductor, please refer to the BelaSigna 300
datasheet.
MARKING DIAGRAM
BELASIGNA300
35−02−G
XXXXYZZ
Key Features
• Ultra−low−power: typically 4−8 mA when executing AfterMaster HD
• Miniature Form Factor: available in a miniature 3.63 mm x
2.68 mm x 0.92 mm (including solder balls) WLCSP package.
BELASIGNA300 = Device Code
35
02
= Number of Balls
= Revision of Die
G
= Pb−Free
2
• Full Range of Configurable Interfaces: including a fast I C−based
XXXX
Y
= Date Code
= Assembly Plant Identifier
= (May be Two Characters)
= Traceability Code
interface for download and general configuration of the
AfterMaster HD algorithm, a highly configurable PCM interface to
stream data into and out of the device, a high−speed UART, an SPI
port and 5 GPIOs
ZZ
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
ORDERING INFORMATION
Compliant
†
Device
B300W35A109A1G
Package
Shipping
WLCSP
2500 / Tape &
Reel
(Pb−Free)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
March, 2015 − Rev. 0
B300AM/D
BelaSigna 300 with AfterMaster HD
Figures and Data
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Min
−0.3
0.9
Max
2.0
2.0
85
Unit
V
Voltage at any input pin
Operating supply voltage (Note 1)
Operating temperature range (Note 2)
Storage temperature range
V
−40
−55
°C
°C
85
Caution: Class 2 ESD Sensitivity, JESD22−A114−B (2000 V)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Functional operation only guaranteed below 0°C for digital core (VDDC) and system voltages above 1.0 V.
2. Parameters may exceed listed tolerances when out of the temperature range 0 to 50°C.
Electrical Performance Specifications
The tests were performed at 20°C with a clean 1.8 V supply voltage. BelaSigna 300 AM was running in high voltage mode (VDDC
= 1.8 V unless otherwise noted). The system clock (SYS_CLK) was generated externally at 38 MHz.
Parameters marked as screened are tested on each chip. Other parameters are qualified but not tested on every part.
Table 2. ELECTRICAL SPECIFICATIONS
Description
OVERALL
Symbol
Conditions
Min
Typ
Max
Units
Screened
Supply voltage
V
1.8
−
2.0
−
V
√
√
√
√
BAT
Current consumption
I
AfterMaster HD @ Fs= 48 kHz
Fs = 44.1 kHz
8
7
3
2
mA
mA
mA
mA
BAT
−
−
Fs =16 kHz
−
−
Fs = 8 kHz
−
−
VREG (1 mF External Capacitor) Measurement at VDDC = 1.0 V, Low voltage mode
Regulated voltage output
Regulator PSRR
Load current
V
0.95
50
−
1.00
55
−
1.05
−
V
dB
√
√
√
REG
REG_PSRR
V
1 kHz
I
2
mA
LOAD
Load regulation
Line regulation
LOAD
−
6.1
2
6.5
5
mV/mA
mV/V
REG
REG
LINE
−
VDBL (1 mF External Capacitor) Measurement at VDDC = 1.0 V, Low voltage mode
Regulated doubled voltage
output
VDBL
1.9
2.0
2.1
V
Regulator PSRR
Load current
VDBL
1 kHz
35
−
41
−
−
dB
mA
PSRR
I
2.5
10
20
LOAD
Load regulation
Line regulation
LOAD
−
7
mV/mA
mV/V
√
√
REG
LINE
−
10
REG
VDDC (1 mF External Capacitor) Measurement at VDDC = 1.0 V, Low voltage mode
Digital supply voltage output
VDDC output level adjustment
Regulator PSRR
VDDC
Configured by a control register
0.79
27
25
−
0.95
29
25.5
−
1.25
31
26
3.5
12
8
V
mV
VDDC
STEP
PSRR
VDDC
1 kHz
dB
Load current
I
mA
LOAD
Load regulation
LOAD
−
3
mV/mA
mV/V
√
REG
REG
Line regulation
LINE
−
3
www.onsemi.com
2
BelaSigna 300 with AfterMaster HD
Table 2. ELECTRICAL SPECIFICATIONS (continued)
Description
POWER−ON−RESET (POR)
POR startup voltage
POR shutdown voltage
POR hysteresis
Symbol
Conditions
Min
Typ
Max
Units
Screened
VDDC
0.775
0.755
13.8
0.803
0.784
19.1
0.837
0.821
22.0
V
V
STARTUP
SHUTDOWN
HYSTERESIS
VDDC
POR
mV
ms
POR duration
T
POR
11.0
11.6
12.3
DIGITAL PADS
Voltage level for high input
V
VBAT
* 0.8
−
−
−
V
V
√
√
√
√
IH
Voltage level for low input
Voltage level for high output
Voltage level for low output
V
−
VBAT
* 0.2
IL
V
OH
2 mA source current
2 mA sink current
VDDO
* 0.8
−
−
V
V
OL
−
−
VDDO
* 0.2
V
Input capacitance for digital
pads
C
−
4
−
pF
kW
kW
%
IN
Pull−up resistance for digital
input pads
R
220
220
−1
270
270
0
320
320
+1
√
√
UP_IN
Pull−down resistance for
digital input pads
R
DOWN_IN
Sample rate tolerance
Rise and fall time
ESD
FS
Sample rate of 16 kHz or 32 kHz
Digital output pad
Tr, Tf
Human Body Model (HBM)
Machine Model (MM)
2
kV
V
200
200
Latch−up
V < GNDC, V > VBAT
mA
DIGITAL INTERFACES
I2C baud rate
System clock < 1.6 MHz
System clock > 1.6 MHz
System clock ≥ 5.12 MHz
−
−
−
−
−
1
100
400
−
kbps
kbps
Mbps
General−purpose UART
baud rate
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
3
BelaSigna 300 with AfterMaster HD
Environmental Characteristics
All BelaSigna 300 AM packages are Pb−free, RoHS−compliant and Green.
BelaSigna 300 AM parts are qualified against standards outlined in the following sections.
All BelaSigna 300 AM package options are Green (RoHS−compliant). Contact ON Semiconductor for supporting
documentation.
WLCSP Package Option
The solder ball composition for the WLCSP package is SAC266.
Table 3. WLCSP PACKAGE−LEVEL QUALIFICATION
Packaging Level
Table 4. WLCSP BOARD−LEVEL QUALIFICATION
Board Level
Moisture sensitivity level
JEDEC Level 1
Temperature
−40°C to 125°C for 2500
cycles with no failures
Thermal cycling test (TCT)
−55°C to 150°C for 500 cycles
85°C / 85% RH for 1000 hours
Highly accelerated stress
test (HAST)
High temperature stress
test (HTST)
150°C for 1000 hours
Mechanical Information and Circuit Design Guidelines
BelaSigna 300 AM is available in a 2.68 x 3.63 mm ultra−miniature wafer−level chip scale package (WLCSP)
1.8V
10uF
1uF
VDBL
To Host Controller
Or ADC/DAC
10uF
PCM_FR
PCM_SERO
PCM_SERI
PCM_CLK
SPI_CLK
SPI_CS
EEPROM
To Host Controller
as needed
SPI_SERO
SPI_SERI
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
BELASIGNA 300 DSP
SDA
SCL
To Programming Interface
VREG
~38MHz Clock
Source
EXT_CLK
1uF
1.8V
AI0
AI1
AI2
AI4
VBATRCVR
RESERVED
100nF
Figure 1. BelaSigna 300 with AfterMaster Layout Schematic
www.onsemi.com
4
BelaSigna 300 with AfterMaster HD
WLCSP Pin Out
A total of 35 active pins are present on the BelaSigna 300 AM WLCSP package. They are organized in a staggered array.
A description of these pins is given in Table 5.
Table 5. WLCSP PAD DESCRIPTIONS
Pad Index BelaSigna 300 AM Pad Name
Description
I/O
N/A
I
A/D
A
A1
A5
GNDRCVR
VBATRCVR
RCVR_HP+
RCVR+
Ground for output driver
Power supply for output stage / NC for AfterMaster
Extra output driver pad for high power mode / NC for AfterMaster*
Output from output driver / NC for AfterMaster*
Output from output driver / NC for AfterMaster*
Extra output driver pad for high power mode / NC for AfterMaster*
Charge pump capacitor pin 0
A
B2
O
A
C3
O
A
A3
RCVR−
O
A
B4
RCVR_HP−
CAP0
O
A
B6
N/A
N/A
O
A
C5
CAP1
Charge pump capacitor pin 1
A
A7
VDBL
Doubled voltage
A
B8
VBAT
Power supply
I
A
B10
A9
VREG
Regulated supply voltage / NC for AfterMaster*
Analog ground
O
A
AGND
N/A
I
A
A11
B12
A13
B14
D14
E13
C13
D12
E11
C9
AI4
Audio signal input 4 / NC for AfterMaster*
Audio signal input 2/output signal from preamp 2 / GND for AfterMaster*
Audio signal input 1/output signal from preamp 1 / GND for AfterMaster*
Audio signal input 0/output signal from preamp 0 / GND for AfterMaster*
General−purpose I/O 4/low speed AD input 4
General−purpose I/O 3/low speed AD input 3
General−purpose I/O 2/low speed AD input 2
General−purpose I/O 1/low speed AD input 1/and UART RX
General−purpose I/O 0/UART TX
A
AI2/LOUT2
AI1/LOUT1
AI0/LOUT0
GPIO[4]/LSAD[4]
GPIO[3]/LSAD[3]
GPIO[2]/LSAD[2]
GPIO[1]/LSAD[1]/UART−RX
GPIO[0]/UART−TX
GNDC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/A
I/O
I/O
I/O
O
A
A
A
A/D
A/D
A/D
A/D
A/D
A
Digital ground
C11
D10
E9
SDA (I2C)
SCL (I2C)
EXT_CLK
VDDC
I2C data
D
I2C clock
D
External clock input/internal clock output
Core logic power
D
D8
A
E7
SPI_CLK
Serial peripheral interface clock
O
D
C7
SPI_SERI
SPI_CS
Serial peripheral interface input
I
D
D6
Serial peripheral interface chip select
Serial peripheral interface output
O
D
E5
SPI_SERO
PCM_FR
O
D
D4
PCM interface frame
I/O
I
D
E3
PCM_SERI
PCM_SERO
PCM_CLK
Reserved
PCM interface input
D
D2
PCM interface output
O
D
C1
PCM interface clock
I/O
D
E1
Reserved / GND for AfterMaster
*NC = Not Connected.
www.onsemi.com
5
BelaSigna 300 with AfterMaster HD
WLCSP Assembly / Design Notes
For PCB manufacture with BelaSigna 300 AM WLCSP,
ON Semiconductor recommends solder−on−pad (SoP)
surface finish. With SoP, the solder mask opening should be
non−solder mask−defined (NSMD) and copper pad
geometry will be dictated by the PCB vendor’s design
requirements.
can be either a GPIO or an LSAD depending on the
configuration. Note that GPIO0 cannot be used as an LSAD.
Inter−IC Communication (I2C) Interfaces
2
The I C interface is an industry−standard interface that
can be used for high−speed transmission of data between
BelaSigna 300 AM and an external device. The interface
operates at speeds up to 400 Kbit/sec for system clocks
(EXT_CLK) higher than 1.6 MHz. In product development
Alternative surface finishes are ENiG and OSP; volume
of screened solder paste (#5) should be less than
3
0.0008 mm . If no pre−screening of solder paste is used,
2
mode, the I C interface is used for application debugging
then following conditions must be met:
1. the solder mask opening should be >0.3 mm in
diameter,
purposes, communicating with the BelaSigna 300 AM
development tools. The interface can be configured to
operate in either master mode or slave mode.
2. the copper pad will have 0.25 mm diameter, and
3. soldermask thickness should be less than 1 mil
thick above the copper surface.
Serial Peripheral Interface (SPI) Port
An SPI port is available on BelaSigna 300 AM for
applications such as communication with a non−volatile
memory (EEPROM). The I/O levels on this port are defined
by the VBAT. The SPI port operates in master mode only,
which supports communications with slave SPI devices.
The SPI port on BelaSigna 300 AM only supports master
mode, so it will only communicate with SPI slave devices.
When connecting to an SPI slave device other than a boot
EEPROM, the SPI_CS pin should be left unconnected and the
slave device CS line should be driven from a GPIO to avoid
BelaSigna 300 AM boot malfunction. When connecting to an
SPI EEPROM for boot, the designer can choose to connect
the SPI_CS pin to the EEPROM or use a GPIO (high at boot)
for a design with several daisy-chained SPI devices.
ON Semiconductor can provide BelaSigna 300 AM
WLCSP land pattern CAD files to assist your PCB design
upon request.
WLCSP Weight
BelaSigna 300 AM WLCSP (B300W35A109XXG) has
an average weight of 0.095 grams.
Digital Interfaces
General−Purpose Input Output (GPIO) Ports
BelaSigna 300 AM has five GPIO ports that can connect to
external digital inputs such as push buttons, or digital outputs
such as the control or trigger of an external companion chip
(GPIO[0..4]). The direction of these ports (input or output) is
configurable and each pin has an internal pull−up resistor
when configured as a GPIO. A read from an unconnected pin
will give a value of logic 1. Four of the five GPIO pins are
multiplexed with an LSAD (see the Low−Speed A.D
Converters section) and as such the functionality of the pin
PCM Interface
BelaSigna 300 AM includes a highly configurable pulse
code modulation (PCM) interface that can be used to stream
audio signal data into and out of the device. The I/O levels
on this port are defined by the voltage on the VBAT pin.
www.onsemi.com
6
BelaSigna 300 with AfterMaster HD
Assembly Information
CARRIER DETAILS
2.6 x 3.8 mm WLCSP
ON Semiconductor offers tape and reel packing for BelaSigna 300 AM WLCSP. The packing consists of a pocketed carrier
tape, a cover tape, and a molded anti−static polystyrene reel. The carrier and cover tape create an ESD safe environment,
protecting the components from physical and electrostatic damage during shipping and handling.
Pin 1
Quantity per Reel: 2500 units
Pin 1 Orientation: Upper Left, Bumps down
Tape Brand / Width: Advantek / 12 mm
Pocket Pitch: 8 mm
A = 13 inches
B = 12 mm
C = 4 inches
D = 13 mm
ꢀ
P/N: BCB043
Reel Brand / Width: Advantek Lokreel / 13 in
Cover Tape: 3M 2666 PSA 9.3 mm
Figure 2. Package Orientation on Tape for WLCSP Package Option
10 sprockets hole pitch cumulative tolerance 0.1.
Camber in compliance with EIA 763.
Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
Figure 3. WLCSP Carrier Tape Drawing
www.onsemi.com
7
BelaSigna 300 with AfterMaster HD
Sample Shipping Label
Figure 4. Sample Shipping Label
Chip Identification
Re−Flow Information
The re−flow profile depends on the equipment that is used
for the re−flow and the assembly that is being re−flowed.
Information from JEDEC Standard 22−A113D and
J−STD−020D.01 can be used as a guideline.
Chip identification information can be retrieved by using
the Communications Accelerator Adaptor (CAA) tool along
with the protocol software provided by ON Semiconductor
(see CAA instruction manual). For BelaSigna 300 AM, the
key identifier components and values are as follows for the
different package options:
Electrostatic Discharge (ESD) Sensitive Device
CAUTION: ESD sensitive device. Permanent damage may
occur on devices subjected to high−energy electrostatic
discharges. Proper ESD precautions in handling, packaging
and testing are recommended to avoid performance
degradation or loss of functionality. Device is 2 kV HBM
ESD qualified.
Package
Option
Chip
Family
Chip
Version
Chip
Revision
WLCSP
0x03
0x02
0x0100
Support Software
A set of tools is available at http://onsemi.com for
downloading the proprietary AfterMaster HD algorithm to
BelaSigna 300 AM. An AfterMaster HD image is supplied
by ON Semiconductor, but must be downloaded to
BelaSigna 300 AM upon boot.
Miscellaneous
Ordering Information
To order BelaSigna 300 with AM, please contact your
account manager and ask for part number
B300W35A109A1G.
Training
To facilitate development on the BelaSigna 300 AM
platform, training is available upon request. Contact your
account manager for more information.
Company or Product Inquiries
For more information about ON Semiconductor products
or services visit our Web site at http://onsemi.com.
www.onsemi.com
8
BelaSigna 300 with AfterMaster HD
PACKAGE DIMENSIONS
WLCSP35, 3.63x2.68
CASE 567AG
ISSUE B
D
A
NOTES:
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
PIN A1
REFERENCE
MILLIMETERS
DIM
A
A1
A2
b
MIN
0.84
0.17
0.72 REF
0.24
MAX
1.00
0.23
E
0.29
C
D
E
eD
eE
0.125 BSC
3.63 BSC
2.68 BSC
0.25 BSC
0.433 BSC
2X
0.10
C
2X
0.10
C
TOP VIEW
A2
A
0.10
C
0.05
C
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
NOTE 3
C
A1
SIDE VIEW
PACKAGE
OUTLINE
eD
A1
C
0.433
PITCH
35X
b
0.05
0.03
C
C
A B
E
D
C
B
A
eE
35X
0.25
0.250
PITCH
0.125
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
14 13 12 11 10
9 8 7 6 5 4 3 2 1
BOTTOM VIEW
BelaSigna is a registered trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
B300AM/D
相关型号：
©2020 ICPDF网 联系我们和版权申明