74HC574 [ONSEMI]
Octal 3−State Noninverting D Flip−Flop; 八路三态同相D触发器
| 型号： | 74HC574 |
| 厂家： | 
ONSEMI |
| 描述： | Octal 3−State Noninverting D Flip−Flop |
| 文件： | 总8页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC574
Octal 3−State Noninverting
D Flip−Flop
High−Performance Silicon−Gate CMOS
The 74HC574 is identical in pinout to the LS574. The device inputs
are compatible with standard CMOS outputs; with pull−up resistors,
they are compatible with LSTTL outputs.
Data meeting the set−up time is clocked to the outputs with the
rising edge of the Clock. The Output Enable input does not affect the
states of the flip−flops but when Output Enable is high, all device
outputs are forced to the high−impedance state. Thus, data may be
stored even when the outputs are not enabled.
http://onsemi.com
MARKING
DIAGRAMS
20
1
HC
574
TSSOP−20
DT SUFFIX
CASE 948E
20
The HC574 is identical in function to the HC374A but has the
flip−flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
ALYW G
1
G
Features
HC574 = Device Code
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 266 FETs or 66.5 Equivalent Gates
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
• This is a Pb−Free Device
©
Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
March, 2007 − Rev. 1
74HC574/D
74HC574
OUTPUT
1
2
20
19
18
17
16
15
14
13
12
11
V
CC
ENABLE
D0
Q0
D1
D2
3
Q1
FUNCTION TABLE
4
Q2
Inputs
Clock
Output
OE
D
Q
D3
5
Q3
L
L
L
H
L
X
X
H
D4
6
Q4
L
No Change
Z
D5
7
Q5
L,H,
X
H
D6
8
Q6
X = Don’t Care
Z = High Impedance
D7
9
Q7
GND
10
CLOCK
Figure 1. Pin Assignment
2
3
4
5
6
7
8
19
D0
D1
D2
D3
D4
D5
D6
Q0
18
17
16
15
14
13
Q1
Q2
Q3
Q4
Q5
Q6
NONINVERTING
OUTPUTS
DATA
INPUTS
9
11
1
12
D7
Q7
CLOCK
PIN 20 = V
PIN 10 = GND
CC
OUTPUT ENABLE
Figure 2. Logic Diagram
Design Criteria
Value
Units
Internal Gate Count*
66.5
ea.
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
1.5
5.0
ns
mW
pJ
0.0075
*Equivalent to a two−input NAND gate.
http://onsemi.com
2
74HC574
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
DC Supply Voltage
*0.5 to )7.0
CC
V
DC Input Voltage
*0.5 to V )0.5
V
I
O
CC
V
DC Output Voltage
(Note 1)
*0.5 to V )0.5
V
CC
I
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
$20
mA
mA
mA
mA
mA
_C
IK
I
$35
OK
I
$35
O
I
$75
CC
I
$75
GND
T
*65 to )150
STG
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
260
_C
L
T
)150
_C
_C/W
mW
J
q
TSSOP
TSSOP
128
450
JA
P
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
D
MSL
Level 1
F
Flammability Rating
Oxygen Index: 30% − 35%
UL 94 V−0 @ 0.125 in
R
V
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
>2000
>200
V
ESD
I
Latchup Performance
Above V and Below GND at 85_C (Note 4)
$300
mA
Latchup
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. I absolute maximum rating must be observed.
O
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to EIA/JESD78.
5. For high frequency or heavy load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
6.0
CC
V , V
DC Input Voltage, Output Voltage
V
CC
V
I
O
T
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 3)
*55
)125
_C
ns
A
t , t
r
V
V
V
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
f
CC
CC
CC
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
ORDERING INFORMATION
†
Device
Package
Shipping
74HC574DTR2G
TSSOP−20*
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
3
74HC574
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
V
Guaranteed Limit
CC
(V)
Symbol
Parameter
Test Conditions
= V – 0.1 V
*55 to 25_C v85_C v125_C
Unit
V
Minimum High−Level Input
V
out
2.0
3.0
4.5
6.0
1.5
2.1
1.5
2.1
1.5
2.1
V
IH
out
CC
Voltage
|I | v 20 mA
3.15
4.2
3.15
4.2
3.15
4.2
V
Maximum Low−Level Input
Voltage
V
out
= 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
IL
out
|I | v 20 mA
V
V
Minimum High−Level Output
V
out
= V
IH
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
OH
OH
in
Voltage
|I | v 20 mA
Minimum High−Level Output
Voltage
V
V
= V
= V
|I | v 2.4 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
in
IH
out
|I | v 6.0 mA
out
|I | v 7.8 mA
out
V
Maximum Low−Level Output
Voltage
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
OL
in
IL
|I | v 20 mA
out
V
= V
|I | v 2.4 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
in
in
IL
out
|I | v 6.0 mA
out
|I | v 7.8 mA
out
I
Maximum Input Leakage
Current
V
= V or GND
6.0
$0.1
$1.0
$1.0
mA
mA
in
CC
I
Maximum Three−State
Leakage Current
Output in High−Impedance State
= V or V
6.0
$0.5
$5.0
$10
OZ
V
in
IL
IH
V
= V or GND
out
CC
I
Maximum Quiescent Supply
Current (per Package)
V
out
= V or GND
6.0
4.0
40
40
mA
CC
in
CC
I
= 0 mA
7. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
http://onsemi.com
4
74HC574
AC ELECTRICAL CHARACTERISTICS (C = 50 pF; Input t = t = 6.0 ns)
L
r
f
V
Guaranteed Limit
CC
(V)
Symbol
Parameter
*55 to 25_C v85_C v125_C
Unit
f
Maximum Clock Frequency (50% Duty Cycle)
(Figures 3 and 6)
2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
MHz
max
24
t
t
t
,
Maximum Propagation Delay, Clock to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
160
105
32
200
145
40
240
190
48
ns
ns
ns
ns
PLH
t
PHL
27
34
41
,
Maximum Propagation Delay, Output Enable to Q
(Figures 4 and 7)
2.0
3.0
4.5
6.0
150
100
30
190
125
38
225
150
45
PLZ
t
PHZ
26
33
38
,
Maximum Propagation Delay, Output Enable to Q
(Figures 4 and 7)
2.0
3.0
4.5
6 0
140
90
28
24
175
120
35
210
140
42
PZL
t
PZH
30
36
t
,
Maximum Output Transition Time, any Output
(Figures 3 and 6)
2.0
3.0
4.5
6.0
60
27
12
10
75
32
15
13
90
36
18
15
TLH
t
THL
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
out
Maximum Three−State Output Capacitance, Output in High−Impedance
State
8. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V
CC
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
24
pF
2
*Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
. For load considerations, see the ON
D
PD CC
CC CC
Semiconductor High−Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (C = 50 pF; Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
V
– 55 to 25_C
v 85_C
v 125_C
CC
Symbol
Parameter
Figure
(V)
Min
Max
Min
Max
Min
Max
Unit
t
Minimum Setup Time, Data to Clock
5
2.0
3.0
4.6
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
su
t
Minimum Hold Time, Clock to Data
Minimum Pulse Width, Clock
5
3
3
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
ns
ns
h
t
2.0
3.0
4.5
6.0
75
60
15
13
95
80
19
16
110
90
22
19
w
t , t
r
Maximum Input Rise and Fall Times
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
f
http://onsemi.com
5
74HC574
SWITCHING WAVEFORMS
t
t
f
r
3.0 V
GND
V
CC
1.3 V
90%
50%
10%
CLOCK
GND
t
t
PLZ
PZL
t
w
HIGH
IMPEDANCE
1/f
1.3 V
max
Q
Q
10%
90%
V
V
OL
t
t
PHL
PLH
t
t
PHZ
PZH
90%
50%
10%
OH
Q
HIGH
IMPEDANCE
t
t
THL
TLH
Figure 3.
Figure 4.
TEST POINT
OUTPUT
VALID
V
DEVICE
UNDER
TEST
CC
DATA
50%
C *
L
GND
t
t
h
su
V
CC
CLOCK
50%
GND
*Includes all probe and jig capacitance.
Figure 5.
Figure 6.
C
Q
19
18
Q0
Q1
2
3
4
5
D0
D
C
Q
D1
D2
D3
D
C
Q
17
16
Q2
Q3
D
C
Q
TEST POINT
1 kW
D
CONNECT TO V WHEN
CC
OUTPUT
TESTING t
AND t
.
PLZ
PZL
C
Q
15
14
DEVICE
UNDER
TEST
Q4
Q5
6
7
CONNECT TO GND WHEN
TESTING t AND t
D4
D5
D
.
PZH
PHZ
C *
L
C
Q
D
C
Q
13
12
*Includes all probe and jig capacitance.
Q6
Q7
8
9
D6
D7
D
Figure 7. Test Circuit
C
Q
D
11
CLOCK
1
OUTPUT ENABLE
Figure 8. Expanded Logic Diagram
http://onsemi.com
6
74HC574
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
K
K1
M
S
S
V
0.10 (0.004)
T U
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
0.15 (0.006) T U
J J1
20
11
2X L/2
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
F
A
B
6.40
4.30
−−−
0.252
0.169
DETAIL E
C
−−− 0.047
0.006
0.030
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
7
74HC574
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
74HC574/D
相关型号：
74HC574D-T
IC HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SO-20, Bus Driver/Transceiver
NXP
74HC574DB
IC HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 5.30 MM, PLASTIC, MO-150, SOT339-1, SSOP-20, Bus Driver/Transceiver
NXP
74HC574DB-T
IC HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SSOP-20, Bus Driver/Transceiver
NXP
©2020 ICPDF网 联系我们和版权申明