74AUP1G56FHX [ONSEMI]
TinyLogic® 低功率通用可配置双输入逻辑门（漏极开路输出）;
| 型号： | 74AUP1G56FHX |
| 厂家： | 
ONSEMI |
| 描述： | TinyLogic® 低功率通用可配置双输入逻辑门（漏极开路输出） |
| 文件： | 总12页 (文件大小：517K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Is Now Part of
To learn more about ON Semiconductor, please visit our website at
www.onsemi.com
Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers
will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor
product management systems do not have the ability to manage part nomenclature that utilizes an underscore
(_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain
device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated
device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please
email any questions regarding the system integration to Fairchild_questions@onsemi.com.
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right
to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON
Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out
of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor
is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
September 2012
74AUP1G56
TinyLogic® Low Power Universal Configurable
Two-Input Logic Gate (Open Drain Output)
Features
Description
The 74AUP1G56 is a universal, configurable, two-input
logic gate with an open drain that provides a high-
performance and low-power solution for battery-
powered portable applications. This product is
designed for a wide low-voltage operating range (0.8 V
to 3.6 V) and guarantees very low static and dynamic
power consumption across the entire voltage range. All
inputs are implemented with hysteresis to allow for
slower transition input signals and better switching
noise immunity.
.
.
0.8 V to 3.6 V VCC Supply Operation
3.6 V Over-Voltage Tolerant I/Os at VCC
from 0.8V to 3.6 V
.
Extremely High Speed tPD
- 3.2 ns: Typical at 3.3 V
.
.
Power-Off High-Impedance Inputs and Outputs
Low Static Power Consumption
- ICC=0.9 µA Maximum
The 74AUP1G56 provides for multiple functions, as
determined by various configurations of the three inputs.
The potential logic functions provided are AND, NAND,
OR, NOR, XNOR, inverter, and buffer (see Figure 2
through Figure 8).
.
.
Low Dynamic Power Consumption
- CPD=3.0 pF Typical at 3.3 V
Ultra-Small MicroPak™ Packages
Ordering Information
Part Number
74AUP1G56L6X
74AUP1G56FHX
Top Mark
Package
Packing Method
AK
AK
6-Lead, MicroPak™, 1.0 mm Wide
5000 Units on Tape & Reel
5000 Units on Tape & Reel
6-Lead, MicroPak2™, 1x1 mm Body, .35 mm Pitch
© 2008 Fairchild Semiconductor Corporation
74AUP1G56 • Rev. 1.0.2
www.fairchildsemi.com
Pin Configuration
B
GND
A
C
V
1
2
3
6
5
4
CC
Y
Figure 1. MicroPak™ (Top Through View)
Pin Definitions
Pin #
Name
Description
1
2
3
4
5
6
B
GND
A
Data Input
Ground
Data Input
Y
Output (Open Drain)
Supply Voltage
Data Input
VCC
C
Function Table
Inputs
Y=Output
C
L
B
L
A
L
H(1)
L
H(1)
L
L
H
L
L
H
H
L
L
H
L
L
H
H
H
L
L
H
L
L
H
H
H(1)
H(1)
H
H
H = HIGH Logic Level
L = LOW Logic Level
Note:
1. High impedance output state, open drain.
Function Selection Table
2-Input Logic Function
2-Input AND
Connection Configuration
Figure 2
2-Input AND with Both Inputs Inverted
2-Input NAND with Inverted Input
2-Input OR with Inverted Input
2-Input NOR
Figure 5
Figure 3, Figure 4
Figure 3, Figure 4
Figure 5
2-Input NOR with Both Inputs Inverted
2-Input XNOR
Figure 2
Figure 6
Inverter
Figure 7
Buffer
Figure 8
© 2008 Fairchild Semiconductor Corporation
74AUP1G56 • Rev. 1.0.2
www.fairchildsemi.com
2
Logic Configurations
Figure 2 through Figure 8 show the logical functions that
can be implemented using the 74AUP1G56. The
diagrams show the DeMorgan’s equivalent logic duals
implementation is next to the board-level physical
implementation of how the pins should be connected.
for
a
given two-input function. The logical
VCC
V
CC
B
Y
B
B
C
Y
Y
B
1
2
3
6
5
4
C
Y
1
2
3
6
5
4
C
Y
C
B
C
B
C
Y
Figure 2. 2-Input AND Gate or 2-Input NOR
with Both Inputs Inverted
Figure 3. 2-Input NAND with Inverted B Input or
2-Input OR Gate with Inverted C Input
VCC
VCC
A
A
Y
Y
Y
1
2
3
6
5
4
C
Y
C
1
2
3
6
5
4
C
Y
C
A
C
A
C
A
A
Y
Figure 4. 2-Input NAND with Inverted C Input or Figure 5. 2-Input NOR Gate or 2-Input AND Gate with
2-Input OR Gate with Inverted A Input Both Inputs Inverted
VCC
VCC
1
2
3
6
5
4
B
1
2
3
6
5
4
C
Y
A
Y
B
C
Y
Y
A
Figure 7. Inverter
Figure 6. 2-Input XNOR Gate
VCC
B
1
2
3
6
B
Y
5
4
Y
Figure 8. Non-Inverter Buffer
© 2008 Fairchild Semiconductor Corporation
74AUP1G56 • Rev. 1.0.2
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Min.
-0.5
-0.5
-0.5
Max.
4.6
Unit
V
Supply Voltage
VIN
DC Input Voltage
DC Output Voltage(2)
4.6
V
VOUT
4.6
V
IIK
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
VIN < 0V
VOUT < 0V
-50
-50
mA
mA
IOK
IOL
ICC or IGND
TSTG
+50
±50
mA
mA
°C
DC VCC or Ground Current per Supply Pin
Storage Temperature Range
-65
+150
+150
+260
130
TJ
Junction Temperature Under Bias
Junction Lead Temperature, Soldering 10s
°C
TL
°C
MicroPak™-6
PD
Power Dissipation at +85°C
mW
V
MicroPak2™-6
120
Human Body Model, JEDEC:JESD22-A114
Charged Device Model, JEDEC:JESD22-C101
4000
2000
ESD
Note:
2. IO absolute maximum rating must be observed.
Recommended Operating Conditions(3)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Condition
Min.
Max.
Unit
VCC
VIN
Supply Voltage
0.8
0
3.6
3.6
V
V
Input Voltage
VOUT
Output Voltage
VCC=0 V
0
3.6
V
VCC=3.0 V to 3.6 V
VCC=2.3 V to 2.7 V
VCC=1.65 V to 1.95 V
VCC=1.4 V to 1.6 V
VCC=1.1 V to 1.3 V
VCC=0.8 V
4.0
3.1
1.9
mA
IOL
Output Current
1.7
1.1
20.0
µA
°C
TA
Operating Temperature, Free Air
Thermal Resistance
-40
+85
MicroPak™-6
MicroPak2™-6
500
560
°C/W
θJA
Note:
3. Unused inputs must be held HIGH or LOW. They may not float.
© 2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74AUP1G56 • Rev. 1.0.2
4
DC Electrical Characteristics
TA=25°C
Min.
TA=-40 to 85°C
Symbol Parameter
VCC
Condition
Unit
Max.
0.60
0.90
1.11
1.29
1.77
2.29
0.60
0.65
0.75
0.84
1.04
1.24
0.50
0.46
0.56
0.66
0.92
1.31
0.10
Min.
0.30
0.53
0.74
0.91
1.37
1.88
0.10
0.26
0.39
0.47
0.69
0.88
0.07
0.08
0.18
0.27
0.53
0.79
Max.
0.60
0.90
1.11
1.29
1.77
2.29
0.60
0.65
0.75
0.84
1.04
1.24
0.50
0.46
0.56
0.66
0.92
1.31
0.10
0.80
1.10
0.30
0.53
0.74
0.91
1.37
1.88
0.10
0.26
0.39
0.47
0.69
0.88
0.07
0.08
0.18
0.27
0.53
0.79
Positive
1.40
VP
VN
VH
Threshold
Voltage
V
1.65
2.30
3.00
0.80
1.10
Negative
Threshold
Voltage
1.40
V
V
1.65
2.30
3.00
0.80
1.10
1.40
Hysteresis
Voltage
1.65
2.30
3.00
IOL=20 µA
0.80 ≤ VCC ≤ 3.60
0.30 x
VCC
0.30 x
VCC
IOL=1.1 mA
1.10 ≤ VCC ≤ 1.30
IOL=1.7 mA
IOL=1.9 mA
0.31
0.31
0.37
0.35
1.40 ≤ VCC ≤ 1.60
1.65 ≤ VCC ≤ 1.95
LOW Level
Output Voltage
VOL
V
IOL=3.1 mA
0.44
0.45
2.30 ≤ VCC ≤ 2.70
IOL=4.0 mA
0.44
±0.1
0.45
±0.5
2.70 ≤ VCC ≤ 3.60
Input Leakage
Current
IIN
0 V to 3.6 V
µA
µA
0 ≤ VIN ≤ 3.6 V
Power Off
Leakage
Current
IOFF
0 V
0.2
0.6
0.6
0 ≤ (VIN,VO)≤ 3.6 V
Additional
Power Off
Leakage
Current
VIN or VO = 0 V to
0V to 0.2 V
0.2
0.5
µA
ΔIOFF
3.6 V
VIN - VCC or GND
0.9
Quiescent
Supply Current
ICC
0.8V to 3.6 V
3.3 V
µA
µA
±0.9
VCC ≤ VIN ≤ 3.6 V
Increase in ICC
per Input
VIN=VCC -0.6 V
40.0
50.0
ΔICC
© 2008 Fairchild Semiconductor Corporation
74AUP1G56 • Rev. 1.0.2
www.fairchildsemi.com
5
AC Electrical Characteristics
TA=25°C
TA=-40 to 85°C
Symbol Parameter
VCC
Condition
Unit
Min. Typ. Max. Min.
Max.
0.80
30
1.0
1.0
1.0
1.0
1.0
10.1
6.6
6.3
4.7
4.6
18.9
11.4
8.7
1.0
1.0
1.0
1.0
1.0
19.9
12.2
9.7
1.10 ≤ VCC ≤ 1.30
1.40 ≤ VCC ≤ 1.60
1.65 ≤ VCC ≤ 1.95
2.30 ≤ VCC ≤ 2.70
3.00 ≤ VCC ≤ 3.60
CL=15 pF,
RU=RD=5 KΩ
VI = 2 x (VCC
Propagation
tPZL, tPLZ
ns
Delay
)
(see Figure 9)
6.9
7.5
6.8
7.4
Input
CIN
0
0
0.8
1.7
pF
pF
Capacitance
Output
COUT
Capacitance
0.80
3.0
3.1
3.2
3.4
3.8
4.4
1.10 ≤ VCC ≤ 1.30
1.40 ≤ VCC ≤ 1.60
1.65 ≤ VCC ≤ 1.95
2.30 ≤ VCC ≤ 2.70
3.00 ≤ VCC ≤ 3.60
Power
VIN=0 V or VCC
f=10 MHz
,
CPD
Dissipation
pF
Capacitance
© 2008 Fairchild Semiconductor Corporation
74AUP1G56 • Rev. 1.0.2
www.fairchildsemi.com
6
AC Loadings and Waveforms
Notes:
4. CL includes load and stray capacitance.
5. Input PRR = 1.0 MHz, tW = 500 ns.
Figure 9.
AC Test Circuit
Figure 10. AC Waveforms
VCC
3.3 V ± 0.3 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 1.5 V ± 0.10 V 1.2 V ± 0.10 V
Symbol
0.8 V
VCC/2
Vmi
Vx
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VOL + 0.3 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.1 V
VOL + 0.1 V
VOL + 0.1 V
© 2008 Fairchild Semiconductor Corporation
74AUP1G56 • Rev. 1.0.2
www.fairchildsemi.com
7
Physical Dimensions
2X
0.05 C
1.45
B
(1)
2X
0.05 C
(0.49)
5X
(0.254)
1.00
(0.75)
(0.52)
1X
A
TOP VIEW
PIN 1 IDENTIFIER
5
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.45
0.35
0.10
6X
0.00
0.25
6X
0.15
1.0
DETAIL A
0.10
C B A
0.40
0.30
0.05
C
0.35
0.25
5X
5X
0.40
0.30
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
0.5
BOTTOM VIEW
(0.05)
6X
(0.13)
4X
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 11. 6-Lead, MicroPak™, 1.0 mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
5000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
L6X
Trailer (Hub End)
75 (Typical)
Empty
© 2008 Fairchild Semiconductor Corporation
74AUP1G56 • Rev. 1.0.2
www.fairchildsemi.com
8
Physical Dimensions
0.89
0.35
0.05
C
1.00
B
A
2X
5X 0.40
1X 0.45
PIN 1
0.66
MIN 250uM
1.00
6X 0.19
0.05
C
C
TOP VIEW
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
2X
0.90
0.35
0.05
0.55MAX
C
5X 0.52
SIDE VIEW
0.73
0.57
1X
(0.08) 4X
DETAIL A
0.09
0.19
6X
1
2
3
0.20 6X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
(0.05) 6X
0.35
5X
0.25
0.60
6
5
4
0.10
.05 C
C B A
0.40
0.30
0.35
(0.08)
4X
BOTTOM VIEW
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
0.075X45°
CHAMFER
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
DETAIL A
PIN 1 LEAD SCALE: 2X
E. DRAWING FILENAME AND REVISION: MGF06AREV3
Figure 12. 6-Lead, MicroPak2™, 1x1 mm Body, .35 mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
5000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
FHX
Trailer (Hub End)
75 (Typical)
Empty
© 2008 Fairchild Semiconductor Corporation
74AUP1G56 • Rev. 1.0.2
www.fairchildsemi.com
9
© 2008 Fairchild Semiconductor Corporation
74AUP1G56 • Rev. 1.0.2
www.fairchildsemi.com
10
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
© Semiconductor Components Industries, LLC
www.onsemi.com
相关型号：
74AUP1G56L6X
TinyLogic® Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明