74AUP1G57 [NXP]
Low-power configurable multiple function gate; 低功耗可配置多功能门
| 型号： | 74AUP1G57 |
| 厂家： | 
NXP |
| 描述： | Low-power configurable multiple function gate |
| 文件： | 总22页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AUP1G57
Low-power configurable multiple function gate
Rev. 01. — 16 January 2006
Preliminary data sheet
1. General description
The 74AUP1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G57 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT− is defined as the input
hysteresis voltage VH.
2. Features
■ Wide supply voltage range from 0.8 V to 3.6 V
■ High noise immunity
■ ESD protection:
◆ HBM JESD22-A114-C Class 3A. Exceeds 5000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101-C exceeds 1000 V
■ Low static power consumption; ICC = 0.9 µA (maximum)
■ Latch-up performance exceeds 100 mA per JESD 78 Class II
■ Inputs accept voltages up to 3.6 V
■ Low noise overshoot and undershoot < 10 % of VCC
■ IOFF circuitry provides partial Power-down mode operation
■ Multiple package options
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3 ns.
Symbol Parameter
Conditions
CL = 5 pF; RL = 1 MΩ;
CC = 0.8 V
CL = 5 pF; RL = 1 MΩ;
CC = 1.1 V to 1.3 V
CL = 5 pF; RL = 1 MΩ;
CC = 1.4 V to 1.6 V
CL = 5 pF; RL = 1 MΩ;
CC = 1.65 V to 1.95 V
CL = 5 pF; RL = 1 MΩ;
CC = 2.3 V to 2.7 V
CL = 5 pF; RL = 1 MΩ;
CC = 3.0 V to 3.6 V
Min
Typ
Max
Unit
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH
-
22.6
-
ns
V
propagation delay
A, B and C to Y
2.8
2.2
2.1
2.0
1.8
6.5
4.6
3.9
3.1
2.8
12.6
7.6
6.2
4.5
3.9
ns
ns
ns
ns
ns
V
V
V
V
V
CI
input capacitance
-
-
-
1.1
3.4
4.5
-
-
-
pF
pF
pF
[1] [2]
[1] [2]
CPD
power dissipation
capacitance
VCC = 1.8 V; f = 1 MHz
VCC = 3.3 V; f = 1 MHz
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] The condition is VI = GND to VCC
.
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature range Name
Description
Version
SOT363
74AUP1G57GW
74AUP1G57GM
−40 °C to +125 °C
−40 °C to +125 °C
SC-88
plastic surface mounted package; 6 leads
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
74AUP1G57GF
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
2 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
5. Marking
Table 3:
Marking
Type number
Marking code
74AUP1G57GW
74AUP1G57GM
74AUP1G57GF
aC
aC
aC
6. Functional diagram
3
1
6
A
B
C
4
Y
001aab583
Fig 1. Logic symbol
7. Pinning information
7.1 Pinning
74AUP1G57
B
GND
A
1
2
3
6
5
C
74AUP1G57
1
2
3
6
B
C
V
Y
CC
5
4
GND
A
V
CC
4
Y
001aab592
Transparent top view
001aab591
Fig 2. Pin configuration SOT363 (SC-88)
Fig 3. Pin configuration SOT886 (XSON6)
74AUP1G57
B
GND
A
1
2
3
6
5
4
C
V
Y
CC
001aae058
Transparent top view
Fig 4. Pin configuration SOT891 (XSON6)
Rev. 01.00 — 16 January 2006
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
3 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
7.2 Pin description
Table 4:
Pin description
Symbol
Pin
1
Description
B
data input B
ground (0 V)
data input A
data output Y
supply voltage
data input C
GND
A
2
3
Y
4
VCC
C
5
6
8. Functional description
8.1 Function table
Table 5:
Function table[1]
Input
Output
C
L
B
L
A
L
Y
H
L
L
L
H
L
L
H
H
L
H
L
L
H
L
H
H
H
H
L
L
H
L
L
H
H
H
H
H
[1] H = HIGH voltage level;
L = LOW voltage level.
8.2 Logic configurations
Table 6:
Function selection table
Logic function
2-input AND
Figure
see Figure 5
see Figure 8
see Figure 6 and 7
see Figure 6 and 7
see Figure 8
see Figure 5
see Figure 9
see Figure 10
see Figure 11
2-input AND with both inputs inverted
2-input NAND with inverted input
2-input OR with inverted input
2-input NOR
2-input NOR with both inputs inverted
2-input XNOR
Inverter
Buffer
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
4 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
V
CC
V
CC
B
C
B
C
Y
Y
Y
Y
B
1
2
3
6
5
4
C
Y
B
1
2
3
6
5
4
C
Y
B
C
B
C
001aab585
001aab584
Fig 5. 2-input AND gate or 2-input NOR
gate with both inputs inverted
Fig 6. 2-input NAND gate with input B
inverted or 2-input OR gate with
inverted C input
V
CC
V
CC
A
C
A
C
Y
Y
Y
Y
1
2
3
6
5
4
C
Y
1
2
3
6
5
4
C
Y
A
C
A
A
C
A
001aab586
001aab587
Fig 7. 2-input NAND gate with input C
inverted or 2-input OR gate with
inverted A input
Fig 8. 2-input NOR gate or 2-input AND
gate with both inputs inverted
V
CC
V
CC
B
1
2
3
6
5
4
C
Y
1
2
3
6
5
4
B
C
Y
A
Y
A
Y
001aab588
001aab589
Fig 9. 2-input XNOR gate
Fig 10. Inverter
V
CC
B
1
2
3
6
5
4
B
Y
Y
001aab590
Fig 11. Buffer
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
5 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
9. Limiting values
Table 7:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
−0.5
-
Max
+4.6
−50
Unit
V
VCC
IIK
supply voltage
input clamping
current
VI < 0 V
mA
[1]
[1]
VI
input voltage
−0.5
+4.6
V
IOK
output clamping
current
VO < 0 V
-
−50
mA
VO
output voltage
active mode and
−0.5
+4.6
V
Power-down mode
IO
output current
VO = 0 V to VCC
-
-
±20
+50
mA
mA
ICC
quiescent supply
current
IGND
Tstg
Ptot
ground current
-
−50
mA
°C
storage temperature
−65
+150
250
[2]
total power
dissipation
Tamb = −40 °C to +125 °C
-
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are
observed.
[2] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
10. Recommended operating conditions
Table 8:
Recommended operating conditions
Symbol Parameter
Conditions
Min Max Unit
VCC
VI
supply voltage
input voltage
output voltage
0.8
0
3.6
3.6
VCC
3.6
V
V
V
V
VO
active mode
0
Power-down mode; VCC = 0 V
0
Tamb
ambient temperature
−40 +125 °C
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
6 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
11. Static characteristics
Table 9:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VOH
HIGH-state output voltage
VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
0.75 × VCC
1.11
1.32
2.05
1.9
2.72
2.6
VOL
LOW-state output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.2
±0.2
V
V
V
V
V
V
V
II
input leakage current
µA
µA
µA
IOFF
∆IOFF
power-off leakage current
additional power-off leakage VI or VO = 0 V to 3.6 V;
current
V
CC = 0 V to 0.2 V
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
additional quiescent supply VI = VCC − 0.6 V; IO = 0 A;
ICC
quiescent supply current
-
-
-
-
0.5
40
µA
µA
V
∆ICC
current
VCC = 3.3 V
CI
input capacitance
output capacitance
VI = GND or VCC; VCC = 0 V to 3.6 V
VO = GND; VCC = 0 V
-
-
1.1
1.7
-
-
pF
pF
CO
Tamb = −40 °C to +85 °C
VOH
HIGH-state output voltage
VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
0.7 × VCC
1.03
1.30
1.97
1.85
2.67
2.55
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
7 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
Table 9:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-state output voltage
VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.37
0.35
0.33
0.45
0.33
0.45
±0.5
±0.5
±0.6
V
V
V
V
V
V
V
II
input leakage current
µA
µA
µA
IOFF
power-off leakage current
∆IOFF
additional power-off leakage VI or VO = 0 V to 3.6 V;
current
V
CC = 0 V to 0.2 V
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
additional quiescent supply VI = VCC − 0.6 V; IO = 0 A;
current CC = 3.3 V
Tamb = −40 °C to +125 °C
VOH HIGH-state output voltage
ICC
quiescent supply current
-
-
-
-
0.9
50
µA
µA
V
∆ICC
V
VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
V
CC − 0.11 -
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
0.6 × VCC
0.93
1.17
1.77
1.67
2.40
2.30
-
-
-
-
-
-
-
VOL
LOW-state output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
V
0.33 × VCC
0.41
V
V
0.39
V
0.36
V
0.50
V
0.36
V
0.50
V
II
input leakage current
±0.75
±0.75
µA
µA
IOFF
power-off leakage current
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
8 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
Table 9:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
∆IOFF additional power-off leakage VI or VO = 0 V to 3.6 V;
-
-
±0.75
µA
current
V
CC = 0 V to 0.2 V
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
additional quiescent supply VI = VCC − 0.6 V; IO = 0 A;
current CC = 3.3 V
ICC
quiescent supply current
-
-
-
-
1.4
75
µA
µA
V
∆ICC
V
12. Dynamic characteristics
Table 10: Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13
[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C; CL = 5 pF
tPHL, tPLH HIGH-to-LOW and
see Figure 12
LOW-to-HIGH propagation
delay A, B and C to Y
VCC = 0.8 V
-
22.6
6.5
4.6
3.9
3.1
2.8
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.8
2.2
2.1
2.0
1.8
12.6
7.6
6.2
4.5
3.9
Tamb = 25 °C; CL = 10 pF
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH propagation
delay A, B and C to Y
see Figure 12
VCC = 0.8 V
-
26.1
7.3
5.2
4.5
3.7
3.4
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.2
2.6
2.5
2.4
2.3
14.4
8.7
7.0
5.2
4.6
Tamb = 25 °C; CL = 15 pF
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH propagation
delay A, B and C to Y
see Figure 12
VCC = 0.8 V
-
31.6
8.0
5.7
4.9
4.1
3.8
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.4
2.8
2.6
2.6
2.5
15.7
9.4
7.7
5.7
5.0
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
9 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
Table 10: Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13
[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C; CL = 30 pF
tPHL, tPLH HIGH-to-LOW and
see Figure 12
LOW-to-HIGH propagation
delay A, B and C to Y
VCC = 0.8 V
-
37.8
10.4
7.4
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
4.6
3.6
3.5
3.4
3.2
20.9
12.2
9.9
7.4
6.6
6.2
5.2
4.9
Tamb = 25 °C
[2] [3]
CPD
power dissipation capacitance f = 1 MHz
VCC = 0.8 V
-
-
-
-
-
-
2.9
3.0
3.2
3.4
3.9
4.5
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
.
[2] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[3] The condition is VI = GND to VCC
.
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
10 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
Table 11: Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13
Symbol
Parameter
Conditions
−40 °C to +85 °C
Min Max
−40 °C to +125 °C
Min Max
Unit
CL = 5 pF
tPHL, tPLH HIGH-to-LOW and see Figure 12
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
2.5
2.5
2.0
1.8
1.5
13.0
2.5
2.5
2.0
1.8
1.5
13.2
ns
ns
ns
ns
ns
propagation delay
A, B and C to Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
8.2
6.8
5.1
4.1
8.6
7.2
5.3
4.3
CL = 10 pF
tPHL, tPLH HIGH-to-LOW and see Figure 12
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
2.8
2.8
2.2
2.1
1.9
14.9
9.3
7.8
5.9
4.9
2.8
2.8
2.2
2.1
1.9
15.2
9.8
8.2
6.2
5.1
ns
ns
ns
ns
ns
propagation delay
A, B and C to Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
CL = 15 pF
tPHL, tPLH HIGH-to-LOW and see Figure 12
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
3.1
3.1
2.5
2.4
2.2
16.7
10.4
8.7
3.1
3.1
2.5
2.4
2.2
17.0
10.9
9.2
ns
ns
ns
ns
ns
propagation delay
A, B and C to Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
6.5
6.9
5.5
5.7
CL = 30 pF
tPHL, tPLH HIGH-to-LOW and see Figure 12
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
3.9
3.8
3.1
3.1
2.8
21.8
13.4
11.1
8.3
3.9
3.8
3.1
3.1
2.8
22.3
14.1
11.8
8.8
ns
ns
ns
ns
ns
propagation delay
A, B and C to Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
7.0
7.4
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Preliminary data sheet
Rev. 01.00 — 16 January 2006
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Low power configurable multiple function gate
13. Waveforms
V
I
A, B, C input
GND
V
V
M
M
t
t
PLH
PHL
V
OH
V
V
V
M
Y output
M
V
OL
t
t
PLH
PHL
V
OH
Y output
V
M
M
V
OL
001aab593
Measurement points are given in Table 12.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 12. Input A, B and C to output Y propagation delay times
Table 12: Measurement points
Supply voltage
VCC
Output
VM
Input
VM
VI
tr = tf
0.8 V to 3.6 V
0.5 × VCC
0.5 × VCC
VCC
≤ 3.0 ns
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Preliminary data sheet
Rev. 01.00 — 16 January 2006
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74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
V
V
EXT
CC
5 kΩ
V
V
O
I
PULSE
GENERATOR
DUT
R
C
R
L
T
L
001aac521
Test data is given in Table 13.
Definitions for test circuit:
RL = Load resistance
CL = Load capacitance including jig and probe capacitance
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator
VEXT = External voltage for measuring switching times.
Fig 13. Load circuitry for switching times
Table 13: Test data
Supply voltage
VCC
Load
CL
VEXT
[1]
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF,
5 kΩ or 1 MΩ open
GND
2 × VCC
15 pF and 30 pF
[1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times
and pulse width RL = 1 MΩ.
14. Transfer characteristics
Table 14: Transfer characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VT+
positive-going
see Figure 14 and
threshold voltage Figure 15
VCC = 0.8 V
0.30
0.53
0.74
0.91
1.37
1.88
-
-
-
-
-
-
0.60
0.90
1.11
1.29
1.77
2.29
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
13 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
Table 14: Transfer characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VT− negative-going
Conditions
Min
Typ
Max
Unit
see Figure 14 and
threshold voltage Figure 15
VCC = 0.8 V
VCC = 1.1 V
0.10
0.26
0.39
0.47
0.69
0.88
-
-
-
-
-
-
0.60
0.65
0.75
0.84
1.04
1.24
V
V
V
V
V
V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VH
hysteresis voltage see Figure 14, Figure 15,
(VT+ − VT−)
Figure 16 and Figure 17
VCC = 0.8 V
0.07
0.08
0.18
0.27
0.53
0.79
-
-
-
-
-
-
0.50
0.46
0.56
0.66
0.92
1.31
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
Tamb = −40 °C to +85 °C
positive-going
VT+
VT−
VH
see Figure 14 and
threshold voltage Figure 15
VCC = 0.8 V
0.30
0.53
0.74
0.91
1.37
1.88
-
-
-
-
-
-
0.60
0.90
1.11
1.29
1.77
2.29
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
negative-going
see Figure 14 and
threshold voltage Figure 15
VCC = 0.8 V
0.10
0.26
0.39
0.47
0.69
0.88
-
-
-
-
-
-
0.60
0.65
0.75
0.84
1.04
1.24
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
hysteresis voltage see Figure 14, Figure 15,
(VT+ − VT−)
Figure 16 and Figure 17
VCC = 0.8 V
0.07
0.08
0.18
0.27
0.53
0.79
-
-
-
-
-
-
0.50
0.46
0.56
0.66
0.92
1.31
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
14 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
Table 14: Transfer characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +125 °C
VT+
VT−
VH
positive-going
threshold voltage Figure 15
see Figure 14 and
VCC = 0.8 V
0.30
0.53
0.74
0.91
1.37
1.88
-
-
-
-
-
-
0.62
0.92
1.13
1.31
1.80
2.32
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
negative-going
threshold voltage Figure 15
see Figure 14 and
VCC = 0.8 V
0.10
0.26
0.39
0.47
0.69
0.88
-
-
-
-
-
-
0.60
0.65
0.75
0.84
1.04
1.24
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
hysteresis voltage see Figure 14, Figure 15,
(VT+ − VT−)
Figure 16 and Figure 17
VCC = 0.8 V
0.07
0.08
0.18
0.27
0.53
0.79
-
-
-
-
-
-
0.50
0.46
0.56
0.66
0.92
1.31
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
15. Waveforms transfer characteristics
V
V
O
T+
V
I
V
H
V
T−
V
O
V
I
V
H
mna208
V
V
T+
T−
mna207
VT+ and VT− limits at 70 % and 20 %.
Fig 14. Transfer characteristic
Fig 15. Definition of VT+, VT− and VH
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
15 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
001aad691
240
I
CC
(µA)
160
80
0
0
0.4
0.8
1.2
1.6
2.0
V (V)
I
Fig 16. Typical transfer characteristics; VCC = 1.8 V
001aad692
1200
I
CC
(µA)
800
400
0
0
1.0
2.0
3.0
V (V)
I
Fig 17. Typical transfer characteristics; VCC = 3.0 V
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
16 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
16. Package outline
Plastic surface mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
97-02-28
04-11-08
SOT363
SC-88
Fig 18. Package outline SOT363 (SC-88)
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
17 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 19. Package outline SOT886 (XSON6)
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
18 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
L
L
1
e
6
5
4
e
1
e
1
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-03-11
05-04-06
SOT891
Fig 20. Package outline SOT891 (XSON6)
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
19 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
17. Abbreviations
Table 15: Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor Transistor Logic
18. Revision history
Table 16: Revision history
Document ID
Release date Data sheet status
<tbd> Preliminary data sheet
Change notice
Doc. number
Supersedes
74AUP1G57_1
-
-
-
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
20 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
19. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
20. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
22. Trademarks
Notice — All referenced brands, product names, service names and
21. Disclaimers
trademarks are the property of their respective owners.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
23. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
74AUP1G57_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 16 January 2006
21 of 22
74AUP1G57
Philips Semiconductors
Low power configurable multiple function gate
24. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
8.1
8.2
Functional description . . . . . . . . . . . . . . . . . . . 4
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Logic configurations . . . . . . . . . . . . . . . . . . . . . 4
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transfer characteristics. . . . . . . . . . . . . . . . . . 13
Waveforms transfer characteristics. . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 21
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Contact information . . . . . . . . . . . . . . . . . . . . 21
10
11
12
13
14
15
16
17
18
19
20
21
22
23
© Koninklijke Philips Electronics N.V. 2006
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 16 January 2006
Document number: 74AUP1G57_1
Published in The Netherlands
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SI9122E
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