2N7002W [ONSEMI]
Small Signal MOSFET 60 V, 340 mA, Single, N−Channel, SC−70; 小信号MOSFET 60 V 340 mA时，单N通道， SC- 70
| 型号： | 2N7002W |
| 厂家： | 
ONSEMI |
| 描述： | Small Signal MOSFET 60 V, 340 mA, Single, N−Channel, SC−70 |
| 文件： | 总5页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2N7002W
Small Signal MOSFET
60 V, 340 mA, Single, N−Channel, SC−70
Features
• ESD Protected
http://onsemi.com
• Low R
DS(on)
• Small Footprint Surface Mount Package
• This is a Pb−Free Device
V
R
DS(on)
MAX
I MAX
D
(Note 1)
(BR)DSS
60 V
1.6 W @ 10 V
2.5 W @ 4.5 V
340 mA
Applications
• Low Side Load Switch
• Level Shift Circuits
• DC−DC Converter
• Portable Applications i.e. DSC, PDA, Cell Phone, etc.
Simplified Schematic
1
2
Gate
MAXIMUM RATINGS (T = 25°C unless otherwise stated)
J
Rating
Drain−to−Source Voltage
Gate−to−Source Voltage
Symbol
Value
60
Unit
V
3
Drain
V
DSS
Source
V
±20
V
GS
Drain Current (Note 1)
Steady State
I
mA
D
T = 25°C
A
310
220
(Top View)
A
T = 85°C
t < 5 s
T = 25°C
A
340
240
A
T = 85°C
MARKING DIAGRAM
& PIN ASSIGNMENT
Power Dissipation (Note 1)
Steady State
t < 5 s
P
mW
D
280
330
Drain
3
Pulsed Drain Current (t = 10 ms)
I
1.4
A
p
DM
Operating Junction and Storage
Temperature Range
T , T
−55 to
°C
J
STG
+150
SC−70/SOT−323
CASE 419
71
G
Source Current (Body Diode)
I
250
260
mA
S
STYLE 8
1
2
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
°C
L
Gate
Source
Gate−Source ESD Rating
ESD
900
V
71
G
= Device Code
= Pb−Free Package
(HBM, Method 3015)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
†
Device
2N7002WT1G
Package
Shipping
THERMAL CHARACTERISTICS
SC−70
(Pb−Free)
3000/Tape & Reel
Characteristic
Symbol
Max
Unit
Junction−to−Ambient − Steady State
(Note 1)
R
q
JA
450
°C/W
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Junction−to−Ambient − t ≤ 5 s (Note 1)
R
q
JA
375
1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in
sq [1 oz] including traces)
©
Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
April, 2007 − Rev. 2
2N7002W/D
2N7002W
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
= 0 V, I = 250 mA
60
V
(BR)DSS
GS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/T
(BR)DSS
71
mV/°C
J
Zero Gate Voltage Drain Current
I
T = 25°C
1
mA
mA
nA
DSS
J
V
V
= 0 V,
= 60 V
GS
T = 125°C
J
500
100
DS
V
= 0 V,
T = 25°C
J
GS
V
= 50 V
DS
Gate−to−Source Leakage Current
I
V
= 0 V, V = ±20 V
±10
450
150
mA
nA
nA
GSS
DS
DS
DS
GS
V
= 0 V, V = ±10 V
GS
V
= 0 V, V = ±5.0 V
GS
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
V
V
= V , I = 250 mA
1.0
2.5
V
GS(TH)
GS
DS
D
Negative Threshold Temperature
Coefficient
V
/T
GS(TH)
4.0
mV/°C
J
Drain−to−Source On Resistance
R
V
= 10 V, I = 500 mA
1.19
1.33
80
1.6
2.5
W
DS(on)
GS
D
V
= 4.5 V, I = 200 mA
D
GS
Forward Transconductance
g
FS
V
= 5 V, I = 200 mA
S
DS
D
CHARGES AND CAPACITANCES
Input Capacitance
C
24.5
4.2
2.2
0.7
0.1
0.3
0.1
pF
ISS
V
= 0 V, f = 1 MHz,
GS
Output Capacitance
C
OSS
C
RSS
V
= 20 V
DS
Reverse Transfer Capacitance
Total Gate Charge
Q
nC
ns
V
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Q
G(TH)
V
= 4.5 V, V = 10 V;
DS
GS
I
= 200 mA
D
Q
GS
GD
Q
SWITCHING CHARACTERISTICS, V = V (Note 3)
GS
Turn−On Delay Time
Rise Time
t
12.2
9.0
d(ON)
t
r
V
I
= 10 V, V = 25 V,
DD
GS
= 500 mA, R = 25 W
Turn−Off Delay Time
Fall Time
t
55.8
29
D
G
d(OFF)
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T = 25°C
J
0.8
0.7
1.2
SD
V
= 0 V,
= 200 mA
GS
I
T = 85°C
J
S
2. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%
3. Switching characteristics are independent of operating junction temperatures
http://onsemi.com
2
2N7002W
TYPICAL CHARACTERISTICS
1.6
1.2
0.8
1.2
5.0 V
4.5 V
V
= 10 V
GS
9.0 V
4.0 V
8.0 V
7.0 V
6.0 V
0.8
3.5 V
T = 25°C
J
3.0 V
2.5 V
0.4
0
0.4
0
T = 125°C
T = −55°C
J
J
0
2
4
6
0
2
4
6
V
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
V
, GATE−TO−SOURCE VOLTAGE (V)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
3.2
2.8
2.4
2.0
1.6
1.2
0.8
3.2
2.8
2.4
2.0
1.6
1.2
0.8
V
= 4.5 V
V
= 10 V
GS
GS
T = 125°C
J
T = 125°C
J
T = 85°C
J
T = 85°C
J
T = 25°C
J
T = 25°C
J
T = −55°C
J
T = −55°C
J
0.4
0
0.4
0
0
0.2
0.4
0.6
0.8
1.0
1.2
0
0.2
0.4
0.6
0.8
1.0
1.2
I , DRAIN CURRENT (A)
D
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Drain Current and
Figure 4. On−Resistance vs. Drain Current and
Temperature
Temperature
2.4
2.0
1.6
1.2
2.2
1.8
1.4
I
= 0.2 A
D
I
= 500 mA
D
V
= 4.5 V
GS
V
= 10 V
GS
I
= 200 mA
D
1.0
0.6
0.8
0.4
2
4
6
8
10
−50 −25
0
25
50
75
100
125 150
V
, GATE−TO−SOURCE VOLTAGE (V)
GS
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. On−Resistance vs. Gate−to−Source
Figure 6. On−Resistance Variation with
Voltage
Temperature
http://onsemi.com
3
2N7002W
TYPICAL CHARACTERISTICS
30
5
C
iss
T = 25°C
J
I
= 0.2 A
D
4
3
2
20
10
0
T = 25°C
J
V
= 0 V
GS
C
oss
1
0
C
rss
0
4
8
12
16
20
0
0.2
0.4
0.6
0.8
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
10
V
= 0 V
GS
1
T = 85°C
J
T = 25°C
J
0.1
0.01
0.4
0.6
0.8
1.0
1.2
V
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
Figure 9. Diode Forward Voltage vs. Current
http://onsemi.com
4
2N7002W
PACKAGE DIMENSIONS
SC−70 (SOT−323)
CASE 419−04
ISSUE M
D
NOTES:
e1
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3
MILLIMETERS
INCHES
NOM
0.035
0.002
0.028 REF
0.014
0.007
0.083
0.049
0.051
E
H
E
DIM
MIN
0.80
0.00
NOM
0.90
0.05
MAX
1.00
0.10
MIN
0.032
0.000
MAX
0.040
0.004
1
2
A
A1
A2
b
c
D
0.7 REF
0.35
0.18
2.10
1.24
0.30
0.10
1.80
1.15
1.20
0.40
0.25
2.20
1.35
1.40
0.012
0.004
0.071
0.045
0.047
0.016
0.010
0.087
0.053
0.055
b
e
E
e
1.30
0.65 BSC
0.425 REF
2.10
0.026 BSC
0.017 REF
0.083
e1
L
c
H
2.00
2.40
0.079
0.095
E
A2
A
STYLE 8:
PIN 1. GATE
2. SOURCE
3. DRAIN
0.05 (0.002)
L
A1
SOLDERING FOOTPRINT*
0.65
0.025
0.65
0.025
1.9
0.075
0.9
0.035
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
2N7002W/D
相关型号：
2N7002W-13
Small Signal Field-Effect Transistor, 0.115A I(D), 60V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, ULTRA SMALL, PLASTIC PACKAGE-3
DIODES
2N7002WT3G
310mA, 60V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, LEAD FREE, CASE 419-04, SC-70, 3 PIN
ONSEMI
©2020 ICPDF网 联系我们和版权申明