MSM7502GS-BK [OKI]
暂无描述;
| 型号： | MSM7502GS-BK |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 暂无描述 解码器 编解码器 PC |
| 文件： | 总35页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2U0023-28-81
This version: Aug. 1998
Previous version: Nov. 1996
¡ Semiconductor
MSM7502
Multi-Function PCM CODEC
GENERAL DESCRIPTION
The MSM7502, developed especially for low-power and multi-function applications in touch-
tone telephone sets and digital telephone terminals of digital PBXs, is a single +5 V power supply
CODEC device. The device consists of the analog speech paths directly connectable to a handset,
thecallingcircuitdirectlyconnectabletoapiezosounder, thepush-buttonkeyscanninginterface
betweenpushbuttonsandcontrolprocessors, thedialtonegenerator, them-law/A-lawCODEC,
and the processor interface. The functions can be controlled via 8-bit data bus.
For the CODEC of the MSM7502, an MSM7543 is used as a core CODEC, so the MSM7502
provides the available bit clock range wider than the family product MSM6895.
In addition, the MSM7502 performs the greater key interface function and offers the upgraded
side-tone level, receive level, and speaker pre-amplifier output level.
FEATURES
• Single +5 V Power Supply
• Low Power Dissipation
Power ON Mode
Power Saving Mode
: 30 mW Typ. 53 mW Max.
2 mW Typ. 5 mW Max.
:
• In compliance with ITU-T’s companding law
• Transmission clocks
: 64, 128, 256, 512, 1024, 2048 kHz
96, 192, 384, 768, 1536, 1544 kHz
• Built-in PLL
• Built-in Reference Voltage Supply
• Calling Tone Interval
• Calling Tone Combination
• Calling Tone Volume
: Controlled by processor
: Controlled by processor, 6 modes
: Controlled by processor, 4 modes
: Controlled by processor
• Ringing Tone Interval
• Ringing Tone Frequency
• Ringing Tone Level
: Controlled by processor, 6 modes
: Controlled by processor, 4 levels
• Built-in PB Tone Generator
• Built-in Speech path Control Switches
• General Latch Output for External Control : 2 bits
• Watch-dog Timer
: 500 ms
• Key Scanning I/O
Output
: 8 bits
Input
: 8 bits
: 1.2 kW driving available
• Direct Connection to Handset
• Built-in Pre-amplifier for Loud-speaker
• Hand-free Interface
• m-law/A-law Switchable CODEC
• LCD Deflection Angle Voltage
• Package :
: Controlled by processor, 8 levels
80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM7502GS-BK)
1/35
¡ Semiconductor
MSM7502
BLOCK DIAGRAM
TPAO TPBI MPAI MPAO MPBI MPBO MLDYI
TO CAI
VOL 9
20 dB
+
–
TPAI
+
–
SW 1
SW 2
SW 7
SW 16
0 dB
5.7 dB
VOL 3
VOL 4
AIN
SW 12
m/A
CODEC
PCMOUT
PCMIN
VOL 8
+
CAO
R1I
AOUT
VOL 10
–
PLL
BCLOCK
VOL 1
SW 3
SW 4
XSYNC
RSYNC
VOL 2
PB GEN.
R2I
SW 9
0 dB
–8.7 dB
SW 17
WRN
RDN
CEN
0 dB
SW 14
SW 13
R-TONE GEN.
400
425
RESETN
–
RPO
VOL 7
440
450
D0 to D7
RMI
400*16
400*20
AD0
AD1
RMO0
SW 5
SW 5
INTT
TIMEN
F-TONE GEN.
1 kHz
RMO1
SPI
–
–
0 dB
0 dB
SW 6
S-TONE GEN.
SW 10
VOL 6
–
WAMBLE TONE
1000 Hz
–3 dB
SW 8
800 Hz
400 Hz
–6.8 dB
SW 18
Latch
VOL 5
SW 21
SW 15
LA
LB
LML
–22 dB
–
SPO
VOL 11
VOL 12
SW 11
SW 20
VLCD GEN.
VLCD
SA0
SA1
SW 19
VOL 13
KEY INTF
SG GEN.
SCANNING OUTPUT
SCANNING INPUT
VA VD AG DG
SGT SGC
PO0 to PO7
PI0 to PI7
2/35
¡ Semiconductor
MSM7502
PIN CONFIGURATION (TOP VIEW)
LML 1
LA 2
64 VD
63 PI7
62 PI6
61 PI5
60 PI4
59 PI3
58 PI2
57 PI1
56 PI0
LB 3
VLCD 4
SA1 5
SA0 6
DG 7
AG 8
RMO1 9
NC
55
10
RMO0
RMI 11
SPI 12
54 PO0
53 PO1
52 PO2
51 PO3
50 PO4
49 PO5
48 PO6
47 PO7
46 PCMOUT
NC
13
SPO 14
RPO 15
R2I 16
R1I 17
MLDYI 18
MPBO 19
MPBI 20
MPAO 21
NC 22
45 BCLOCK
44 XSYNC
43 RSYNC
MPAI 23
42 PCMIN
NC
NC
41
24
NC : No connect pin
80-Pin Plastic QFP
3/35
¡ Semiconductor
MSM7502
PIN AND FUNCTIONAL DESCRIPTIONS
LA, LB
General latch outputs for external control.
Statuses of these outputs are controlled via the processor interface. Refer to the description of the
control data for details. These outputs provide the capability to drive one TTL.
DG
Digital Ground.
DG is separated from the analog ground AG inside the device. But, DG should be connected as
close to the AG pin on PCB as possible.
AG
Analog Ground.
SA0, SA1
Sounder (calling tone) driving outputs.
The output signal on SA1 is inverted against the signal on SA0. The sounder circuit can be easily
configuredbyconnectingapiezo-sounderbetweenSA0andSA1.Throughprocessorcontrol,the
calling tone volume is selectable from four levels and one of six tone combinations is selectable.
Initially, the ringing tone volume is set at a maximum and the tone combination is set at a 16 Hz
Wamble tone by a combination of 1 kHz and 1.3 kHz. If these pins are used with no-load, tone
volume cannot be controlled. When tone volume control is required, a load resistor must be
connected between SA0 and SA1.
4/35
¡ Semiconductor
MSM7502
RMI, RMO0, RMO1
Receive main amplifier input and outputs.
RMI is the inverted input and RMO0 and RMO1 are the outputs of the receive main amplifier.
The output signal on RMO1 is inverted against RMO0 by a gain 1 (0 dB), so the earphone of a
handset is directly connected between RMO0 and RMO1. During the system power down, the
RMO0 and RMO1 outputs are in a high impedance state. The receive main amplifier gain is
determined by a resistor connected between RPO and RMI, and a resistor connected between
RMI and RMO0. The receive main amplifier gain varies between 0 and +20 dB in effect. A piezo-
receiver with an impedance greater than 1.2 kW is available.
If the adjusting of receive path frequency characteristics is required, insert the following circuit
for adjustment. During the whole system Power ON, the speech path from RMI to RMO0 and
RMO1 is disconnected and the output of RMO0 and RMO1 is at the SG level (VA/2). The speech
path is provided by processor control.
A circuit example for adjustment of frequency characteristics
RPO
RMI
RMO0
R1
C1
R2
C2
Main amplifier gain without capacitors
R2
R1
G=
5/35
¡ Semiconductor
MSM7502
SPI
Addit0ion input of speaker amplifier.
The typical gain between SPI and SPO is 0 dB. But, the 2-stage gain amplifier allows to set up a
gain between 0 dB and –18 dB in a 6 dB step, or a gain between 0 dB and –28 dB in a 4 dB step
through processor control. The input resistance of SPI is typically 20 kW to 150 kW (it varies by
gain setting).
SPO
Output of pre-amplifier for speaker.
Since the driving capability is 2.4 V for the load of 20 kW, SPO can not directly drive a speaker.
PP
Duringthewholesystempowerdownmode, SPOisatananaloggroundlevel. Duringthewhole
system power on mode, SPO is in a non-signal state (SG level), and a receive voice signal, R-tone,
F-tone, hold acknowledge tone, PB signal acknowledge tone, and sounder tone are output from
the speaker by processor control.
When the speaker is used as a sounder, the sounder tone is output via the SPO pin by connecting
the SPI input with the sounder output (SA0 or SA1). In addition, when the AD-converted
sounder tone is sent from the main device, the sounder tone is output via the SPO pin since the
CAO pin for CODEC output is internally connected.
R1I, R2I, RPO
R1I and R2I are for the inputs and RPO is for the output of the receive pre-amplifier.
Normally, R1I is connected via an AC-coupling capacitor to the CODEC analog output (CAO),
and R2I is used as the mixing signal input pin.
The typical gain between R1I and PRO is –6 dB. Through processor control, gains are variable
from –14 dB to 0 dB in 2 dB steps. In addition, the receive pad can control the gain of –9, –6, –3,
or 0 dB. The gain between R2I and RPO is fixed to 0 dB.
During the whole system power-on mode, the RPO output is in non-signal state, and speech
signal, R-tone, F-tone, PB acknowledge tone, side tone signal are output by processor control.
During the whole system power-down mode, the RPO output is the analog ground level.
The input resistance of R1I is typically between 20 kW and 100 kW (it varies by gain setting). The
input resistance of R2I is typically 20 kW.
MLDYI
Hold tone signal input.
For example, the output of external melody IC is connected to this pin. Through processor
control, the signal applied to MLDYI is output from the TO output pin as a hold tone on the
transmit path, and from the SPO output pin as a hold acknowledge tone on the receive path. The
typical gain between MLDYI and TO is –2 dB. Through processor control, a gain between –2 dB
and –11 dB is also settable at 3 dB steps. The typical gain between MLDYI and SPO is –3 dB.
Through processor control, a gain between –3 dB to –31 dB is also settable at 4 dB steps. MLDYI
is a high impedance input, so insert an about 100 kW bias resistor between MLDYI and SGT.
6/35
¡ Semiconductor
MSM7502
TPBI, TO
TPBI is the input and TO is the output of the transmit pre-amplifier (B).
Whenthehandsetisused,TPBIisconnectedtothetransmitpre-amplifier(A)outputpin(TPAO).
If adjustment of frequency characteristics on the transmit path is required, insert a circuit for
adjustment of characteristic between TPAO and TPBI. Through processor control, the signal
applied to this pin is output via the TO pin on the transmit path and its side tone via the RPO pin.
During the whole system power down mode, TO is at an analog ground level. The typical gain
between TPBI and TO is +17.7 dB. Through processor control, a gain between +17.7 dB and +8.7
dB is also settable at 3 dB steps.
The typical gain between TPBI and RPO is +3.0 dB. Through processor control, a gain between
–9 dB and +9 dB is variable in 3 dB steps. Changing the gain between TPBI and TO may change
the gain between TPBI and RPO. TPBI is a high impedance input, so insert an about 100 kW
resistor between TPBI and SGT.
A circuit example for adjustment of frequency characteristics
TPAO
TPBI
SGT
R3
C3
R4
C4
MPAI, MPAO
Handfree microphone pre-amplifier (A) input and output.
MPAIistheinputandMPAOistheoutput.ThespeechpathbetweenMPAIandMPAOisalways
active regardless of processor control. During the whole system power saving mode, MPAO is
at an analog ground level. The gain between MPAI and MPAO is typically +20 dB. Through
processor control, gains between +14 dB and +11 dB are also settable. MPAI is a high impedance
input, so insert an about 100 kW between MPAI and SGT.
MPBI, MPBO
The handfree microphone (B) input and output.
MPBI is the inverted input and MPBO is the output. With an external resistance, the amplifier
gain is adjusted in the range between –25 dB and +25 dB. A signal on the MPBO is output via the
TO pin through processor control. During the whole system power down mode, MPBO is at an
analog ground level. The gain between MPBO and TO is fixed to 0 dB.
7/35
¡ Semiconductor
MSM7502
TPAI, TPAO
The transmit pre-amplifier input and output.
TPAI is the input and TPAO is the output. TPAI should be connected to the microphone of
handset via an AC-coupling capacitor if the DC offset appears at a transmit signal (offset from
SGT). The transmit path from TPAI to TPAO is always active regardless of processor control.
During the whole system power down mode, TPAO is at an analog ground level. The gain
between TPAI and TPAO is fixed to 20 dB.
SGT
Transmit path signal ground.
SGT outputs half the supply voltage. During the whole power down mode, SGT is in a high
impedance state.
SGC
Bypass capacitor connecting pin for signal ground level.
Insert a 0.1 mF high performance capacitor between SGC and AG.
VA, VD
+5 V power supply.
VA is for an analog circuit and VD is for digital supply. Connect both VA and VD to the +5 V
analog path of the system.
CAI, CAO
CODEC analog input and output.
CAI is the analog input of CODEC to be connected to the TO pin. If the DC offset voltage on the
TO signal is great, CAI should be connected via AC-coupling capacitor. At this time, insert an
about 100 kW bias resistor between CAI and SGT.
CAO is the analog output of CODEC. CAO should be connected to R1I via AC-coupling
capacitor. AbiasresistorisnotrequiredtoR1I. DuringthewholesystemorCODECpowerdown
mode, CAO is at the SG voltage level.
8/35
¡ Semiconductor
MSM7502
BCLOCK
CODEC PCM data I/O shift clock input.
Thefrequencyisoneof64kHz, 128kHz, 256kHz, 512kHz, 1024kHz, 2048kHz, 96kHz, 192kHz,
384 kHz, 786 kHz, 1536 kHz, and 1544 kHz. If the BCLOCK signal is not applied, PLL is out of
synchronization and the CODEC path goes into the power down mode.
XSYNC, RSYNC
Synchronous signal input.
CODEC PCM data is sent out sequencially via the PCMOUT pin from MSB at the rising edge of
the BCLOCK signal in synchronization with the rise of the XSYNC signal. PCM data should be
entered via the PCMIN pin with MSB at the head in synchronization with the rise of the RSYNC
signal. PCM data is shifted in at the falling edge of the BCLOCK signal.
Since the XSYNC signal is used for a trigger signal for PLL and for a clock signal to the tone
generator, if this signal is not applied, not only any tone can not be output, but also PLL goes out
of synchronization and the CODEC path goes into a power down mode. This signal has to be
synchronouswiththeBCLOCKsignalanditsfrequencymustbewithin8kHz±50ppmtoensure
the CODEC AC characteristics (mainly frequency characteristics).
PCMIN
PCM signal input.
PCMIN data is shifted in at the falling edge of the BCLOCK signal and is latched into the internal
register after eight bits are shifted.
PCMOUT
PCM signal output.
PCMOUT data is shifted out at the rising edge of the BCLOCK signal. PCMOUT is left open after
eight bits are shifted or when PLL goes out of synchronization. PCMOUT also is left open
through processor control. In addition, a digital path between PCMIN and PCMOUT is formed
through processor control. PCMOUT needs a pull-up resistor because of its open-drain circuit.
9/35
¡ Semiconductor
MSM7502
PO0, PO1, PO2, PO3, PO4, PO5, PO6, PO7
Key scanning outputs.
Theseoutputpinsneedexternalpull-upresistorsbecauseoftheiropen-draincircuits. But, when
these are used in combination with PI0 to PI7, pull-up resistors are not required. Through
processor control, these outputs can be set open or to digital "0". Initially, these outputs are set
at an opened state.
PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7
Key scanning inputs.
In the READ mode, data on PI0 to PI7 can be read out of the processor via data bus (DB0 to DB7).
Since these inputs are pulled up inside the IC, external resistors are not required.
INTT
Interrupt signal output to the processor.
INTT outputs interrupt signals (digital "0") at intervals of 8 ms by the interrupt release control
signal from the processor. This output keeps digital "0" unless the interrupt is released. INTT
does not output any signal while no XSYNC signal is input. When the RESETN signal is in "0"
state, INTT is in "1" state. INTT goes from "1" state to "0" state 8 ms after the RESETN signal goes
to "1" state.
Interrupt release signal
t < 8 ms
8 ms < t < 16 ms
t < 8 ms
from processor
INTT output
8 ms
16 ms
8 ms
DB0, DB1, DB2, DB3, DB4, DB5, DB6, DB7
Data bus inputs and outputs.
ThesepinsareconfiguredasanoutputduringtheREADmodeonlyandasaninputduringother
modes.
10/35
¡ Semiconductor
MSM7502
AD0, AD1
Address data inputs for the internal control registers.
Addressing of the internal control registers is executed by AD0 and AD1 and sub address data,
DB7 and DB6.
AD1 AD0 DB7 DB6
Function
ON/OFF controls of sounder, R-Tone, F-Tone
Level/Frequency controls of sounder, R-Tone
PB tone control
0
0
1
0
1
0
0
0
Controls of internal speech path switch and general latch
Watchdog timer reset
1
1
0
0
0
1
Controls of receive gain and side tone gain
Controls of transmit hold tone, PB tone, handfree input, handset inputs gain
Controls of speaker pre-amplifier gain and additional speaker gain
Controls of receive PAD and incoming tone input gain
Key scanning output control
WRITE
0
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
—
0
—
0
Key scanning interrupt reset
0
1
LCD deflection angle control voltage setting
Power ON/OFF control
1
0
1
1
CODEC control (Controls of companding law and digital loop)
READ
1
0
—
—
Key scanning data read-out
WRN
Write signal for internal control registers.
Data on the data bus is written into the registers at the rising edge of WRN under the condition
of digital "0" of CEN (Chip Enable). While CEN is in digital "1" state, WRN becomes invalid. The
Write cycle is a minimum of 2 ms regardless of the presence or absence of clock signals.
RDN
Read signal input to read PI0 to PI7 out of the processor.
When CEN and RDN are in digital "0" state, the digital values on PI0 to PI7 are output onto the
data buses DB0 to DB7. While CEN is in digital "1" state, the RDN signal becomes invalid.
11/35
¡ Semiconductor
MSM7502
CEN
Chip Enable signal input.
When CEN is in digital "0" state, WRN and RDN are valid.
RESETN
Reset signal input.
Digital "0" input to RESETN makes all of internal control registers to be initialized. When
powered on, this RESETN signal should be input for initializing the system.
TIMEN
Watchdog timer output.
When the processor does not reset the timer, the 500 ms period (Digital "0" : 4 ms) digital signal
is continuously output. When RESETN is at digital "0", this timer is reset. And, in about 500 ms
after RESETN goes to digital "1", the first timer output signal is issued and then the timer signal
is output at intervals of a 500 ms. If the SYNC signal is not input, the TIMEN signal is not output.
LML
Control signal output for external hold tone generator.
LML goes to digital "1" state when the hold tone transmit mode on transmit path or the hold
acknowledge tone mode on receive path is selected. During initialized state, LML is in digital "0"
state.
VLCD
By processor control, VLCD outputs a DC voltage between 0 and 1.7 V is about 0.25 V step.
This is used to control the deflection angle of the LCD display. VLCD has the internal resistance
value of about 1 kW, so the external load of over 100 kW should be used. During initialized state,
VLCD outputs the voltage of 0 V.
12/35
¡ Semiconductor
MSM7502
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
VDD
Condition
AG, DG = 0 V
AG, DG = 0 V
AG, DG = 0 V
—
Rating
0 to 7
Unit
V
VAIN
-0.3 to VDD + 0.3
-0.3 to VDD + 0.3
-55 to +150
V
VDIN
V
TSTG
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
Input High Voltage
Input Low Voltage
Symbol
Condition
VA, VD (Voltage must be fixed)
—
Min.
4.75
–10
2.2
0
Typ.
5.0
+25
—
Max.
Unit
V
VD
Ta
VIH
VIL
tIr
5.25
+70
VDD
0.8
50
°C
V
All Digital Input Pins
All Digital Input Pins
All Digital Input Pins
All Digital Input Pins
—
V
Digital Input Rise Time
Digital Input Fall Time
—
—
ns
ns
tIf
—
—
50
PO0 to PO7
PCMOUT
10
0.5
—
—
—
—
RDL
CDL
kW
Digital Output Load
PO0 to PO7
PCMOUT
pF
—
—
100
Recommend Operating Conditions (Analog Interface)
Parameter
Symbol
Condition
TPAO, MPAO, MPBO, TO,
RPO, SPO, CAO
Min.
Typ.
Max.
Unit
20
—
—
Analog Load Resistance
RAL
kW
RMO0, RMO1 with respected to
SG Level
0.6
—
—
—
—
TPAO, MPAO, MPBO, TO,
RPO, SPO, CAO
100
pF
nF
Analog Load Capacitance
CAL
RMO0, RMO1
TPAI, TPBI, MPAI
MLDY
—
–10
–50
–25
–100
—
—
—
—
—
70
+10
+50
+25
+100
Allowable Analog
Input Offset Voltage
Voff
mV
R1I, R2I, SPI
CAI
13/35
¡ Semiconductor
MSM7502
Recommended Operating Conditions (CODEC Digital Interface)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
64, 128, 256, 512, 1024,
2048
BCLOCK
Clock Frequency
FC
kHz
96, 192, 384, 768, 1536,
1544
Sync Pulse Frequency
Clock Duty Ratio
FS
XSYNC, RSYNC
BCLOCK
6.0
40
8.0
50
10.0
60
kHz
%
DC
BCLOCKÆX, RSYNC
tXS
tSX
—
—
—
—
100
100
ns
ns
See Fig.1
Sync Pulse Setting Time
X, RSYNCÆBCLOCK
See Fig.1
Sync Pulse Width
Data Setup Time
Data Hold Time
tWS
tDS
tDH
—
XSYNC, RSYNC
PCMIN
1 BCK
100
100
—
—
—
—
—
100
—
ms
ns
ns
ns
PCMIN
—
Allowable Jitter Width
XSYNC, RSYNC
500
Recommended Operating Conditions (Processor Digital Interface)
Parameter
Write Pulse Period
Write Pulse Width
Read Pulse Width
Symbol
PW
Condition
WRN
Min.
2000
100
200
10
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TW
WRN
TR
RDN
tAW1
tAR1
tAW2
tAR2
tCW1
tCR1
tCW2
tCR2
tDW1
tDW2
tWRES
AD0, AD1ÆWRN
AD0, AD1ÆRDN
WRNÆAD0, AD1
RDNÆAD0, AD1
CENÆWRN
Address Data
Setup Time
80
50
Address Data
Hold Time
10
See Fig.2
10
CEN Setup Time
CEN Hold Time
CENÆRDN
80
WRNÆCEN
50
RDNÆCEN
10
Data Setup Time
Data Hold Time
Reset Pulse Width
DB0 to 7ÆWRN
WRNÆDB0 to 7
RESETN
110
20
110
14/35
¡ Semiconductor
MSM7502
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 5 V 5%, Ta = –10°C to +70°C)
Parameter
Symbol
IDD1
Condition
Operating Mode (No Signal, Sounder OFF)
Whole system Power Down
CODEC Power Down
Min.
—
Typ.
6.0
0.4
2.8
—
Max. Unit
10.0
0.8
5.0
VDD
0.8
2.0
2.0
0.5
25
mA
mA
mA
V
Power Supply Current
IDD2
—
IDD3
—
Input High Voltage
Input Low Voltage
VIH
—
2.2
0.0
—
VIL
—
—
V
Digital Pins except for PI0 to PI7
PI0 to PI7 (Internal Pull-up Pins)
Digital Pins except for PI0 to PI7
PI0 to PI7 (Internal Pull-up Pins)
—
mA
mA
mA
mA
High Input Leakage
Current
IIH
IIL
—
—
—
—
Low Input Leakage
Current
10
—
I
OH = 0.4 mA
2.4
3.8
—
VDD
VDD
Digital Output High
Voltage
VOH
V
IOH = 1 mA
—
Digital Output Low
Voltage
VOL
IO
I
OL = –1.6 mA
0.0
—
—
—
0.4
10
V
PCMOUT, DB0 to DB7
(Write Mode)
Digital Output Leakage
Current
mA
Analog Output Offset
Voltage
TPAO, MPAO, MPBO, TO,
CAO, RPO, RMO0, RMO1, SPO
Voff
CIN
–100
—
—
5
+100
—
mV
pF
Input Capacitance
—
TPAI, TPBI, MLDYI, RMI, MPAI,
MPBI
—
10
—
MW
Analog Input Resistance
RIN
R1I, R2I, SPI
10
—
—
1
—
—
kW
CAI (fin : < 4 kHz)
MW
VA/2
–0.05
VA/2
+0.05
SG Voltage
—
—
VA/2
V
ISGF
ISGS
FORCE Current
SINK Current
1.0
0.3
1.5
0.5
—
—
SG Drive Current
mA
Equivalent Pull-up Resistance RPULL
PI0 to PI7, VI = 0 V
200
370
500
kW
15/35
¡ Semiconductor
MSM7502
AC Characteristics 1 (CODEC)
(VDD = 5 V 5%, Ta = –10°C to +70°C)
Freq. Level
(Hz) (dBm0)
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
Loss T1
60
20
–0.20
27
+0.07
Reference
–0.03
+0.06
0.38
–0.03
Reference
–0.02
+0.15
0.56
—
+0.20
Loss T2 300
Loss T3 1020
Loss T4 2020
Loss T5 3000
Loss T6 3400
Loss R1 300
Loss R2 1020
Loss R3 2020
Loss R4 3000
Loss R5 3400
SD T1
Transmit Frequency
Response
0
0
dB
–0.15
–0.15
0.0
+0.20
+0.20
0.80
+0.20
–0.15
Receive Frequency
Response
dB
dB
dB
dB
dB
–0.15
–0.15
0.0
35
+0.20
+0.20
0.80
—
3
43.0
SD T2
0
35
35
29
24
37
37
37
30
41.0
38.0
31.0
26.5
43.0
41.0
40.0
34.0
—
—
—
—
—
—
—
—
Transmit Signal to
Distortion Ratio
SD T3
SD T4
SD T5
SD R1
SD R2
SD R3
SD R4
SD R5
GT T1
GT T2
GT T3
GT T4
GT T5
GT R1
GT R2
GT R3
GT R4
GT R5
1020
1020
1020
1020
–30
–40
–45
3
0
*1
*1
Receive Signal to
Distortion Ratio
–30
–40
–45
3
–10
–40
–50
–55
3
–10
–40
–50
–55
25
–0.2
31.0
—
+0.2
+0.01
Reference
–0.05
+0.05
+0.30
0.0
Reference
–0.10
–0.30
–0.40
Transmit Gain
Tracking
–0.2
–0.4
–1.2
–0.2
+0.2
+0.4
+1.2
+0.2
Receive Gain
Tracking
–0.2
–0.5
–1.2
+0.2
+0.5
+1.2
Note:
*1 Psophometric filter is used
16/35
¡ Semiconductor
MSM7502
AC Characteristics 1 (CODEC) (Continued)
(VDD = 5 V 5%, Ta = –10°C to +70°C)
Freq. Level
(Hz) (dBm0)
Parameter
Symbol
Condition
AIN = SG
Min.
Typ.
Max. Unit
–73.5
–71
–70
Nidle T
Nidle R
—
—
—
—
0
—
—
*2
*1
–69
Idle Channel Noise
dBmOp
*1
*3
–78.0
–75
AV T
AV R
0.5671
0.5671
0.6007
0.6007
0.6363
Vrms
1020
Absolute Amplitude
Absolute Delay Time
0.6363
A to A
BCLOCK = 64 kHz
Td
1020
0
0
—
0.58
0.60
ms
ms
tgd T1
tgd T2
tgd T3
tgd T4
tgd T5
tgd R1
tgd R2
tgd R3
tgd R4
tgd R5
500
600
1000
2600
2800
500
—
—
—
—
—
—
—
—
—
—
0.19
0.12
0.02
0.05
0.08
0.0
0.0
0.0
0.09
0.12
0.75
0.35
0.125
0.125
0.75
Transmit Group Delay
Receive Group Delay
*4
0.75
0.35
600
1000
2600
2800
0.125
0.125
0.75
0
0
*4
ms
CR T
CR R
Transmit Æ Receive
Receive Æ Transmit
70
75
78
86
—
—
dB
dB
1020
Crosstalk Attenuation
Discrimination
4.6 kHz to
72 kHz
DIS
S
–25
0
30
—
—
—
32.0
–37.5
–52
—
0 to 4000 Hz
4.6 kHz to 100 kHz
2fa–fb
Out-of-band Signal
Spurious
300 to
3400
–35 dBmO
–35 dBmO
fa = 470
fb = 320
IMD
–4
Intermodulation Distortion
PSR T
PSR R
Power Supply Noise
Rejection Ratio
0 to 50
kHz
50
mVpp
dB
*5
30
—
Notes: *2 Upper is specified for the m-law, lower of the A-law
*3 PCMIN input : idle CODE
*4 Minimum value of the group delay distortion
*5 The measurement under idle channel noise
17/35
¡ Semiconductor
MSM7502
AC Characteristics 2 (Transmit Path)
(VDD = 5 V 5%, Ta = –10°C to +70°C)
Freq. Level
(Hz) (dBV)
Parameter
Pre-Amp Gain
Symbol
Condition
Min.
Typ.
Max. Unit
GTPA
TPAI-TPAO
18.0
15.7
20.0
17.7
22.0
19.7
dB
dB
TPBI-TO
Set at typical gain
Transmit Path Gain
GTPB1
1020 –24.0
1020 –24.0
RG1TPB
RG2TPB
RG3TPB
For
typical
setting
–3 dB
–6 dB
–9 dB
–5.0
–8.0
–11.0
–3.0
–6.0
–9.0
–1.0
–4.0
–7.0
Transmit Path Gain
Setting (VOL8)
dB
dB
dB
Microphone Pre-Amp
Gain
MPAI-MPAO
Set at typical gain
GMPA
18.0
20.0
22.0
Microphone Pre-Amp
Gain Setting
(VOL9)
For
typical
setting
RG1MPA
RG2MPA
–6 dB
–9 dB
–8.0
–6.0
–9.0
–4.0
–7.0
–11.0
Additional Transmit
Signal Gain
GTMX
1020
—
–4.0
—
MPBO-TO
–2.0
0.0
+2.0
dB
In-Channel PB Signal
Output Level
To per wave
set at typical gain
VPBT1
–19.4
–17.4
–15.4
dBV
GPBT1
GPBT2
GPBT3
For
typical
setting
–3 dB
–6 dB
–9 dB
–5.0
–8.0
–11.0
–3.0
–6.0
–9.0
–1.0
–4.0
–7.0
In-Channel PB Signal
Output Level Setting
(VOL4)
dB
—
—
In-Channel PB Signal
Frequency Deviation
DfPBT
—
—
—
—
–1.0
—
—
+1.0
–30
%
In-Channel PB Signal
Distortion
THDPBT
In-band Distortion
–35
dB
MLDYI-TO
Set at typical gain
Hold Tone Path Gain
GPAT
–4.0
–2.0
0.0
dB
dB
1020
–4.0
RG1PAT
RG2PAT
RG3PAT
For
typical
setting
–3 dB
–6 dB
–9 dB
–5.0
–8.0
–11.0
–3.0
–6.0
–9.0
–1.0
–4.0
–7.0
Hold Tone Path Gain
Setting
(VOL3)
TPAI:Terminated in 510 W
Measured at TO
TPAO-TPBI Directly
connected Set at
typical gain *6
Idle Channel Noise
NiTPA
—
—
—
—
–75
—
—
—
dBV
VPP
TPAO, TO,
MPAO, MPBO
RL = 20 kW
Maximum Output Voltage
Swing
VOT
1020
2.4
Note:
*6 Noise band width: 0.3 kHz to 3.4 kHz, non-weighted
18/35
¡ Semiconductor
MSM7502
AC Characteristics 3 (Receive Main Amp.)
(VDD = 5 V 5%, Ta = –10°C to +70°C)
Freq. Level
(Hz) (dBV)
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
Receive Main Amp
Output Gain Difference
RMO0/RMO1
Gain = 1
DGRMO 1020
DPRMO 1020
–4.4
–4.4
—
—
–0.10
—
—
dB
Receive Main Amp
Output Phase Difference
RMO0/RMO1
–179.6
deg
1.2 kW between
RMO0 and RMO1.
Measured at each output
VRMO
1020
—
3.6
—
—
VPP
Maximum Amplitude
AC Characteristics 3 (Receive Path)
(VDD = 5 V 5%, Ta = –10°C to +70°C)
Freq. Level
(Hz) (dBV)
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
Typical gain is set
between R1I and RPO
GRPA
Receive Signal Path Gain
–8.0
–6.0
–4.0
dB
RGRPA1
RGRPA2
RGRPA3
RGRPA4
RGRPA5
RGRPA6
RGRPA7
RGPAD1
RGPAD2
RGPAD3
–8 dB
–6 dB
–4 dB
–2 dB
2 dB
4 dB
6 dB
–3 dB
–6 dB
–9 dB
–10.0
–8.0
–6.0
–4.0
0.0
2.0
4.0
–5.0
–8.0
–11.0
–8.0
–6.0
–4.0
–2.0
2.0
4.0
6.0
–3.0
–6.0
–9.0
–6.0
–4.0
–2.0
0.0
4.0
6.0
For
typical
setting
Receive Signal
Path Gain Setting
(VOL1)
dB
1020
1020
–4.0
–4.0
8.0
For
typical
setting
–1.0
–4.0
–7.0
Receive PAD
Gain Setting
(VOL10)
dB
Additional Receive
Signal Path Gain
GRMX
GSIDE
R2I and RPO
–2.0
1.0
0.0
3.0
+2.0
5.0
dB
dB
Typical gain is set
betweenTPBI and RPO
Side Tone Path Gain
RGSIDE1
RGSIDE2
RGSIDE3
RGSIDE4
RGSIDE5
RGSIDE6
6 dB
3 dB
–3 dB
–6 dB
4.0
1.0
–5.0
–8.0
–11.0
–14.0
6.0
3.0
–3.0
–6.0
–9.0
–12.0
8.0
5.0
–1.0
–4.0
–7.0
–10.0
For
typical
setting
Side Tone Path Gain
Setting
(VOL2)
1020 –14.0
dB
dB
–9 dB
–12 dB
Typical gain is set
between RPO and SPO
Speaker Pre-Amp
Gain
GSP
–2.0
0.0
+2.0
RGSP1
RGSP2
RGSP3
RGSP4
RGSP5
RGSP6
RGSP7
–4 dB
–8 dB
–6.0
–4.0
–8.0
–2.0
–6.0
–10.0
–14.0
–18.0
–22.0
–26.0
–30.0
For
typical
setting
–12 dB
–16 dB
–20 dB
–24 dB
–28 dB
–12.0
–16.0
–20.0
–24.0
–28.0
–10.0
–14.0
–18.0
–22.0
–26.0
Speaker Pre-Amp
Gain Setting
(VOL5)
1020
1020
–4.0
–4.0
dB
Additional Speaker
Input Path Gain
Typical gain is set
between SPI and SPO
GSPI
–2.0
0.0
+2.0
dB
19/35
¡ Semiconductor
MSM7502
AC Characteristics 3 (Receive Path) (Continued)
(VDD = 5 V 5%, Ta = –10°C to +70°C)
Freq. Level
(Hz) (dBV)
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
RGSPI1
RGSPI2
RGSPI3
Setting,
than
typical gain –18 dB
Typical gain is set
between MLDYI and SPO
–6 dB
–12 dB
–8.0
–14.0
–20.0
–6.0
–12.0
–18.0
–4.0
–10.0
–16.0
Additional Speaker
Input Path Gain Setting
(VOL6)
Hold Acknowledge Tone
Path Gain
1020
1020
–4.0
–4.0
dB
GPAR
VPBRP
VPBSP
–5.0
–32.1
–30.2
–3.0
–30.1
–28.2
–1.0
–28.1
–26.2
dB
RPO per wave
dBV
dBV
PB Acknowledge Tone
Output Level
—
—
SPO per wave
Set at typical gain
PB Acknowledge Tone
Frequency Difference
DfPBR
THDPBR
GCAO
—
—
—
—
RPO, SPO
RPO, SPO
–1.0
—
—
–35
0.0
+1.0
–30
%
dB
dB
PB Acknowledge Tone
Distortion
Incoming Tone Speaker
Output Path Gain
Typical gain is set
between CAO and SPO
–2.0
+2.0
1020
–20
Incoming Tone Speaker
Output Path Gain
Setting (VOL11)
Setting,
than
typical gain
RGCAO1
RGCAO2
–10 dB
–20 dB
–12.0
–22.0
–10.0
–20.0
–8.0
dB
–18.0
R1I:SG,
Measured at RPO
Set at typical gain. *6
NiRPO
NiSPO
—
—
—
—
—
—
–86.0
–89.0
—
—
dBV
dBV
R1I:SG,
Measured at SPO
Set at typical gain. *6
Idle Channel Noise
R1I:SG, Gain
0 dB
RMO0, RMOB *6
NiRMO
VOR
—
—
—
—
—
–86.0
—
—
—
dBV
VPP
RPO, SPO
RL = 20 kW
Maximum Output Amplitude
2.4
Note: *6. Noise band width : 0.3 kHz to 3.4 kHz, non weighted
AC Characteristics 4 (Ringing Tone)
(VDD = 5 V 5%, Ta = –10°C to +70°C)
Parameter
R-Tone Output
Symbol
Condition
Level Setting 1
Min.
63
84
105
126
112
Typ.
90
120
150
180
Max. Unit
117
156
195
Level Setting 2
Level Setting 3
Level Setting 4
VRTO
RPO
SPO
mVPP
Amplitude (VOL7)
234
VFTRP
VFTSP
RPO
SPO
160
208
mVPP
14.5
F-Tone Output Amplitude
7.5
154
49
11.0
220
70
0 dB
–10 dB
–20 dB
286
Gain
Setting
S-Tone Output
Amplitude (VOL12)
VSTSP
91
22
mVPP
12
17
20/35
¡ Semiconductor
MSM7502
AC Characteristics 4 (Sounder Output Circuit)
(VDD = 5 V 5%, Ta = –10°C to +70°C)
Freq. Level
(Hz) (dBV)
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
VST1
VST2
VST3
VST4
730 W between Vol.1
SA0 and SA1. Vol.2
3.25
0.73
0.25
0.13
4.0
—
1.98
0.65
0.45
1.28
0.47
0.28
Sounder Tone Output
Amplitude (VOL13)
—
—
Vpp
Measured at
each out
Vol.3
Vol.4
LCD Defelection Angle Control Voltage Output
(VDD = 5 V 5%, Ta = –10°C to +70°C)
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
DB2 DB1 DB0
1.40
1.25
1.05
0.85
0.65
0.35
0.15
0.0
1.70
1.50
1.30
1.10
0.85
0.55
0.30
0.0
2.00
1.75
1.55
1.35
1.05
0.75
0.45
0.05
—
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
—
1
0
1
0
1
0
1
0
Output Voltage
VLCD
V
Output Resistance
Output Load
ROLCD
RLLCD
—
1.0
kW
kW
To GND
100
—
—
Digital Interface Characteristics
(VDD = 5 V 5%, Ta = –10°C to +70°C)
Parameter
Symbol
Condition
WRÆLA, LB
Min.
Typ.
Max. Unit
Digital Output (Latch)
Delay Time
tPDLA
0.2
—
1.5
1.5
ms
ms
ns
ns
WRÆPO0 to PO7
Pull-up resistance : 10 kW
Key Scanning Output
Delay Time
Digital Output (Data)
Delay Time
tPDSCN
tPDDATA
tPDCOD
0.2
20
20
—
52
50
RDÆDB0 to DB7
150
100
BCLOCKÆPCMOUT
Pull-up resistance : 500 W
CODEC Data Output
Delay Time
21/35
¡ Semiconductor
MSM7502
TIMING DIAGRAM
CODEC Timing
BCLOCK
2
3
4
5
6
7
8
9
1
tSX
tXS
XSYNC
tWS
tPDCOD
PCMOUT
MSB
B2
B3
B4
B5
B6
B7
B8
CODEC Transmit Timing
BCLOCK
RSYNC
1
2
3
4
5
6
7
8
9
tSX
tXS
tDS tDH
tWS
MSB
B2
B3
B4
B5
B6
B7
B8
PCMIN
CODEC Receive Timing
Figure 1
Processor Interface Timing
AD0, AD1
tAW1
tAW2
tAR1
tAR2
CEN
tCW1
tCW2
tCR1
tCR2
WRN
TR
TW
tDW1 tDW2
RDN
tPDDATA
tPDDATA
DB0 to DB7
PO0 to PO7
tPDSCN
tPDLA
Latch Output
Figure 2
22/35
FUNCTIONAL DESCRIPTION
Control Data Description
Sounder and tone ON/OFF control
WRITE Mode
Address Data AD1 = 0, AD0 = 0
Control Data
Description for Control
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
Sounder output ON
Sounder output OFF
Sounder output ON
Sounder output OFF
SW19 ON
SW19 OFF
SW20 ON
SW20 OFF
SW13 ON
Tone Output: SA0, SA1
Tone Output: SPO *1
0
R-Tone
R-Tone
F-Tone
F-Tone
F-Tone
F-Tone
ON
0
0
0
0
OFF
SW13 OFF
SW14 ON,
Tone Output: RPO
Tone Output: SPO
ON(1 kHz)
OFF
SW15 OFF,
0
1
SW14 OFF, SW15 OFF,
SW14 OFF, SW15 ON,
SW14 OFF, SW15 OFF,
ON(1 kHz)
OFF
*1: This Sounder Output is sent at the timing shown below.
ON
OFF
ON
OFF
0.625 s
2 s
0.25 s 0.125 s
Level and frequency control of sounder and R-tone
WRITE Mode
Address Data AD1 = 0, AD0 = 0
Control Data
Description for Control
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
1
0
1
0
1
SA0, SA1 outputs sounder volume 1 (Large)
SA0, SA1 outputs sounder volume 2 (Middle)
SA0, SA1 outputs sounder volume 3 (Small 1)
SA0, SA1 outputs sounder volume 4 (Small 2)
Sounder combination tone 1 (16 Hz wamble tone with 1000 Hz/1333 Hz)
Sounder combination tone 2 (16 Hz wamble tone with 667 Hz/800 Hz)
Sounder combination tone 3 (8 Hz wamble tone with 800 Hz/1000 Hz)
Sounder combination tone 4 (Single tone of 1000 Hz)
Sounder combination tone 5 (Single tone of 800 Hz)
Sounder combination tone 6 (Single tone of 400 Hz)
R-Tone output level 1 (90 mVPP at RPO output)
R-Tone output level 2 (120 mVPP at RPO output)
R-Tone output level 3 (150 mVPP at RPO output)
R-Tone output level 4 (180 mVPP at RPO output)
R-Tone 400 Hz single tone
Sounder volume and tone
are defind at a time.
—
—
—
At the initial setting, sounder
volume 1 and sounder
combination tone 1 are set.
SA0, SA1 sounder volume:
VOL 13
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
0
—
0
1
0
0
1
1
0
1
0
1
R-Tone output level = VOL 7
—
R-Tone output level and
frequency are defined at a
time.
At the initial setting, output
level 1 and a single 400 Hz
tone are set.
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
R-Tone 425 Hz single tone
R-Tone 440 Hz single tone
—
R-Tone 450 Hz single tone
R-Tone 400 Hz ON/OFF by 16 Hz
R-Tone 400 Hz ON/OFF by 20 Hz
PB tone control
WRITE Mode
Address Data AD1 = 0, AD0 = 0
Control Data
Output PB Frequency
Low High
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
1
2
3
A
4
5
6
B
7
8
9
C
*
0
#
D
697 Hz 1209 Hz
697 Hz 1336 Hz
697 Hz 1477 Hz
697 Hz 1633 Hz
770 Hz 1209 Hz
770 Hz 1336 Hz
770 Hz 1477 Hz
770 Hz 1633 Hz
852 Hz 1209 Hz
852 Hz 1336 Hz
852 Hz 1477 Hz
852 Hz 1633 Hz
941 Hz 1209 Hz
941 Hz 1336 Hz
941 Hz 1477 Hz
941 Hz 1633 Hz
When PBTC = 0
SW16: ON
SW17: ON
SW18: OFF
PB tone is sent to the transmit path T0 and the receive path RPO.
When PBTC = 1
SW16: OFF
SW17: OFF
SW18: ON
1
PBTC
1
0
PB tone is sent to the receive path SPO only.
0
0
PB tone stop
SW16, SW17, SW18: OFF
SW control and timer reset
WRITE Mode
Address Data AD1 = 0, AD0 = 0
Control Data
Description for Control
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
1
1
0
1
SW1
SW2
SW3
ON
ON
ON
Transmit handfree input
Transmit handset input
Receive input
When hold tone or PB tone transmit is
selected, these inputs are muted.
—
When Handfree input is selected, side
tone is muted.
0
1
0
1
SW4
ON
Side tone input
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
SW5
SW6
SW7
SW8
SW9
ON
ON
ON
ON
ON
Receive main amplifier input
Receive speaker input
—
1
0
Transmit path hold tone input
Receive path hold tone Acknowledge input
Additional receive input
Additional speaker input
Speaker DEC input
When either of SW7 or SW8 is set to ON,
external terminal LML goes to "1".
1
1
—
SW10 ON
SW11 ON
SW12 ON
LA = 1
Speaker DEC input = CODEC AOUT
—
PCM output enable
General Latch output for external control
LB = 1
0
0
1
0
0
1
Above codes
Above corresponding SW or latch is set to OFF or "0".
All of above SWs or latches are set to OFF or "0" at the initial setting stage.
Watchdog timer is reset.
0
0
0
0
0
0
0
0
1
1
Gain setting (receive gain, side tone gain)
WRITE Mode
Address Data AD1 = 0, AD0 = 1
Control Data
Description for Control
Typical receive gain (–6dB)
Remarks
Receive gain = VOL1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
–8 dB than the typical gain
–6 dB than the typical gain
–4 dB than the typical gain
–2 dB than the typical gain
+2 dB than the typical gain
+4 dB than the typical gain
+6 dB than the typical gain
Side tone gain = VOL2
Receive gain and side tone gain are set at a time.
At the initial setting, the typical gain is set.
—
—
—
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Typical side tone gain (–9 dB)
–12 dB than the typical gain
–9 dB than the typical gain
–6 dB than the typical gain
–3 dB than the typical gain
+3 dB than the typical gain
+6 dB than the typical gain
Side tone OFF (VOL2 max loss)
—
Gain control (transmit hold tone, PB tone, microphone input, handset input)
WRITE Mode
Address Data AD1 = 0, AD0 = 1
Control Data
Description for Control
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
1
0
1
0
1
Typical transmit hold tone gain (–2 dB)
–3 dB with respect to the typical gain
–6 dB with respect to the typical gain
–9 dB with respect to the typical gain
Typical transmit PB tone gain (+4 dB)
–3 dB with respect to the typical gain
–6 dB with respect to the typical gain
–9 dB with respect to the typical gain
Typical handfree input gain (+20 dB)
–6 dB with respect to the typical gain
–9 dB with respect to the typical gain
—
Transmit hold tone gain = VOL3
Transmit PB tone gain = VOL4
—
—
Hold tone gain and PB tone
gain are set at a time.
0
0
0
1
1
0
1
0
1
At the initial setting, the typical gain is set.
—
0
1
0
0
0
1
1
0
1
0
1
Handfree input gain = VOL9
Handset input gain = VOL8
—
—
Handfree input gain and handset Input
gain are set at a time.
1
0
0
1
1
0
1
0
1
Typical handset input gain (+12 dB)
–3 dB with respect to the typical gain
–6 dB with respect to the typical gain
–9 dB with respect to the typical gain
At the initial setting, the typical gain is set.
—
Gain control (receive PAD, speaker)
WRITE Mode
Address Data AD1 = 0, AD0 = 1
Control Data
Description for Control
Typical speaker amp. gain (0 dB)
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Speaker amp. gain = VOL5
Additional speaker gain = VOL6
-4 dB with respect to the typical gain
-8 dB with respect to the typical gain
-12 dB with respect to the typical gain
-16 dB with respect to the typical gain
Speaker amp. gain and additional
speaker gain are set at a time.
—
—
1
-20 dB with respect to the typical gain At the initial setting, SW21-OFF and the
1
0
typical gain are set.
-24 dB with respect to the typical gain
-28 dB with respect to the typical gain
0
0
1
1
0
1
0
1
Typical additional speaker input path gain (0 dB)
-6 dB with respect to the typical gain
-12 dB with respect to the typical gain
-18 dB with respect to the typical gain
—
0
1
0
1
0
1
Speaker receive OFF(SW21 OFF)
0
0
0
0
0
0
Speaker receive ON (SW21 ON)
Typical receive PAD gain (0 dB)
0
0
1
1
Receive PAD = VOL10
-3 dB with respect to the typical gain
Incoming tone gain = VOL11, VOL12
—
-6 dB with respect to the typical gain
-9 dB with respect to the typical gain
Receive PAD and incoming tone gain are
set at a time.
1
1
0
0
0
1
0
1
0
Typical incoming tone gain (0 dB)
At the initial setting, the typical gain is set.
—
-10 dB with respect to the typical gain
-20 dB with respect to the typical gain
Key scanning signal output control
WRITE Mode
Address Data AD1 = 1, AD0 = 0
Controlo Data
Description for Control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
The data set on DB7 to DB0 are output on PO7 to PO0 respectively.
Output data is held until next data is written.
When the set data is set to "0", output data goes to "0", when set to "1", output pin becomes open.
At the initial setting, PO7 to PO0 are in open state.
Output Data
Key scanning data read out
Read Mode
Address Data AD1 = 1, AD0 = 0
Contorol Data
Description for Control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0
Data input onto PI7 to PI0 are output onto DB7 to DB0.
Key scanning interrupt reset
WRITE Mode
Address Data AD1 = 1, AD0 = 1
Control Data
Description for Control
INTT output is reset (Output = 1)
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
Valid during write mode only
Special functions
WRITE Mode
Address Data AD1 = 1, AD0 = 1
Contorol Data
Description for Control
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LCD Deflection Angle Control Voltage Output
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VLCD pin output voltage: 0.0 V
: 0.30 V
: 0.55 V
: 0.85 V
: 1.1 V
: 1.3 V
: 1.5 V
: 1.7 V
0
1
0
0
0
At the initial setting stage,
set to 0 V.
Power Down Mode Control
0
0
1
1
0
1
0
1
Whole system power down mode
Whole system power ON mode
CODEC power down mode
CODEC power ON mode
At the initial setting stage, set to
whole system power down mode.
CODEC power ON/OFF control is
valid in the whole system power
ON mode.
1
0
0
0
0
0
CODEC Control
At the initial setting stage, set to
m-law, and PCMIN and PCMOUT
are normally connected.
The componding law and the
connection control are set at a
time.
0
1
CODEC operates in m-law
—
CODEC operates in A-law
1
1
0
0
0
0
0
1
PCMIN and PCMOUT are normally connected
PCMOUT is connected to PCMIN
—
*2: Even during the whole system power down mode, following functions are available, if XSYNC is input. :
Key scanning data I/O, sounder outputs (SA0, SA1), WDT, INTT, and general latch output (LA, LB)
*1
+5 V
100 kW
0.1
100 kW
m
F
0.1 mF
MPAI
TPAO
TPBI MPAO MPBI
MPBO
TO
CAI
MLDYI
LML
Hold Tone
Generator
+5 V
SGT
100 kW
TPAI
CAO
PCMOUT
PCMIN
BCLOCK
XSYNC
RSYNC
Line
Line
Interface
R1I
RPO
RMI
WRN
RDN
*2
RMO0
CEN
RESETN
RMO1
SPO
SPI
Controller
DB0 to DB7
AD0
AD1
INTT
TIMEN
SAO
PO0 PO1 PO2 PO3 PO4 PO5 PO6 PO7
0-20 W
+5 V
0 V
+
10 mF
*1
*2
Inserting a capacitor (1 mF to 22 mF)
between SGT and AG will improve
the transmit path noise
0.1 mF
0.1 mF to 1 mF
characteristic.
Insert a resistor if necessary.
MLDYI
TPAO TPBI MPAI
VOL 9
TO CAI
MPAO MPBI
MPBO
TPAI
CAO
AIN
+
–
–
–
SW1
SW2
SW7
SW16
0 dB
5.7 dB
VOL 3
VOL 4
20 dB
20 dB to +25 dB
+
CODEC
AOUT
+
VOL 8
PB GEN.
Per Wave
0.24 VPP(–21.4 dBV Equivalent)
R1I
R2I
–
VOL 10
CODEC I/O Level
Overload Point: 1.2 Vop
SW9
SW3
0 dB
RPO
RMI
R-Tone GEN.
90 mVPP Pulse (–27.8 dBV Equivalent)
0 dBmO
: 0.6007 Vrms
(–4.4 dBV)
VOL 1
VOL 2
VOL 7
–
F-Tone GEN.
0.16 VPP Pulse (–22.8 dBV Equivalent)
SW4
SW5
–
S-Tone GEN.
0.22 VPP Pulse (–20.0 dBV Equivalent)
SW13
SW17
SW14
SW5
RMO0
RMO1
–
8.7 dB
0 dB
VOL No. Typical Level Variable Range Step Width
0 dB
–6 dB
–9 dB
–2 dB
+4 dB
0 dB
–14 dB to 0 dB
–21 dB to –3 dB
–11 dB to –2 dB
–5 dB to +4 dB
–28 dB to 0 dB
2 dB
3 dB
3 dB
3 dB
4 dB
VOL 1
VOL 2
VOL 3
VOL 4
VOL 5
VOL 6
VOL 7
VOL 8
VOL 9
VOL 10
–
0 dB
SW6
SW8
–
3 dB
6.8 dB
VOL 6
SPO
–
VOL 5
VOL 12
VOL 11
SW21
SW20
SW11
SW15
–
6 dB
30 mV
3 dB
3,6 dB
3 dB
0 dB
0 dB
+12 dB
+20 dB
0 dB
–18 dB to 0 dB
90 mV to 180 mV
+3 dB to +12 dB
+11 dB to +20 dB
–9 dB to 0 dB
–
SW18
SW10
–
22 dB
–20 dB to 0 dB
–20 dB to 0 dB
VOL 11
VOL 12
0 dB
0 dB
10 dB
10 dB
SPI
¡ Semiconductor
MSM7502
RECOMMENDATIONS FOR ACTUAL DESIGN
• To assure proper electrical characteristics, use bypass capacitors with excellent high frequency
characteristics for the power supply and keep them as close as possible to the VA and AG pins.
• Connect the AG pin and the DG pin each other as close as possible. Connect to the system
ground with low impedance.
• Connect the VA pin and the VD pin as close together as possible and route them to the analog
5 V power supply.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an
IC socket is unavoidable, use the short lead type socket.
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave
source such as power supply transformers surround the device.
• Keep the voltage on the V pin not lower than –0.3 V even instantaneously to avoid latch-up
DD
phenomenon when turning the power on.
• Usealownoise(particularly,lowleveltypeofhighfrequencyspikenoiseorpulsenoise)power
supplytoavoiderroneousoperationandthedegradationofthecharacteristicsofthesedevices.
• Connect analog input pins and digital input pins that are not used to the SG pin and to GND,
respectively.
• When the data is written differently from the data defined in the section, Control Data
Description in FUNCTIONAL DESCRIPTION, normal device operation is not guaranteed.
34/35
¡ Semiconductor
MSM7502
PACKAGE DIMENSIONS
(Unit : mm)
QFP80-P-1420-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Epoxy resin
42 alloy
Solder plating
5 mm or more
Solder plate thickness
Package weight (g)
1.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
35/35
相关型号：
©2020 ICPDF网 联系我们和版权申明