MSM7503 [OKI]
Multi-Function PCM CODEC; 多功能的PCM编解码器
| 型号： | MSM7503 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Multi-Function PCM CODEC |
| 文件： | 总41页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2U0024-16-X2
This version: Jan. 1998
Previous version: Nov. 1996
¡ Semiconductor
MSM7503
Multi-Function PCM CODEC
GENERAL DESCRIPTION
The MSM7503 is a high performance, low power CODEC LSI device integrating a 2-wire time
division transmission (ping-pong transmission) interface function and has a basic function of
man-machine interface to that of the MSM7502.
The MSM7503 operates from single 5 V power supply and is ideal for digital telephone terminals
such as pushbutton telephone sets and digital PBXs.
The MSM7503 ping-pong transmission interface supports a bidirectional communication of up
to 800 m long on the 2-wire twisted pair line, and can send and receive voice data at 64 kbps and
control data at 16 kbps.
The man-machine interface consists of analog speech path, key-scanner, tone generators,
CODEC meeting the m/A companding law, and processor interface, which are controlled via 8-
bit data buses.
FEATURES
• Single +5 V Power Supply
• Low Power Dissipation
Power ON Mode
Power Down Mode
: 50 mW Typ. 100 mW Max.
: 15 mW Typ. 30 mW Max.
• Pin-Pong Transmission
: Burst of 8 kHz, Transmission of 256 kbps,
AMI coding, 2-wire time division transmission
: Transmit Start bit (1 bit), K-bit (1 bit),
Control bit (2 bits), Voice bit (8 bits),
DCbalancebit(1bit), totalling13bits
Receive Sync bit (4 bits), K-bit (1 bit),
Control bit (2 bits), Voice bit (8 bits),
DCbalancebit(1bit), totalling16bits
• Transmission data configuration
• Control Data Interface supports synchronous and asynchronous communications
• Built-in Power-on Reset by the power supply voltage monitoring
• Output of the ping-pong transmission monitoring signal
• CODEC complied by the ITU-T companding law
• Calling Tone Interval
: Controlled by processor
• Calling Tone Combination
• Calling Tone Volume
• Ringing Tone Interval
: Controlled by processor, 6 modes
: Controlled by processor, 4 modes
: Controlled by processor
• Ringing Tone Frequency
• Ringing Tone Level
: Controlled by processor, 6 modes
: Controlled by processor, 4 levels
• Built-in PB Tone Generator
• Built-in Speech path Control Switches
• General Latch Output for External Control : 2 bits
• Watch-dog Timer : 500 ms
1/41
¡ Semiconductor
MSM7503
• Scanning I/O
Output
: 8 bits
Input
: 8 bits
• Direct Connection to Handset
• Built-in Pre-amplifier for Loud-speaker
• Hand-free Interface
• m-law/A-law Switchable CODEC
• LCD Deflection Angle Voltage
• Package:
: 1.2 kW driving available
: Controlled by processor, 8 levels
80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM7503GS-BK)
2/41
¡ Semiconductor
MSM7503
BLOCK DIAGRAM
Communication Suppervisor
I/O CLK
PS
SYNC
CLK1
CLK2
CLK3
CLC
R1N
R2N
Start bit
Detector
Start-Stop
Sampling
R • Mix
FHW
FD
FK
BHW
BD
Transmit Polarity Definition
T • Counter
T1N
T2N
BDS
CTEST
T • Mix
XOUT
X1
X2
Crystal Oscillator
TEST
Reset
1024 kHz
LRSTN
Voltage Detect
WDT Output
TO
MPAO
MPAI
TPAO
TPAI
VOL9
20 dB
+
AIN
CAI
PCMOUT
SW12
+
MPBO
SW1
SW2
SW7
SW16
0 dB
5.7 dB
VOL3
VOL4
m/A
MPBI
TPBI
-
CODEC
VOL8
+
MLDYI
CAO
AOUT
DIV
VOL10
PCMIN
R1I
-
VOL1
SW3
SW4
SW17
SW14
SW13
64 kHz
VOL2
-8.7 dB
0 dB
R2I
SW9
0 dB
8 kHz
WRN
RDN
CEN
PB GEN.
R Tone GEN.
400
RPO
-
VOL7
RMI
RMO0
425
440
SW5
-
SW5
450
Processor
INTF
400 ¥ 16
DB0
to
DB7
RMO1
SPI
-
400 ¥ 20
0 dB
SW10
VOL6
0 dB
-3 dB
-6.8 dB
SW6
SW8
SW18
F Tone GEN.
1 kHz
-
AD0
AD1
S Tone GEN.
Latch
VOL5
0 dB
VOL11
VOL12
SW21
SW15
SW11
SW20
LA
LB
-
SPO
SA0
VLCD GEN.
VLCD
Man-machine INTF
VOL13
SW19
Scanning Output
Scanning Input
SG GEN.
VA VD AG DG
SGT SGC
PO0~PO7
PI0~PI7
3/41
¡ Semiconductor
MSM7503
PIN CONFIGURATION (TOP VIEW)
CLK2 1
CLK1 2
SYNC 3
FHW 4
BHW 5
CTEST 6
LRSTN 7
LB 8
64 CEN
63 RDN
62 WRN
61 AD1
60 AD0
59 DB7
58 DB6
57 DB5
56 DB4
LA 9
SAO 10
VLCD 11
DG 12
55
DB3
54 DB2
53 DB1
52 DB0
51 PI7
50 PI6
49 PI5
48 PI4
47 PI3
46 PI2
45 PI1
44 PI0
AG 13
RMO1 14
RMO0 15
RMI 16
SPI 17
SPO 18
RPO 19
R2I 20
R1I 21
PO0
MLDYI 22
MPBO 23
43
42 PO1
41
24
MPBI
PO2
80-Pin Plastic QFP
4/41
¡ Semiconductor
MSM7503
PIN AND FUNCTIONAL DESCRIPTIONS
LA, LB
General latch outputs for external control.
Statuses of these outputs are controlled via the processor interface. Refer to the description of the
control data for details. These outputs provide the capability to drive one TTL.
DG
Digital Ground.
DG is separated from the analog ground AG inside the device. But, DG should be connected as
close to the AG pin on PCB as possible.
AG
Analog Ground.
SA0
Sounder (calling tone) driving outputs.
Through processor control, the calling tone volume is selectable from 4 levels and one of six tone
combinations is selectable. Initially, the calling tone volume is set at a maximum and the tone
combination is set at a 16 Hz Wamble tone by a combination of 1 kHz and 1.3 kHz.
The SA0 outputs pulse waveforms using DG as a reference potential.
5/41
¡ Semiconductor
MSM7503
RMI, RMO0, RMO1
Receive main amplifier input and outputs.
RMI is the inverted input and RMO0 and RMO1 are the outputs of the receive main amplifier.
The output signal on RMO1 is inverted against RMO0 by a gain 1 (0 dB), so the earphone of a
handset is directly connected between RMO0 and RMO1. During the system power down, the
RMO0 and RMO1 outputs are in a high impedance state. The receive main amplifier gain is
determined by a resistor connected between RPO and RMI, and a resistor connected between
RMI and RMO0. The receive main amplifier gain varies between 0 and +20 dB in effect. A piezo-
receiver with an impedance greater than 1.2 kW is available.
If the adjusting of receive path frequency characteristics is required, insert the following circuit
for adjustment. During the whole system Power ON, the speech path from RMI to RMO0 and
RMO1 is disconnected and the output of RMO0 and RMO1 is at the SG level (VA/2). The speech
path is provided by processor control.
A circuit example for adjustment of frequency characteristics
RPO
RMI
RMO0
R1
C1
R2
C2
Main amplifier gain without capacitors
R2
R1
G=
SPI
Addition input of speaker amplifier.
The typical gain between SPI and SPO is 0 dB. But, the 2-stage gain amplifier allows to set up a
gain between 0 dB and –18 dB in a 6 dB step, or a gain between 0 dB and –28 dB in a 4 dB step
through processor control. The input resistance of SPI is typically 20 kW to 150 kW (it varies by
gain setting).
6/41
¡ Semiconductor
MSM7503
SPO
Output of pre-amplifier for speaker.
Since the driving capability is 2.4 V for the load of 20 kW, SPO can not directly drive a speaker.
PP
Duringthewholesystempowerdownmode, SPOisatananaloggroundlevel. Duringthewhole
system power on mode, SPO is in a non-signal state (SG level), and a receive voice signal, R-tone,
F-tone, hold acknowledge tone, PB signal acknowledge tone, and sounder tone are output from
the speaker by processor control.
When the speaker is used as a sounder, the sounder tone is output via the SPO pin by connecting
the SPI input with the sounder output (SA0 or SA1). In addition, when the AD-converted
sounder tone is sent from the main device, the sounder tone is output via the SPO pin since the
CAO pin for CODEC output is internally connected.
R1I, R2I, RPO
R1I and R2I are for the inputs and RPO is for the output of the receive pre-amplifier.
Normally, R1I is connected via an AC-coupling capacitor to the CODEC analog output (CAO),
and R2I is used as the mixing signal input pin.
The typical gain between R1I and PRO is –6 dB. Through processor control, gains are variable
from –14 dB to 0 dB in 2 dB steps. In addition, the receive pad can control the gain of –9, –6, –3,
or 0 dB. The gain between R2I and RPO is fixed to 0 dB.
During the whole system power-on mode, the RPO output is in non-signal state, and speech
signal, R-tone, F-tone, PB acknowledge tone, side tone signal are output by processor control.
During the whole system power-down mode, the RPO output is the analog ground level.
The input resistance of R1I is typically between 20 kW and 100 kW (it varies by gain setting). The
input resistance of R2I is typically 20 kW.
MLDYI
Hold tone signal input.
For example, the output of external melody IC is connected to this pin. Through processor
control, the signal applied to MLDYI is output from the TO output pin as a hold tone on the
transmit path, and from the SPO output pin as a hold acknowledge tone on the receive path. The
typical gain between MLDYI and TO is –2 dB. Through processor control, a gain between –2 dB
and –11 dB is also settable at 3 dB steps. The typical gain between MLDYI and SPO is –3 dB.
Through processor control, a gain between –3 dB to –31 dB is also settable at 4 dB steps. MLDYI
is a high impedance input, so insert an about 100 kW bias resistor between MLDYI and SGT.
7/41
¡ Semiconductor
MSM7503
TPBI, TO
TPBI is the input and TO is the output of the transmit pre-amplifier (B).
Whenthehandsetisused,TPBIisconnectedtothetransmitpre-amplifier(A)outputpin(TPAO).
If adjustment of frequency characteristics on the transmit path is required, insert a circuit for
adjustment of characteristic between TPAO and TPBI. Through processor control, the signal
applied to this pin is output via the TO pin on the transmit path and its side tone via the RPO pin.
During the whole system power down mode, TO is at an analog ground level. The typical gain
between TPBI and TO is +17.7 dB. Through processor control, a gain between +17.7 dB and +8.7
dB is also settable at 3 dB steps.
The typical gain between TPBI and RPO is +3.0 dB. Through processor control, a gain between
–9 dB and +9 dB is variable in 3 dB steps. Changing the gain between TPBI and TO may change
the gain between TPBI and RPO. TPBI is a high impedance input, so insert an about 100 kW
resistor between TPBI and SGT.
A circuit example for adjustment of frequency characteristics
TPAO
TPBI
SGT
R3
C3
R4
C4
MPAI, MPAO
Handfree microphone pre-amplifier (A) input and output.
MPAIistheinputandMPAOistheoutput.ThespeechpathbetweenMPAIandMPAOisalways
active regardless of processor control. During the whole system power saving mode, MPAO is
at an analog ground level. The gain between MPAI and MPAO is typically +20 dB. Through
processor control, gains between +14 dB and +11 dB are also settable. MPAI is a high impedance
input, so insert an about 100 kW between MPAI and SGT.
MPBI, MPBO
The handfree microphone (B) input and output.
MPBI is the inverted input and MPBO is the output. With an external resistor, the amplifier gain
is adjusted in the range between –25 dB and +25 dB. A signal on the MPBO is output via the TO
pin through processor control. During the whole system power down mode, MPBO is at an
analog ground level. The gain between MPBO and TO is fixed to 0 dB.
8/41
¡ Semiconductor
MSM7503
TPAI, TPAO
The transmit pre-amplifier (A) input and output.
TPAI is the input and TPAO is the output. TPAI should be connected to the microphone of
handset via an AC-coupling capacitor if the DC offset appears at a transmit signal (offset from
SGT). The transmit path from TPAI to TPAO is always active regardless of processor control.
During the whole system power down mode, TPAO is at an analog ground level. The gain
between TPAI and TPAO is fixed to 20 dB.
SGT
Transmit path signal ground.
SGT outputs half the supply voltage. During the whole power down mode, SGT output is in a
high impedance state.
SGC
Bypass capacitor connecting pin for a signal ground level.
Insert a 0.1 mF high performance capacitor between SGC and AG.
VA, VD
+5 V power supply.
VA is for an analog circuit and VD is for a digital circuit. Both VA and VD should be connected
to the +5 V analog path of the system.
CAI, CAO
CODEC analog input and output.
CAI is the analog input of CODEC to be connected to the TO pin. If the DC offset voltage on the
TO signal is great, CAI should be connected via AC-coupling capacitor. At this time, insert an
about 100 kW bias resistor between CAI and SGT.
CAO is the analog output of CODEC. CAO should be connected to R1I via AC-coupling
capacitor.
A bias resistor is not required to R1I. During the whole system or CODEC power down mode,
CAO is at the SG voltage level.
9/41
¡ Semiconductor
MSM7503
PO0, PO1, PO2, PO3, PO4, PO5, PO6, PO7
Scanning outputs.
Theseoutputpinsneedexternalpull-upresistorsbecauseoftheiropen-draincircuits. But, when
these are used in combination with PI0 to PI7, pull-up resistors are not required. Through
processor control, these outputs can be set open or to digital "0". Initially, these outputs are set
at an opened state.
PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7
Scanning inputs. In the READ mode, data on PI0 to PI7 can be read out of the processor via data
bus (DB0 to DB7).
Since these inputs are pulled up inside the IC, external resistors are not required.
DB0, DB1, DB2, DB3, DB4, DB5, DB6, DB7
Data bus I/O pins.
ThesepinsareconfiguredasanoutputduringtheREADmodeonlyandasaninputduringother
modes.
T1N, T2N
Line transmit signal output.
Signals which consist of a total of 13 bits configured by the start bit (fixed at "1"), the K bit (fixed
at "1"), the D bits (control data of two bits), the transmit B bits (eight for voice and data) and the
DC bit (1 bit for the DC balance) at the bit rate of 256 kHz are output in burst mode from the T1N
pin and the T2N pin in turn at intervals of 125 msec. These output signals become the AMI code
with a duty of 50% in the line coding configuration by connecting to the line via a transformer
etc. IntheoutputtimingoftheT1NandT2Npins, thetopbitofthesignalisoutputafterreceiving
a 16-bit signal.
R1N, R2N
Line receive signal input.
Line signals (50% duty AMI code) which consist of a total of 16 bits configured by the frame
synchronous bits (four bits with "1"), the K bit (one bit for polling), the D bits (control data of two
bits), the receive B bits (eight bits for voice and data), and the DC bit (bit for DC balance) have
been transmitted in burst mode at the bit rate of 256 kHz at interval of 125 msec. These signals
should be input in the R1N pin and the R2N pin after separating then into the polarity of "+" and
"–".
10/41
¡ Semiconductor
MSM7503
SYNC
Synchronous signal (8 kHz) output.
This synchronous signal is generated by dividing the oscillator output of 8.192 MHz, applying
the frame synchronous bit included in the line signal as a reference phase. This signal also sent
to the tone generator and the CODEC inside the device. All timing signals of the CODEC are
synchronized by this signal.
CLK1
64 kHz CLK signal output synchronized to the SYNC signal output.
This signal is connected to the CODEC inside the device and is used as a bit clock for receiving
and sending the PCM I/O data from and to the ping-pong transmission interface. When an
external signal is input to the BHW pin, or when the FHW pin outputs signals for the external
circuit, thetimingshouldbesetbytheCLK1signal. ThissignalisalwaysoutputinthepowerON
mode.
CLK2
16 kHz CLK signal output synchronized to the SYNC signal output.
This signal can be used for the input or output of the control signal (BD input or FD output) of
16 kbps. This signal is always output in the power ON mode.
CLK3
CLK signal output of 256 kHz synchronized to the SYNC signal.
Thissignalcanbeusedwhenthecontrolsignalof16kHzisinputoroutputfromortotheexternal
device by the start-stop synchronization. This signal is always output in the power ON mode.
CLC
Control signal input for phase-inverting the 256 kHz CLK signal which is output form the CLK3
pin.
If the reference phase is set by setting CLC to "0", the CLK signal of 256 kHz is phase-inverted
against the reference phase by setting CLC to "1".
11/41
¡ Semiconductor
MSM7503
FHW
TheoutputoftheextractedB-bit(8-bitsequence)fromreceivesignalswhichareinputtoR1Nand
R2N.
ThissignalisoutputsynchronizingtotherisingedgeofaCLK1(64kHz)outputsignalbeginning
with the rising edge of a SYNC output signal.
Since this pin is connected to the D/A converter of the CODEC inside device, the B bits of receive
signals are decoded to analog signals.
BHW
Input to the B bit slot of line signals transmitted from the T1N and T2N pins.
The input signal to this pin must be synchronized to the CLK1 output signal (64 kHz) beginning
with the rising edge of the SYNC output signal. The input signal is shifted at the falling edge of
CLK1.
In the case of inserting the voice data into the transmit B bit, the PCM output of the CODEC is
connected to this input pin, and inserting the voice data into the B bit slot is enabled by setting
SW12 to ON through processor control. In this case the BHW pin is used as an output pin, so
external signals can not be input to this pin. This is an input and output pin of an open drain type
with a pulled-up resistance of 5 kW.
FD
The signal output of the extracted Control bit (2-bit sequence at 16 kbps) from line signals which
are input to the R1N and R2N pins.
ThissignalisoutputsynchronizingtotherisingedgeofaCLK2outputsignalbeginningwiththe
rising edge of the SYNC output signal.
FD is an output pin of an open drain type with a pulled-up resistance of about 10 kW.
FK
The signal output of the extracted K bit (8 kbps) from the line receive signals which are input to
the R1N and R2N pins.
This signal is output synchronizing to the rising edge of a SYNC output signal. FK is an output
pin of an open drain type with a pulled-up resistance of about 10 kW.
12/41
¡ Semiconductor
MSM7503
BD
Input to the D bit (2-bit sequence at 16 kbps) of line signals transmitted from the T1N and T2N
pins. When the BDS control pin is in "0", this pin enters the synchronous mode and data must be
input to this pin synchronizing with CLK2 (16 kHz).
When the BDS control pin is set to "1", this pin enters the asynchronous data input mode and the
asynchronousdataof11bitsincludingthestartbitandstopbitcanbeinputatdatarateof16kbps.
BDS
Control signal input for selection of the synchronous mode or asynchronous mode for control
data (D-bit) input.
Whenbeingat"0"level, thispinentersthesynchronousdatainputmode, whenbeingat"1"level,
this pin enters the asynchronous data input mode.
PS
Monitoring signal output for the state of the ping-pong transmission. When frames are
synchronized(innormaloperation)afterreceivingmorethanthreeconsecutiveframesynchronous
signals which are included in the line receive signal sequence, this pin outputs "1".
Otherwise, this pin outputs "0". PS is an output of an open drain type with pulled-up resistance
of about 10 kW.
X1, X2
CLK oscillator circuit input and output. X1 is input and X2 is output. A crystal oscillator of 8.192
MHz should be connected between X1 and X2. If the frequency deviation in CLK oscillation is
great with respect to the receive data rate, the noise of the CODEC increases. The oscillation
frequency deviation in CLK should be kept in ±20 ppm or less.
13/41
¡ Semiconductor
MSM7503
XOUT
8.192 MHz CLK signal output.
Ifcapacitanceloadisgiventotheoutput, thecurrentconsumptionwillincrease. About0.03mA/
pF.
AD0, AD1
Address data inputs for the internal control registers.
Addressing of the internal control registers is executed by AD0 and AD1 and sub address data,
DB7 and DB6.
AD1 AD0 DB7 DB6
Function
ON/OFF controls of sounder, R-Tone, F-Tone
Level/Frequency controls of sounder, R-Tone
PB tone control
0
0
1
0
1
0
0
0
Controls of internal speech path switch and general latch
Watchdog timer reset
1
1
0
0
0
1
Controls of receive gain and side tone gain
Controls of transmit hold tone, PB tone, handfree input, handset inputs gain
Controls of speaker pre-amplifier gain and additional speaker gain
Controls of receive PAD and incoming tone input gain
Scanning output control
WRITE
0
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
—
0
—
0
Scanning interrupt reset
0
1
LCD deflection angle control voltage setting
Power ON/OFF control
1
0
1
1
CODEC control (Controls of companding law and digital loop)
READ
1
0
—
—
Scanning data read-out
WRN
Write signal for internal control registers.
Data on the data bus is written into the registers at the rising edge of WRN under the condition
of digital "0" of CEN (Chip Enable). While CEN is in digital "1" state, WRN becomes invalid. The
Write cycle is a minimum of 2 ms regardless of the presence or absence of clock signals.
14/41
¡ Semiconductor
MSM7503
RDN
Read signal input to read PI0 to PI7 out of the processor.
When CEN and RDN are in digital "0" state, the digital values on PI0 to PI7 are output onto the
data buses DB0 to DB7. While CEN is in digital "1" state, the RDN signal becomes invalid.
CEN
Chip Enable signal input.
When CEN is in digital "0" state, WRN and RDN are valid.
VLCD
By processor control, VLCD outputs a DC voltage between 0 and 1.4 V is about 0.2 V step.
This is used to control the deflection angle of the LCD display. VLCD has the internal resistance
value of about 1 kW, so the external load of over 100 kW should be used. During initialized state,
VLCD outputs the voltage of 0 V.
LRSTN
Reset signal output for external circuit.
This reset signal output pin goes to "0" level when the power supply is approximately more than
4.0 V or when the TEST pin is at digital "0" level and the watchdog timer (WDT) outputs a signal.
The WDT output does not affect the LSRTN output when TEST pin is at digital "1" level.
The LRSTN signal is also used as a reset signal for internal registers.
When LRSTN is at "0" level, all internal control registers are initialized.
The internal WDT outputs a 500 ms cycle signal when the LRSTN is at digital "1" and the
processor does not send a timer reset signal.
Refer to the figure 1 for the output timing of this output.
TEST
Control signal input for deciding valid/invalid of reset control from the internal WDT output.
When this input pin is at digital "0" level, the LRSTN output goes to "0" level. When this input
pin is at "1" level, the internal WDT does not affect the LSRTN output.
CTEST
Test pin for shipment testing.
This pin should be set to "0" level.
15/41
¡ Semiconductor
MSM7503
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
VDD
Condition
AG, DG = 0 V
AG, DG = 0 V
AG, DG = 0 V
—
Rating
0 to 7
Unit
V
VAIN
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
-55 to 150
V
VDIN
V
TSTG
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature Range
Input High Voltage
Symbol
VD
Condition
VA, VD (Voltage must be fixed)
—
Min.
Typ.
5.0
25
Max.
Unit
V
4.75
–10
2.2
0
5.25
70
Ta
°C
V
VIH
VIL
All Digital Input Pins
All Digital Input Pins
All Digital Input Pins
All Digital Input Pins
PO0 to PO7
—
VDD
0.8
50
Input Low Voltage
—
V
Digital Input Rise Time
Digital Input Fall Time
tIr
—
—
ns
ns
kW
tIf
—
—
50
RDL
10
—
—
PO0 to PO7
—
—
100
10
Digital Output Load
CDL
pF
Other digital output pins except PO0 to PO7
—
—
Oscillating Frequency
Allowable Frequency Deviation
Temperature Characteristics
Equivalent Series Resistance
Production Load Capacitance
—
8.192
—
—
MHz
ppm
ppm
W
25°C 3°C
–50
–50
—
50
—
50
—
80
—
16
—
pF
Recommend Operating Conditions (Analog Interface)
Parameter
Symbol
Condition
TPAO, MPAO, MPBO, TO,
RPO, SPO, CAO
Min.
Typ.
Max.
Unit
20
—
—
Analog Load Resistance
RAL
kW
RMO0, RMO1 with respected to
SG Level
0.6
—
—
—
—
30
TPAO, MPAO, MPBO, TO,
RPO, SPO, CAO
pF
nF
Analog Load Capacitance
CAL
RMO0, RMO1
—
–10
–50
–25
–100
—
—
—
—
—
70
10
TPAI, TPBI, MPAI
MLDY
50
With respect
to SG
Allowable Analog
Input Offset Voltage
Voff
mV
R1I, R2I, SPI
CAI
25
100
16/41
¡ Semiconductor
MSM7503
Recommended Operating Conditions (Processor Digital Interface)
Parameter
Write Pulse Period
Write Pulse Width
Read Pulse Width
Symbol
PW
Condition
WRN
Min.
2000
100
200
80
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
—
—
—
TW
WRN
TR
RDN
tAW1
tAR1
tAW2
tAR2
tCW1
tCR1
tCW2
tCR2
tDW1
tDW2
AD0, AD1ÆWRN
AD0, AD1ÆRDN
WRNÆAD0, AD1
RDNÆAD0, AD1
CENÆWRN
Address Data
Setup Time
80
50
Address Data
Hold Time
See Fig.2
50
80
CEN Setup Time
CEN Hold Time
CENÆRDN
80
WRNÆCEN
50
RDNÆCEN
50
Data Setup Time
Data Hold Time
DB0 to 7ÆWRN
WRNÆDB0 to 7
110
20
Recommended Operating Conditions (Ping-Pong transmission Interface)
Parameter
B Signal Set-up Time
B Signal Hold Time
Symbol
TSBHW
THBHW
TSBD
Condition
BHW Input
Min.
50
Typ.
—
Max.
—
Unit
ns
See Fig. 3
See Fig. 3
See Fig. 4
See Fig. 4
See Fig. 5
BHW Input
BD Input
BD Input
R1N, R2N
50
—
—
ns
D Signal Set-up Time
D Signal Hold Time
50
—
—
ns
THBD
50
—
—
ns
Receive Data Cycle Time
Receive Data Width
Receive Flame Cycle Time
TCB
—
3.906
1.953
125
—
ms
ms
ms
TWB
Width of "L" at R1N and R2N See Fig. 5
1.35
—
2.5
—
TFM
—
See Fig. 5
17/41
¡ Semiconductor
MSM7503
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 5 V 5ꢀ, Ta = –10°C to 70°C)
Parameter
Symbol
IDD1
IDD2
IDD3
Vth
Condition
Min.
—
Typ.
10
3
Max. Unit
Operating Mode (No Signal, Sounder OFF)
Whole system Power Down
CODEC Power Down
20
6
mA
mA
mA
V
Power Supply Current
—
—
7
14
Power Supply Voltage Detection
Power Supply Voltage Non-Detection
Input High Voltage
Power Supply Voltage at LRSTN = 1, See Fig. 1
Power Supply Voltage at LRSTN = 0, See Fig. 1
—
3.9
—
—
—
—
—
—
—
—
—
—
—
—
—
Vtl
3.8
VDD
0.8
2.0
2.0
0.5
25
V
VIH
2.2
0.0
—
V
Input Low Voltage
VIL
—
V
Digital Pins except for PI0 to PI7
PI0 to PI7 (Internal Pull-up Pins)
Digital Pins except for PI0 to PI7
PI0 to PI7 (Internal Pull-up Pins)
Output Pins 1 *1 IOH = 0.1 mA
Output Pins 2 *2 IOH = 1.6 mA
All Output Pins IOH = 1 mA
mA
mA
mA
mA
High Input Leakage
Current
IIH
IIL
—
—
Low Input Leakage
Current
10
2.4
2.4
3.8
VDD
VDD
VPP
Digital Output High
Voltage
VOH
V
Digital Output Low
Voltage
VOL
IO
I
OL = –1.6 mA
0.0
—
0.4
V
DB0 to DB7
Digital Output Leakage
Current
—
—
—
10
mA
(Write Mode)
–200
200
Analog Output Offset
Voltage
TPAO, MPAO
MPBO, TO, CAO, RPO, RMO0, RMO1, SPO
—
Voff
CIN
mV
pF
–100
—
—
5
100
—
Input Capacitance
TPAI, TPBI, MLDYI, RMI, MPAI,
MPBI
—
10
—
MW
Analog Input Resistance
RIN
R1I, R2I, SPI
10
—
—
1
—
—
kW
CAI (fin : < 4 kHz)
MW
VA/2
–0.05
VA/2
+0.05
SG Voltage
—
—
VA/2
V
ISGF
ISGS
FORCE Current
SINK Current
1.0
0.3
1.5
0.5
—
—
SG Drive Current
mA
Equivalent Pull-up Resistance RPULL
PI0 to PI7, VI = 0 V
200
370
500
kW
Notes: *1 BHW, FK, FD, PS
*2 SYNC, CLK1, CLK2, CLK3, T1N, T2N, XOUT, LA, LB, LRSTN, DB0 TO DB7
18/41
¡ Semiconductor
MSM7503
Digital Interface Characteristics
(VDD = 5 V 5ꢀ, Ta = –10°C to 70°C)
Parameter
Symbol
Condition
WRÆLA, LB
Min.
Typ.
Max. Unit
Digital Output (Latch) Delay Time
tpd LA
See Fig. 2
0.2
—
1.5
ms
WRÆPO0 to PO7
Key Scanning
Output Delay Time
See
Fig. 2
tpd scn
0.2
—
1.5
ms
Pull-up resistance 10 kW
Digital Output (Data) Delay Time
tpd data
tdRST1
tdRST2
TWDT
RDÆDB0~DB7
LRSTN 0Æ1
LRSTN 1Æ0
See Fig. 2
10
—
—
—
—
—
366
366
366
—
—
—
—
—
—
—
—
—
—
—
—
20
128
0.01
500
0.85
1.7
—
100
—
—
—
—
—
488
488
488
—
—
—
—
—
—
—
—
—
—
—
—
ns
ms
ms
Delay Time of Power
Supply Voltage Detect
See Fig. 1
ms
Delay Time of LRSTN
due to WDT
tdRST3
tWRST
tdSCK1
tsSCK2
tdSCK3
tdFHW
See Fig. 1
ms
SYNCÆCLK1
SYNCÆCLK2
SYNCÆCLK3
CLK1ÆFHW
See Fig. 3
See Fig. 4
CLK Output Delay Time
—
ns
—
B Signal Delay Time
See Fig. 3
10
ns
ns
LÆH
340
10
tdFD
tdFK
D Signal Output Delay Time
CLK2ÆFD
See Fig. 4
See Fig. 4
HÆL
LÆH
HÆL
740
500
8
K Signal Output Delay Time
ns
SYNC Output Frequency
SYNC Output Width
fSYNC
TWSYNC
fCLK1
fCLK2
fCLK3
—
kHz
ms
16.6
64
CLK1 Output Frequency
CLK2 Output Frequency
CLK3 Output Frequency
CLK Output Duty Ratio
Line Output Signal Width
kHz
kHz
kHz
ꢀ
16
256
50
CLK1, CLK2, CLK3
T1N, T2N "L" Width
See Fig. 5
SYNC, CLK1, CLK2
CLK3 When use Xtal
tWF
1.953
ms
Clock Output Jitter Width
—
250
—
ns
19/41
¡ Semiconductor
MSM7503
AC Characteristics 1 (CODEC)
(VDD = 5 V 5ꢀ, Ta = –10°C to 70°C)
Freq. Level
(Hz) (dBm0)
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
Loss T1
60
20
–0.20
27
0.07
Reference
–0.03
0.06
—
0.20
Loss T2 300
Loss T3 1020
Loss T4 2020
Loss T5 3000
Loss T6 3400
Loss R1 300
Loss R2 1020
Loss R3 2020
Loss R4 3000
Loss R5 3400
SD T1
Transmit Frequency
Response
0
0
dB
–0.15
–0.15
0.0
0.20
0.20
0.80
0.20
0.38
–0.15
–0.03
Reference
–0.02
0.15
0.56
43.0
Receive Frequency
Response
dB
dB
dB
dB
–0.15
–0.15
0.0
35
0.20
0.20
0.80
—
3
SD T2
0
35
35
29
24
37
37
37
30
41.0
38.0
31.0
26.5
43.0
41.0
40.0
34.0
31.0
0.01
Reference
–0.05
0.05
0.30
0.0
Reference
–0.10
–0.30
–0.40
—
—
—
—
—
—
—
—
Transmit Signal to
Distortion Ratio
SD T3
SD T4
SD T5
SD R1
SD R2
SD R3
SD R4
SD R5
GT T1
GT T2
GT T3
GT T4
GT T5
GT R1
GT R2
GT R3
GT R4
GT R5
1020
1020
1020
1020
–30
–40
–45
3
0
*1
*1
Receive Signal to
Distortion Ratio
–30
–40
–45
3
–10
–40
–50
–55
3
–10
–40
–50
–55
25
–0.3
—
0.3
Transmit Gain
Tracking
–0.3
–0.5
–1.2
–0.3
0.3
0.4
1.2
0.3
Receive Gain
Tracking
–0.3
–0.5
–1.2
0.3
0.5
1.2
dB
AIN = SG
*1
m
A
—
—
–73.5
–71
–70
–68
Nidle T
Nidle R
—
—
—
—
0
Idle Channel Noise
dBmOp
*1
*2
—
–78.0
–75
AV T
AV R
CAI Æ BHW
FHW Æ CAO
0.5671
0.5671
0.6007
0.6007
0.6363
0.6363
1020
Vrms
ms
Absolute Amplitude
Absolute Delay Time
CAI Æ CAO
BCLOCK = 64 kHz
Td
1020
0
—
0.58
0.60
Notes: *1 The Psophometric weighted filter is used
*2 PCMIN input: idle CODE
20/41
¡ Semiconductor
MSM7503
AC Characteristics 1 (CODEC) (Continued)
(VDD = 5 V 5ꢀ, Ta = –10°C to 70°C)
Freq. Level
(Hz) (dBm0)
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
tgd T1
500
600
1000
2600
2800
500
—
—
—
—
—
—
—
—
—
—
0.19
0.12
0.02
0.05
0.08
0.0
0.0
0.0
0.09
0.12
0.75
0.35
0.125
0.125
0.75
0.75
0.35
0.125
0.125
0.75
t
t
t
t
gd T2
gd T3
gd T4
gd T5
Transmit Group Delay
0
*3
ms
ms
t
t
t
t
t
gd R1
gd R2
gd R3
gd R4
gd R5
600
Receive Group Delay
Crosstalk Attenuation
1000
2600
2800
0
0
*3
CR T
CR R
CAI Æ CAO
70
75
78
86
—
—
dB
dB
1020
FHW Æ BHW CAO left open
Discrimination
Out-of-band Signal
4.6 kHz to
72 kHz
DIS
S
–25
0
30
—
—
25
32.0
–37.5
–52
—
0 to 4000 Hz
4.6 kHz to 100 kHz
2fa–fb
Out-of-band Signal
Spurious
300 to
3400
–35 dBmO
–35 dBmO
fa = 470
fb = 320
IMD
–4
Intermodulation Distortion
PSR T
PSR R
Power Supply Noise
Rejection Ratio
0 to 50
kHz
50
mVpp
dB
*4
30
—
Notes: *3 The minimum value of group delay only is defined as the reference value
*4 Measurement at the idle channel noise
21/41
¡ Semiconductor
MSM7503
AC Characteristics 2 (Transmit Path)
(VDD = 5 V 5ꢀ, Ta = –10°C to 70°C)
Freq. Level
(Hz) (dBV)
Parameter
Pre-Amp Gain
Symbol
Condition
Min.
Typ.
Max. Unit
GTPA
TPAI-TPAO
18.0
15.7
20.0
17.7
22.0
19.7
dB
dB
TPBI-TO
Set at typical gain
Transmit Path Gain
GTPB1
1020 –24.0
1020 –24.0
RG1TPB
RG2TPB
RG3TPB
Setting,
than
typical gain
–3 dB
–6 dB
–9 dB
–5.0
–8.0
–11.0
–3.0
–6.0
–9.0
–1.0
–4.0
–7.0
Transmit Path Gain
Setting (VOL8)
dB
dB
dB
Microphone Pre-Amp
Gain
MPAI-MPAO
Set at typical gain
GMPA
18.0
20.0
22.0
Microphone Pre-Amp
Gain Setting
(VOL9)
Setting,
than
typical gain
RG1MPA
RG2MPA
–6 dB
–9 dB
–8.0
–6.0
–9.0
–4.0
–7.0
–11.0
Additional Transmit
Signal Gain
GTMX
1020
–4.0
–24
—
MPBO-TO
–2.0
50
0.0
60
2.0
—
dB
dB
Cross Talk Attennation
at Microphone Signal Path
TMX OFF 1020
MPAI-TO
In-Channel PB Signal
Output Level
TO per wave
set at typical gain
VPBT1
—
—
–19.4
–17.4
–15.4
dBV
GPBT1
GPBT2
GPBT3
Setting,
than
typical gain
–3 dB
–6 dB
–9 dB
–5.0
–8.0
–11.0
–3.0
–6.0
–9.0
–1.0
–4.0
–7.0
In-Channel PB Signal
Output Level Setting
(VOL4)
dB
—
In-Channel PB Signal
Frequency Deviation
DfPBT
—
—
—
—
–1.0
—
—
1.0
ꢀ
In-Channel PB Signal
Distortion
THDPBT
In-band Distortion
–35
–30
dB
MLDYI-TO
Set at typical gain
Hold Tone Path Gain
GPAT
–4.0
–2.0
0.0
dB
dB
1020
–4.0
RG1PAT
RG2PAT
RG3PAT
Setting,
than
typical gain
–3 dB
–6 dB
–9 dB
–5.0
–8.0
–11.0
–3.0
–6.0
–9.0
–1.0
–4.0
–7.0
Hold Tone Path Gain
Setting
(VOL3)
TPAI:Terminated in 510 W
Measured at TO
TPAO-TPBI Directly
connected Set at
typical gain *5
Idle Channel Noise
NiTPA
—
—
—
—
–70
—
—
—
dBV
Vpp
TPAO, TO,
MPAO, MPBO
RL = 20 kW
Maximum Output Voltage
Swing
VOT
1020
2.4
Note:
*5 Noise band width: 0.3 to 3.4 kHz, non weighted
22/41
¡ Semiconductor
MSM7503
AC Characteristics 3 (Receive Path)
(VDD = 5 V 5ꢀ, Ta = –10 to 70°C)
Freq. Level
(Hz) (dBV)
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
Typical gain is set
between R1I and RPO
GRPA
Receive Signal Path Gain
–8.0
–6.0
–4.0
dB
RGRPA1
RGRPA2
RGRPA3
RGRPA4
RGRPA5
RGRPA6
RGRPA7
RGPAD1
RGPAD2
RGPAD3
–8 dB
–6 dB
–4 dB
–2 dB
2 dB
4 dB
6 dB
–3 dB
–6 dB
–9 dB
–10.0
–8.0
–6.0
–4.0
0.0
2.0
4.0
–5.0
–8.0
–11.0
–8.0
–6.0
–4.0
–2.0
2.0
4.0
6.0
–3.0
–6.0
–9.0
–6.0
–4.0
–2.0
0.0
4.0
6.0
Setting,
than
typical gain
Receive Signal
Path Gain Setting
(VOL1)
dB
1020
1020
–4.0
–4.0
8.0
Setting,
than
typical gain
–1.0
–4.0
–7.0
Receive PAD
Gain Setting
(VOL10)
dB
Additional Receive
Signal Path Gain
GRMX
GSIDE
R2I and RPO
–2.0
1.0
0.0
3.0
2.0
5.0
dB
dB
Typical gain is set
betweenTPBI and RPO
Side Tone Path Gain
RGSIDE1
RGSIDE2
RGSIDE3
RGSIDE4
RGSIDE5
RGSIDE6
6 dB
3 dB
–3 dB
–6 dB
4.0
1.0
–5.0
–8.0
–11.0
–14.0
6.0
3.0
–3.0
–6.0
–9.0
–12.0
8.0
5.0
–1.0
–4.0
–7.0
–10.0
Setting,
than
typical gain
Side Tone Path Gain
Setting
(VOL2)
1020 –14.0
dB
dB
–9 dB
–12 dB
Typical gain is set
between RPO and SPO
Speaker Pre-Amp
Gain
GSP
–2.0
0.0
2.0
RGSP1
RGSP2
RGSP3
RGSP4
RGSP5
RGSP6
RGSP7
–4 dB
–8 dB
–6.0
–4.0
–8.0
–2.0
–6.0
–10.0
–14.0
–18.0
–22.0
–26.0
–30.0
Setting,
than
typical gain
–12 dB
–16 dB
–20 dB
–24 dB
–28 dB
–12.0
–16.0
–20.0
–24.0
–28.0
–10.0
–14.0
–18.0
–22.0
–26.0
Speaker Pre-Amp
Gain Setting
(VOL5)
1020
1020
–4.0
–4.0
dB
dB
Additional Speaker
Input Path Gain
Typical gain is set
between SPI and SPO
GSPI
–2.0
0.0
2.0
23/41
¡ Semiconductor
MSM7503
AC Characteristics 3 (Receive Path) (Continued)
(VDD = 5 V 5ꢀ, Ta = –10°C to 70°C)
Freq. Level
(Hz) (dBV)
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
RGSPI1
RGSPI2
RGSPI3
Setting,
than
typical gain –18 dB
Typical gain is set
between MLDYI and SPO
–6 dB
–12 dB
–8.0
–14.0
–20.0
–6.0
–12.0
–18.0
–4.0
–10.0
–16.0
Additional Speaker
Input Path Gain Setting
(VOL6)
Hold Acknowledge Tone
Path Gain
1020
1020
–4.0
–4.0
dB
GPAR
VPBRP
VPBSP
–5.0
–32.1
–30.2
–3.0
–30.1
–28.2
–1.0
–28.1
–26.2
dB
RPO per wave
dBV
dBV
PB Acknowledge Tone
Output Level
—
—
SPO per wave
Set at typical gain
PB Acknowledge Tone
Frequency Difference
DfPBR
THDPBR
GCAO
—
—
—
—
RPO, SPO
RPO, SPO
–1.0
—
—
–35
0.0
1.0
–30
2.0
ꢀ
dB
dB
PB Acknowledge Tone
Distortion
Incoming Tone Speaker
Output Path Gain
Typical gain is set
between CAO and SPO
–2.0
1020
–20
Incoming Tone Speaker
Output Path Gain
Setting (VOL11)
Setting,
than
typical gain
RGCAO1
RGCAO2
–10 dB
–20 dB
–12.0
–22.0
–10.0
–20.0
–8.0
dB
–18.0
R1I:SG,
Measured at RPO
Set at typical gain.
NiRPO
NiSPO
—
—
—
—
—
—
–86.0
–89.0
—
—
dBV
dBV
R1I:SG,
Measured at SPO
Set at typical gain.
Idle Channel Noise
R1I:SG, Gain
0 dB
RMO0, RMOB *5
NiRMO
VOR
—
—
—
—
—
–86.0
—
—
—
dBV
Vpp
RPO, SPO
RL = 20 kW
Maximum Output Amplitude
2.4
Resister of 1.2 kW
between RMO0 and RMO1
Measurement at each output
Maximum Output
Amplitude
VOR
1020
—
–4
3.6
4.5
—
55
—
—
Vpp
Cross Talk Attennation
between Transmit Path
and Receive Path
RX to TX 1020
Between R1I and TO
dBV
Note:
*5 Noise band width : 0.3 kHz to 3.4 kHz, non weighted
24/41
¡ Semiconductor
MSM7503
AC Characteristics 4 (Ringing Tone)
(VDD = 5 V 5ꢀ, Ta = –10°C to 70°C)
Parameter
R-Tone Output
Symbol
Condition
Level Setting 1
Min.
63
84
105
126
112
Typ.
90
120
150
180
Max. Unit
117
156
195
Level Setting 2
Level Setting 3
Level Setting 4
VRTO
RPO
SPO
mVpp
Amplitude (VOL7)
234
VFTRP
VFTSP
RPO
SPO
160
208
mVpp
14.5
F-Tone Output Amplitude
7.5
154
49
11.0
220
70
0 dB
–10 dB
–20 dB
286
Gain
Setting
S-Tone Output
Amplitude (VOL12)
VSTSP
DfT
91
22
mVpp
ꢀ
12
17
—
–0.5
—
–0.5
Frequency Deviation
AC Characteristics 4 (Sounder Output Circuit)
(VDD = 5 V 5ꢀ, Ta = –10°C to 70°C)
Freq. Level
(Hz) (dBV)
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
VST1
VST2
VST3
VST4
ROSAO
Reference level Vol.1
of DG RLSA0 Vol.2
3.5
1
0.25
0.2
—
4
—
1.5
0.6
0.35
—
—
1.2
0.44
0.27
2
Sounder Tone Output
Amplitude (VOL13)
—
—
V
is 40 kW or
more.
Vol.3
Vol.4
Output Resistance
Output Load
—
kW
kW
RLSAO
With respect to DG
40
—
LCD Defelection Angle Control Voltage Output
(VDD = 5 V 5ꢀ, Ta = –10°C to 70°C)
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
DB2 DB1 DB0
1.1
0.9
0.7
0.5
0.3
0.2
0.15
0.0
—
1.4
1.2
1.0
0.8
0.8
0.4
0.2
0.0
1.0
1.7
1.5
1.3
1.1
0.9
0.6
0.4
0.05
—
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
—
1
0
1
0
1
0
1
0
Output Voltage
VLCD
V
Output Resistance
Output Load
ROLCD
RLLCD
kW
kW
To GND
100
—
—
25/41
¡ Semiconductor
MSM7503
TIMING DIAGRAM
Reset Signal Output Timing
Vth
tdRST1
Vtl
tdRST2
Vth
tdRST1
VD
(VA)
LRSTN
(a) LRSTN output timing by the power supply voltage charging
Writing the reset
data of WDT
TWDT
Internal WDT output
tdRST3
TWDT
LRSTN
tWRST
(b) LRSTN output timing by the internal WDT
Figure 1
Processor Interface Timing
AD0, AD1
tAW1
tAW2
tAR1
tAR2
CEN
tCW1
tCW2
tCR1
tCR2
WRN
tR
tW
tDW1 tDW2
RDN
tPDDATA
tPDDATA
DB0 to DB7
PO0 to PO7
tPDSCN
tPDLA
Latch Output
Figure 2
26/41
¡ Semiconductor
MSM7503
B-bit signal I/O Timing
1/fSYNC
TWSYNC
SYNC
1/fCLK1
tdSCK1
CLK1
tdFHW
FHW Output
F0
B0
F1
F2
B2
F3
F4
B4
F5
B5
F6
B6
F7
B7
F0
B0
F1
B1
B1
B3
BHW Input
TSBHW
THBHW
Figure 3
D-, K-bit Signal I/O Timing
SYNC
1/fCLK2
tdSCK2
CLK2
1/fCLK3
tdSCK3
CLK3
(CLC=1)
CLK3
(CLC=0)
tdFD
tdFD
FD Output
BD Output
TSBD
tdFK
THBD
FK Output
Figure 4
27/41
Ping-Pong Transmission Signal Timing
1 Frame (TFM 125 ms)
Receive (62.4 ms)
Transmit (50.78 ms)
Wave Shape
of Line Signal
R1N
Receive
TWB
R2N
TCB
Receive Data
1
1
1
1
K
D
B
DC
FP
K
D
B
125 ms
SYNC
CLK1
FHW
RB1
RB2
TB8
BHW
CLK2
CLK3
RD1
FD
BD
FK
TD1
TD2
RK
T1N
Transmit
T2N
tWF
D
Transmit Data
1
1
B
DC
Figure 5
FUNCTIONAL DESCRIPTION
Control Data Description
Sounder Calling Tone and tone ON/OFF control
WRITE Mode
Address Data AD1 = 0, AD0 = 0
Control Data
Description for Control
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
Sounder output ON
Sounder output OFF
Sounder output ON
Sounder output OFF
SW19 ON
SW19 OFF
SW20 ON
SW20 OFF
SW13 ON
Tone Output: SA0
Tone Output: SPO *1
0
R-Tone
R-Tone
F-Tone
F-Tone
F-Tone
F-Tone
ON
0
0
0
0
OFF
SW13 OFF
SW14 ON,
Tone Output: RPO
Tone Output: SPO
ON(1 kHz)
OFF
SW15 OFF,
0
1
SW14 OFF, SW15 OFF,
SW14 OFF, SW15 ON,
SW14 OFF, SW15 OFF,
ON(1 kHz)
OFF
*1: This Sounder Output is sent at the timing shown below.
ON
OFF
ON
OFF
0.625 s
2 s
0.25 s 0.125 s
Level and frequency control of sounder and R-tone
WRITE Mode
Address Data AD1 = 0, AD0 = 0
Control Data
Description for Control
SA0 output sounder volume 1 (Large)
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
1
0
1
0
1
Sounder volume and tone
are defind at a time.
SA0 output sounder volume 2 (Middle)
—
—
—
SA0 output sounder volume 3 (Small 1)
At the initial setting, sounder
volume 1 and sounder
combination tone 1 are set.
SA0 sounder volume:
VOL 13
SA0 output sounder volume 4 (Small 2)
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
Sounder combination tone 1 (16 Hz wamble tone with 1000 Hz/1333 Hz)
Sounder combination tone 2 (16 Hz wamble tone with 667 Hz/800 Hz)
Sounder combination tone 3 (8 Hz wamble tone with 800 Hz/1000 Hz)
Sounder combination tone 4 (Single tone of 1000 Hz)
Sounder combination tone 5 (Single tone of 800 Hz)
Sounder combination tone 6 (Single tone of 400 Hz)
R-Tone output level 1 (90 mVPP at RPO output)
R-Tone output level 2 (120 mVPP at RPO output)
R-Tone output level 3 (150 mVPP at RPO output)
R-Tone output level 4 (180 mVPP at RPO output)
R-Tone 400 Hz single tone
0
—
0
1
0
0
1
1
0
1
0
1
R-Tone output level = VOL 7
—
R-Tone output level and
frequency are defined at a
time.
At the initial setting, output
level 1 and a single 400 Hz
tone are set.
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
R-Tone 425 Hz single tone
R-Tone 440 Hz single tone
—
R-Tone 450 Hz single tone
R-Tone 400 Hz ON/OFF by 16 Hz
R-Tone 400 Hz ON/OFF by 20 Hz
PB tone control
WRITE Mode
Address Data AD1 = 0, AD0 = 0
Control Data
Output PB Frequency
Low High
697 Hz 1209 Hz
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
1
2
3
A
4
5
6
B
7
8
9
C
*
0
#
D
When PBTC = 0
SW16: ON
697
697
697
770
770
770
770
852
852
852
852
941
941
941
941
1336
1477
1633
1209
1336
1477
1633
1209
1336
1477
1633
1209
1336
1477
1633
SW17: ON
SW18: OFF
PB tone is sent to the transmit path T0 and the receive path RPO.
When PBTC = 1
SW16: OFF
SW17: OFF
SW18: ON
1
PBTC
1
0
PB tone is sent to the receive path SPO only.
0
0
PB tone stop
SW16, SW17, SW18: OFF
SW control and timer reset
WRITE Mode
Address Data AD1 = 0, AD0 = 0
Control Data
Description for Control
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
1
1
0
1
SW1
SW2
SW3
ON
ON
ON
Transmit handfree input
Transmit handset input
Receive input
When hold tone or PB tone transmit is
selected, these inputs are muted.
—
When Handfree input is selected, side
tone is muted.
0
1
0
1
SW4
ON
Side tone input
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
SW5
SW6
SW7
SW8
SW9
ON
ON
ON
ON
ON
Receive main amplifier input
Receive speaker input
—
—
—
1
0
Transmit path hold tone input
Receive path hold tone Acknowledge input
Additional receive input
Additional speaker input
Speaker DEC input
1
1
SW10 ON
SW11 ON
SW12 ON
LA = 1
Speaker DEC input = CODEC AOUT
—
PCM output enable
General Latch output for external control
LB = 1
0
0
1
0
0
1
Above codes
Above corresponding SW or latch is set to OFF or "0".
All of above SWs or latches are set to OFF or "0" at the initial setting stage.
Watchdog timer is reset.
0
0
0
0
0
0
0
0
1
1
Gain setting (receive gain, side tone gain)
WRITE Mode
Address Data AD1 = 0, AD0 = 0
Control Data
Description for Control
Typical receive gain (–6dB)
Remarks
Receive gain = VOL1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
–8 dB than the typical gain
–6 dB than the typical gain
–4 dB than the typical gain
–2 dB than the typical gain
+2 dB than the typical gain
+4 dB than the typical gain
+6 dB than the typical gain
Side tone gain = VOL2
Receive gain and side tone gain are set at a time.
At the initial setting, the typical gain is set.
—
—
—
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Typical side tone gain (–9 dB)
–12 dB than the typical gain
–9 dB than the typical gain
–6 dB than the typical gain
–3 dB than the typical gain
+3 dB than the typical gain
+6 dB than the typical gain
Side tone OFF (VOL2 max loss)
—
Gain control (transmit hold tone, PB tone, microphone input, handset input)
WRITE Mode
Address Data AD1 = 0, AD0 = 1
Control Data
Description for Control
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
1
0
1
0
1
Typical transmit hold tone gain (–2 dB)
–3 dB with respect to the typical gain
–6 dB with respect to the typical gain
–9 dB with respect to the typical gain
Typical transmit PB tone gain (+4 dB)
–3 dB with respect to the typical gain
–6 dB with respect to the typical gain
–9 dB with respect to the typical gain
Typical handfree input gain (+20 dB)
–6 dB with respect to the typical gain
–9 dB with respect to the typical gain
—
Transmit hold tone gain = VOL3
Transmit PB tone gain = VOL4
—
—
Hold tone gain and PB tone
gain are set at a time.
0
0
0
1
1
0
1
0
1
At the initial setting, the typical gain is set.
—
0
1
0
0
0
1
1
0
1
0
1
Handfree input gain = VOL9
Handset input gain = VOL8
—
—
Handfree input gain and handset Input
gain are set at a time.
1
0
0
1
1
0
1
0
1
Typical handset input gain (+12 dB)
–3 dB with respect to the typical gain
–6 dB with respect to the typical gain
–9 dB with respect to the typical gain
At the initial setting, the typical gain is set.
—
Gain control (receive PAD, speaker)
WRITE Mode
Address Data AD1 = 0, AD0 = 1
Control Data
Description for Control
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Typical speaker pre-amp. gain (0 dB)
Speaker pre-amp. gain = VOL5
Additional speaker gain = VOL6
-4 dB with respect to the typical gain
-8 dB with respect to the typical gain
-12 dB with respect to the typical gain
-16 dB with respect to the typical gain
Speaker pre-amp. gain and additional
speaker gain are set at a time.
—
—
1
-20 dB with respect to the typical gain At the initial setting, SW21-OFF and the
1
0
typical gain are set.
-24 dB with respect to the typical gain
-28 dB with respect to the typical gain
0
0
1
1
0
1
0
1
Typical additional speaker input path gain (0 dB)
-6 dB with respect to the typical gain
-12 dB with respect to the typical gain
-18 dB with respect to the typical gain
—
0
1
0
1
0
1
Speaker receive OFF(SW21 OFF)
0
0
0
0
0
0
Speaker receive ON (SW21 ON)
Typical receive PAD gain (0 dB)
0
0
1
1
Receive PAD = VOL10
-3 dB with respect to the typical gain
Incoming tone gain = VOL11, VOL12
—
-6 dB with respect to the typical gain
-9 dB with respect to the typical gain
Receive PAD and incoming tone gain are
set at a time.
1
1
0
0
0
1
0
1
0
Typical incoming tone gain (0 dB)
At the initial setting, the typical gain is set.
—
-10 dB with respect to the typical gain
-20 dB with respect to the typical gain
Key scanning signal output control
WRITE Mode
Address Data AD1 = 1, AD0 = 0
Controlo Data
Description for Control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
The data set on DB7 to DB0 are output on PO7 to PO0 respectively.
Output data is held until next data is written.
When the set data is set to "0", output data goes to "0", when set to "1", output pin is left open.
At the initial setting, PO7 to PO0 are in open state.
Output Data
Key scanning data read out
Read Mode
Address Data AD1 = 1, AD0 = 0
Contorol Data
Description for Control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0
Data input onto PI7 to PI0 are output onto DB7 to DB0.
Special functions
WRITE Mode
Address Data AD1 = 1, AD0 = 1
Contorol Data
Description for Control
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LCD Deflection Angle Control Voltage Output
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VLCD pin output voltage: 0.0 V
: 0.20 V
: 0.40 V
: 0.60 V
: 0.8 V
: 1.0 V
: 1.2 V
: 1.4 V
0
1
0
0
0
At the initial setting stage,
set to 0 V.
Power Down Mode Control
0
0
1
1
0
1
0
1
Analog, CODEC power down mode
Analog, CODEC power ON mode
CODEC power down mode
At the initial setting stage, set to
analog and CODEC power down
mode. CODEC power ON/OFF
control is valid in the analog and
CODEC power ON mode.
1
0
0
0
0
0
CODEC power ON mode
CODEC Control
At the initial setting stage, set to
m-law, and FHW and BHW
are normally connected.
The componding law and the
connection control are set at a
time.
0
1
CODEC operates in m-law
—
CODEC operates in A-law
1
1
0
0
0
0
0
1
FHW and BHW are normally connected
BHW is connected to FHW
—
*2: Even during the analog and CODEC power down mode, following functions are available,
Key scanning data I/O, sounder outputs (SA0), WDT, and general latch output (LA, LB)
¡ Semiconductor
MSM7503
APPLICATION CIRCUIT
S p e a k e r
H a n d s e t
38/41
MLDYI
TPAO TPBI MPAI
VOL 9
TO CAI
MPAO MPBI
MPBO
TPAI
CAO
AIN
+
–
–
–
SW1
SW2
SW7
SW16
0 dB
5.7 dB
VOL 3
VOL 4
20 dB
20 dB to +25 dB
+
CODEC
AOUT
+
VOL 8
PB GEN.
Per Wave
0.24 VPP(–21.4 dBV Equivalent)
R1I
R2I
–
VOL 10
CODEC I/O Level
Overload Point: 1.2 Vop
SW9
SW3
0 dB
RPO
RMI
R-Tone GEN.
90 mVPP Pulse (–27.8 dBV Equivalent)
0 dBmO
: 0.6007 Vrms
(–4.4 dBV)
VOL 1
VOL 2
VOL 7
–
F-Tone GEN.
0.16 VPP Pulse (–22.8 dBV Equivalent)
SW4
SW5
–
S-Tone GEN.
0.22 VPP Pulse (–20.0 dBV Equivalent)
SW13
SW17
SW14
SW5
RMO0
RMO1
–
8.7 dB
0 dB
VOL No. Typical Level Variable Range Step Width
0 dB
–6 dB
–9 dB
–2 dB
+4 dB
0 dB
–14 dB to 0 dB
–21 dB to –3 dB
–11 dB to –2 dB
–5 dB to +4 dB
–28 dB to 0 dB
2 dB
3 dB
3 dB
3 dB
4 dB
VOL 1
VOL 2
VOL 3
VOL 4
VOL 5
VOL 6
VOL 7
VOL 8
VOL 9
VOL 10
–
0 dB
SW6
SW8
–
3 dB
6.8 dB
VOL 6
SPO
–
VOL 5
VOL 12
VOL 11
SW21
SW20
SW11
SW15
–
6 dB
30 mV
3 dB
3,6 dB
3 dB
0 dB
0 dB
+12 dB
+20 dB
0 dB
–18 dB to 0 dB
90 mV to 180 mV
+3 dB to +12 dB
+11 dB to +20 dB
–9 dB to 0 dB
–
SW18
SW10
–22 dB
–20 dB to 0 dB
–20 dB to 0 dB
VOL 11
VOL 12
0 dB
0 dB
10 dB
10 dB
SPI
Note :
+
: The output signal is input with the same phase as
: The output signal is with inverted phase.
–
¡ Semiconductor
MSM7503
RECOMMENDATIONS FOR ACTUAL DESIGN
• To assure proper electrical characteristics, use bypass capacitors with excellent high frequency
characteristics for the power supply and keep them as close as possible to the VA and AG pins.
• Connect the AG pin and the DG pin each other as close as possible. Connected to the system
ground with low impedance. If the AG and DG of the device are connected to different ground
lines, the device may be latched up.
• Connect the VA pin and the VD pin as close together as possible and routed them to the analog
5 V power supply. If the VA and VD of the device are connected to different power supplies,
the device may be latched up.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an
IC socket is unavoidable, the short lead type socket is recommended.
• Whenmountedonaframe,electro-magneticshieldingshouldberecommended, ifanyelectro-
magnetic wave source such as power supply transformers is surrounding the device.
• Keep the voltage on the V pin not lower than –0.3 V even instantaneously to avoid latch-up
DD
phenomenon when turning the power on.
• Usealownoise(particularly,lowleveltypeofhighfrequencyspikenoiseorpulsenoise)power
supplyshouldbeusedtoavoidtheerroneousoperationandthedegradationofthecharacteristics
of these devices.
• Connect analog input pins and digital input pins that are not used to the SG pin and to GND,
respectively.
• When the data is written differently from the data defined in the section, Control Data
Description in Functional Description, the device is not guaranteed in normal operation.
40/41
¡ Semiconductor
MSM7503
PACKAGE DIMENSIONS
(Unit : mm)
QFP80-P-1420-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Epoxy resin
42 alloy
Solder plating
5 mm or more
Solder plate thickness
Package weight (g)
1.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
41/41
相关型号：
©2020 ICPDF网 联系我们和版权申明