MSM548331 [OKI]
222,720-Word x 12-Bit Field Memory; 222720字×12位字段存储
| 型号： | MSM548331 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 222,720-Word x 12-Bit Field Memory |
| 文件： | 总23页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2L0037-17-Y1
This version: Jan. 1998
Previous version: Dec. 1996
¡ Semiconductor
MSM548331
222,720-Word ¥ 12-Bit Field Memory
DESCRIPTION
The MSM548331 is a 2.7-Mbit, 768 bits ¥ 290 lines, Field Memory. Access is done line by line. The line
address must be set each time a line is changed.
More than two MSM548331s can be cascaded directly without any delay devices between them.
Cascading MSM548331s provides larger capacity and longer delay.
X serial address input enables random initial address setting of serial access in a page. Other than the
random address setting, MSM548331 has several types of address set modes such as line hold,
address jump to initial address and line increment.
SelfrefreshfunctionreleasestheMSM548331frombeingappliedexternalrefreshcontrolclockseven
though it contains dynamic type memory cells. MSM548331 has write mask function or input enable
function (IE), and read-data skipping function or output enable function (OE).
The MSM548331 is especially designed for digital TVs and VTRs for consumer use and video
cameras.
The MSM548331 is not designed for high end use in such applications as medical systems,
professional graphics systems which require long term picture storage, data storage systems and
others.
FEATURES
• 768 ¥ 290 ¥ 12-bit configuration
• Line by line access
• X serial address inputs for random serial initial bit address
• Asynchronous operation
• Serial read and write cycle times
Read cycle: 30 ns
Write cycle: 30 ns
• Low operating supply voltage: 3.3 V ±0.3 V
• Self-refresh
• Various address reset mode for picture processing
• Write mask function (Input enable control)
• Data skipping function (Output enable control)
• Package:
44-pin 400 mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM548331TS-K)
1/23
¡ Semiconductor
MSM548331
PIN CONFIGURATION (TOP VIEW)
VSS
1
44 DIN6
43 DIN7
42 DIN8
41 DIN9
40 DIN10
39 DIN11
38 WCLK
37 WXAD
36 WADE/RX
35 WR/TR
34 WE
DIN5 2
DIN4 3
DIN3 4
DIN2 5
DIN1 6
DIN0 7
RCLK 8
RXAD 9
RADE/RX 10
RR 11
RXINC 12
RE 13
33 WXINC
32 IE
OE 14
31 DO11
30 DO10
29 VCC
DO0 15
DO1 16
VCC 17
28 DO9
DO2 18
DO3 19
VSS 20
27 DO8
26 VSS
25 DO7
DO4 21
DO5 22
24 DO6
23 VCC
44-Pin Plastic TSOP (II)
(K Type)
2/23
¡ Semiconductor
MSM548331
Function
Pin Name
Address Setting Cycle
Serial Read/Write Cycle
Read Port, Serial Read Clock
RCLK
RE
Read Port, X Serial Address Strobes
—
Read Port, Read Enable
Read Port, Data Output
DO0 - 11
RR
—
Read Port, Address Reset Mode Enable
Read Port, X Address Increment
Read Port, X Address Input Enable
Read Port, X Address Reset
Read Port, X Serial Address Data
—
—
RXINC
—
—
—
RADE/RX
RXAD
OE
Output Enable
WCLK
WE
Write Port, X Serial Address Strobes
—
Write Port, Serial Write Clock
Write Port, Write Enable
Write Port, Input Data
Write Port, Write Data Transfer
—
DIN0 - 11
WR/TR
WXINC
—
Write Port, Address Reset Mode Enable
Write Port, X Address Increment
Write Port, X Address Input Enable
Write Port, X Address Reset
Write Port, X Serial Address Data
—
WADE/RX
—
WXAD
IE
—
Input Enable
VCC
VSS
Power Supply Voltage (3.3 V)
Ground (0 V)
Note: Same power supply voltage level must be provided to every V pin.
CC
Same ground voltage level must be provided to every V pin.
SS
3/23
WE
WCLK
IE
12
Refresh
Counter
Write Buffer
DIN0 to DIN11
WCLK
WADE/RX
WXAD
Write Register
WR/TR
WXINC
Memory Cell Array
768 ¥ 290 ¥ 12 bits
RCLK
RADE/RX
RXAD
RR
Read Register
DOUT Buffer
RXINC
12
DO0 to DO11
VBB
Generator
RCLK
RE
OE
¡ Semiconductor
MSM548331
PIN FUNCTION
READ RELATED
RCLK : Read Clock
RCLKisthereadcontrolclockinput. SynchronizedwithRCLK'srisingedge, serialreadaccessfrom
read ports is executed when both RE and OE are high.
The internal counter for the serial read address is incremented automatically on the rising edge of
RCLK. In a read address set cycle, all the read address bits which were input from RXAD pin are
stored into internal address registers synchronized with RCLK. In this address set cycle, RADE/RX
must be held high and RR must be held low.
In the read address reset cycle, various read address reset modes can be set synchronously with
RCLK. Theseresetcyclesworktoreplacecomplicatedserialaddresscontrolwhichrequiresmany
RCLKclockswithasimpleresetcyclecontrolrequiringonlyasingleRCLKcycle.Itgreatlyfacilitates
memory access.
RE : Read Enable
RE is a read enable clock input. RE enables or disables both internal read address pointers and data-
outbuffers.WhenREishigh,theinternalreadaddresspointerisincrementedsynchronouslywith
RCLK. When RE is low, even if the RCLK is input, the internal read address pointer is not
incremented.
OE : Output Enable
OE is an output enable clock input. OE enables or disables data-outs. OE high level enables the
outputs. TheinternalreadaddresspointerisalwaysincrementedbycyclingRCLKregardlessofOE
level.
DO0-11 : Data-Outs
DO0-11areserialdata-outs. DataisoutputsynchronouslywithRCLKwhenOEishigh. Theoutput
enable/disableoperationthroughOEinputisperformedsynchronouslywithOEandasynchronously
with RCLK.
RR : Read Reset
RR is a read reset control input. Read address reset modes are defined when RR level is high
according to the "FUNCTION TABLE for read".
RXINC : Read X Address Increment
RXINC is a read X address (or line address) increment control input. In the read address reset cycle,
definedbyRRhigh,theXaddress(orlineaddress)isincrementedby1whenRXINCispulledhigh
with RADE/RX low.
RADE/RX : Read Address Enable/Read X Address Reset Logic Function
RADE/RXisadualfunctioncontrolinput. RADE, oneofthetwofunctionsofRADE/RX, isaread
addressenableinput. Inthereadaddresssetcycle, definedbyRRhigh, Xaddress(orlineaddress)
input from the RXAD pin are latched into internal read X address register synchronously with RCLK.
RX, the second function of RADE/RX, works as an element to set read X address (or line address)
resetmode. Inanaddressresetmodecycle, definedbyRRhigh, readXaddressisresetto0when
RADE/RX is pulled high with RXINC low.
RXAD : Read X Address
RXAD is a read X address (or line address) input. RXAD specifies the line address. 9 bits of read X
address data are input serially from RXAD.
5/23
¡ Semiconductor
MSM548331
WRITE RELATED
WCLK : Write Clock
WCLKisawritecontrolclockinput. SynchronizedwithWCLK'srisingedge, serialwriteaccessinto
write ports is executed when WE is high and IE is high.
AccordingtoWCLKclocks,theinternalcounterfortheserialaddressisincrementedautomatically.
Inawriteaddresssetcycle, allthewriteaddresseswhichwereinputfromWXADarestoredinto
internal address registers synchronously with WCLK. In this address set cycle, WADE/RX must be
held high and WR/TR must be held low.
In the write address reset cycle, various write address reset modes can be set synchronously with
WCLK. These reset cycles replace complicated serial address control with simple reset cycle control
which requires only one WCLK cycle. It greatly facilitates memory access.
WE : Write Enable
WE is a write enable clock input. WE enables or disables both internal write address pointers and
data-inbuffers.WhenWEishigh,theinternalwriteaddresspointerisincrementedsynchronously
with WCLK. When WE is low, even if WCLK is input, the internal write address pointer is not
incremented.
DIN0-11 : Data-Ins
DIN0-11 are serial data-ins. Corresponding data-in-buffers are masked by IE.
WR/TR : Write Reset/Write Transfer
WR/TR is a write reset control input. Write address reset modes are defined when WR/TR level is
high according to the "FUNCTION TABLE for write".
When the write operation on a line is terminated, be sure to perform a write transfer operation by
WR/TR in order to store the written data in the write register to corresponding memory cells.
WXINC : Write X Address Increment
WXINCisawriteXaddress(orlineaddress)incrementcontrolinput.Inthewriteaddressresetcycle,
defined by WR/TR high, the write X address (or line address) is incremented when WXINC and
WADE/RX are high.
WADE/RX : Write Address Enable/Write X Address Reset Logic Function
WADE/RX is a dual functional control input. WADE, one of the two functions of WADE/RX, is a
write address enable input. In the write address reset cycle, defined by WR/TR high, X address (or
lineaddress)inputfromWXADislatchedintointernalwriteXaddressregistersynchronouslywith
WCLK.
WXAD : Write X Address
WXAD is a write X address (or line address) input. WXAD specifies line address. 9 bits of write X
address data are input serially from WXAD.
IE : Input Enable
IE is an input enable which controls the write operation. When IE is high, the input operation is
enabled. When IE is low, the write operation is masked. When WE signal is high, and IE low, the
internalserialwriteaddresspointerisincrementedontherisingedgeofWCLKwithoutactualwrite
operations. This function facilitates picture in picture function in a TV system.
6/23
¡ Semiconductor
MSM548331
OPERATION MODE
Write
1. Write operation
Before the write operation begins, X address (or line address) must be input to set the initial
bit address for the following serial write access. When WE and IE are high, a set of serial 12-
bit-widthwritedataonDIN0-11iswrittenintowriteregistersattachedtotheDRAMmemory
arrays temporarily on the rising edge of WCLK.
Following 12-bit-width serial input data is written into the memory locations in the write
register designated by an internal write address pointer which is advanced by WCLK. This
enablescontinuousserialwriteonaline. WhenwriteclockWCLKandreadclockRCLKare
tied together and are controlled by a common clock or CLK, more than two MSM548331s can
becascadeddirectlywithoutanydelaydevicesbetweentheMSM548331sbecausetheread
timing is delayed by one CLK cycle to the write timing. When the write operation on a line is
terminated, be sure to perform a write transfer operation by WR/TR in order to store the
writtendatainthewriteregisterstothecorrespondingmemorycellsintheDRAMmemory
arrays.
2. Write address pointer increment operation
The write address pointer is incremented synchronously with WCLK when WE is high.
Relationship between the WE and IE input levels,
Write Address pointer, and data input status
WCLK Rise
Internal Write
Address Pointer
Data Input
Inputted
WE
IE
H
H
H
L
Incremented
Stopped
L
Not Inputted
—
When WE and IE are high, the write operation is enabled.
IfIElevelgoeslowwhileWCLKisactive,thewriteoperationishaltedbutthewriteaddress
pointerwillcontinuetoadvance.Thatis,IEenablesawritemaskfunction.WhenWEgoes
low, the write address pointer stops without WCLK.
Read
1. Read operation
Before the read operation begins, the X address (or line address) must be input for setting
initial bit address for the following serial read access.
When both RE and OE are high, a set of serial 12-bit-width read data on DO0-11 pins is read
from read registers attached to DRAM memory arrays on the rising edge of RCLK.
Each access time is specified by the rising edges of RCLK.
7/23
¡ Semiconductor
MSM548331
2. Read address pointer increment operation
The read address pointer is incremented synchronized with RCLK when OE level is high.
Relationship between the RE and OE input levels,
Read Address pointer, and data output status
RCLK Rise
RE OE
Internal Read
Address Pointer
Data Output
H
H
Outputted
Hi-Z
Incremented
Stopped
H
L
L
L
H
L
Outputted
Hi-Z
When each read address pointer reaches the last address of a line, it stops at the last address
and no address increment occurs.
Initial Address Setting (Write/Read Independent)
Any read operations are prohibited in the read initial address set period. Similarly, any write
operationsareprohibitedinthewriteinitialaddresssetperiod.Notethatreadinitialaddresssetand
writeinitialaddresssetcanoccurindependently.Similarly,readaccesscanbeachievedindependently
from write initial address set period and write access can be achieved independently from read initial
address set cycles.
1. Write address setting
WADE/RX enables initial read address inputs. When WADE/RX is high, 9 bits of serial X
address (or line address) are input from WXAD.
Theoperationsaboveenableselectionofspecificlinesrandomlyandenablesthestartofserial
write access synchronized with write clock WCLK. Address for each line must be input
betweeneachlineaccess.Inotherwords,MSM548331'swriteisachievedina"linebyline"
manner. Any write operations are prohibited in the initial write address set periods.
Serialwriteinputenabletimet
mustbekeptforstartingaserialwritejustaftertheinitial
SWE
write address set period.
2. Read address setting
RADE/RX enables initial read address inputs.
When RADE/RX is high, 9 bits of serial X address (or line address) are input from RXAD.
Theoperationsaboveenableselectionofspecificlinesrandomlyandenablesthestartofserial
read access synchronized with read clocks, RCLK. Address for each line must be input
betweeneachlineaccess. Inotherwords, MSM548331'sreadoperationisachievedin"lineby
line" manner.
Any read operations are prohibited in the initial read address set periods. Serial read
operations are prohibited while RADE/RX is high. Serial read port enable time t
kept for starting a serial read just after the initial read address set period.
must be
SRE
Initial Address Reset Modes (Write/Read Independent)
Theinitialaddressresetmodesreplacecomplicatedreadorwriteinitialaddresssettingswithsimple
resetcycles.InitialaddressresetmodesareselectedbyRRhighduringreadandWR/TRhighduring
write. Asinnormalreadorwriteaddresssettings, anyreadoperationsareprohibitedintheread
addressresetcycles.Similarly,anywriteoperationsareprohibitedintheinitialwriteaddressreset
cycles.Notethatreadinitialaddressresetandwriteinitialaddressresetcanoccurindependently.
Similarly, read access can be achieved independently from write initial address reset cycles and write
8/23
¡ Semiconductor
MSM548331
access can be achieved independently from read initial address reset cycles.
Inputaddressesarestoredintoaddressregisterswhichareconnectedwithaddresscounterwhich
controls address pointer operation. In the serial access operation, the input address into the address
registers are kept.
Serial write data input enable time t
and serial read port read enable time t
must be kept for
SWE
SRE
starting serial read or write just after the initial read or write address reset cycles.
Refer to the "FUNCTION TABLE" shown later.
1. Line hold operation (read only)
By the "Line hold operation" logic which is composed by a combination of control inputs' level,
access is executed starting from the first word on the current line.
2. Original address reset operation
Bythe"Originaladdressreset"logic, theaddresscounterisresetto(0,0). Aftertheresetmode,
serial access starts from the address (0,0) .
The address counter is reset by this reset mode but the address register, which stored input
addressinthepreviousaddressresetcycleoraddresssetcycle,isnotreset.Thenon-initialized
address can be used as a preset address in "address jump reset" mode.
3. Line increment operation
By the "Line increment operation" logic, the X address counter is incremented by one from the
current X address. That is, serial access from the Y = (0) on the next line is enabled.
4. Address jump operation
Bythe"Addressjumpoperation"logic,ajumpmaybecausedtotheinitializedlineaddress.
Note :During one reset setting cycle, a plurality of resets cannot be set.
Power ON
PowermustbeappliedtoRCLK, RE, OE, WCLK, WEandIEinputsignalstopullthem"Low"before
or when the V supply is turned on.
CC
After power-up, the device is designed to begin proper operation in at least 200 ms after V has
CC
reachedthespecifiedvoltage. After200ms, aminimumofonelinedummywriteoperationandread
operation is required according to the address setting mode, because the read and write address
pointers are not valid after power-up.
New Data Read Access
In order to read out "new data', the delay between the beginning of a write address setting cycle and
read address setting cycle must be at least two lines.
Old Data Read Access
In order to read out "old data", the delay between the beginning of a write address setting cycle and
read address setting cycle must be more than 0 but less than a half line.
9/23
¡ Semiconductor
MSM548331
FUNCTION TABLE
1. Write
Description of
Operation
Mode
No.
WR/TR WXINC WADE/RX Internal Address Pointer
1
Write Transfer
Reset
H
H
H
H
L
L
L
L
H
L
2
3
X address cleared to (0, 0)
Address Reset
Mode
X address increment to (Xn +
1, 0)
Line Increment
Address Jump
First Address Setting
H
H
L
4
H
H
X address jump to (Xi, 0)
X address set
Address Setting
Mode
—
Note :For write, Line hold is not provided.
2. Read
Description of
Operation
Mode
No.
RR
RXINC RADE/RX Internal Address Pointer
1
Line Hold
H
L
L
L
H
L
X address holde to (Xn, 0)
X address cleared to (0, 0)
2
3
Reset
H
H
H
L
Address Reset
Mode
X address increment to (Xn +
1, 0)
Line Increment
Adress Jump
First Address Setting
H
H
L
4
H
H
X address jump to (Xi, 0)
X address set
Address Setting
Mode
—
10/23
¡ Semiconductor
MSM548331
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Pin Voltage
Symbol
VT
Condition
Rating
Ta = 25°C, with respect to VSS
–0.5 to 4.6 V
50 mA
Short Circuit Output Current
Power Dissipation
IOS
Ta = 25°C
Ta = 25°C
—
PD
1 W
Operating Temperature
Storage Temperature
Topr
Tstg
0 to 70°C
–55 to 150°C
—
Recommended Operating Conditions
(Ta = 0 to 70°C)
Parameter
Power Supply Voltage
Power Supply Voltage
"H" Input Voltage
Symbol
VCC
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
Unit
V
V
V
V
VSS
0
VIH
2.1
–0.5
VCC
0
V
CC + 0.3
0.8
"L" Input Voltage
VIL
DC Characteristics
(VCC = 3.0 to 3.6 V, Ta = 0 to 70°C)
Parameter
"H" Output Voltage
"L" Output Voltage
Symbol
VOH
Condition
Min.
2.2
Max.
—
Unit
V
IOH = –0.1 mA
IOL = 0.1 mA
0 < VI < VCC
VOL
—
0.6
V
Input Leakage Current
ILI
ILO
–10
–10
—
10
10
50
mA
mA
mA
Other input voltage 0 V
0 < VO < VCC
Output Leakage Current
Power Supply Current
(During Operation)
ICC1
min. cycle
-50
Power Supply Voltage
(During Standby)
ICC2
Input pin = VIL/VIH
—
10
mA
Capacitance
(Ta = 25°C, f = 1 MHz)
Parameter
Input Capacitance
Symbol
Max.
Unit
pF
CI
7
7
Output Capacitance
CO
pF
11/23
¡ Semiconductor
MSM548331
AC Characteristics (1/2)
Measurement Conditions: (VCC = 3.3 V 0.3 V, Ta = 0 to 70°C)
Parameter
Symbol
tWCLK
tWWCLH
tWWCLL
tWAS
Min.
30
13
13
5
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WCLK Cycle Time
WCLK "H" Pulse Width
WCLK "L" Pulse Width
Serial Write Address Input Active Setup Time
Serial Write Address Input Active Hold Time
Serial Write Address Input Inactive Hold Time
Serial Write Address Input Inactive Setup Time
Write Transfer Instruction Setup Time
Write Transfer Instruction Hold Time
Write Transfer Instruction Inactive Hold Time
Write Transfer Instruction Inactive Setup Time
Serial Write X Address Setup Time
Serial Write X Address Hold Time
Serial Write Data Input Enable Time
Write Instruction Setup Time
tWAH
7
tWADH
tWADS
tWTRS
tWTRH
tWTDH
tWTDS
tWXAS
tWXAH
tSWE
7
7
5
7
7
7
5
7
3000
5
tWES
Write Instruction Hold Time
tWEH
7
Write Instruction Inactive Hold Time
Write Instruction Inactive Setup Time
Input Data Setup Time
tWEDH
tWEDS
tDS
7
7
5
Input Data Hold Time
tDH
12
5
WR/TR-WCLK Active Setup Time
WR/TR-WCLK Active Hold Time
WR/TR-WCLK Inactive Hold Time
WR/TR-WCLK Inactive Setup Time
WXINC-WCLK Active Setup Time
WXINC-WCLK Active Hold Time
WXINC-WCLK Inactive Hold Time
WXINC-WCLK Inactive Setup Time
WADE/RX-WCLK Active Setup Time
WADE/RX-WCLK Active Hold Time
WADE/RX-WCLK Inactive Hold Time
WADE/RX-WCLK Inactive Setup Time
IE Enable Setup Time
tWRS
tWRH
7
tWRDH
tWRDS
tWINS
tWINH
tWINDH
tWINDS
tWRXS
tWRXH
tWRXDH
tWRXDS
tIES
7
7
5
7
7
7
5
7
7
7
5
IE Enable Hold Time
tIEH
7
IE Disable Setup Time
tIEDS
7
IE Disable Hold Time
tIEDH
7
12/23
¡ Semiconductor
MSM548331
AC Characteristics (2/2)
Measurement Conditions: (VCC = 3.3 V 0.3 V, Ta = 0 to 70°C)
Parameter
Symbol
tRCLK
tWRCLH
tWRCLL
tRAS
Min.
30
13
13
5
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30
—
20
—
—
—
—
—
—
—
—
—
—
—
—
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RCLK Cycle Time
RCLK "H" Pulse Width
RCLK "L" Pulse Width
Serial Read Address Input Active Setup Time
Serial Read Address Input Active Hold Time
Serial Read Address Input Inactive Hold Time
Serial Read Address Input Inactive Setup Time
Serial Read X Address Setup Time
Serial Read X Address Hold Time
RE Enable Setup Time
tRAH
7
tRADH
tRADS
tRXAS
tRXAH
tRES
7
7
5
7
5
RE Enable Hold Time
tREH
7
RE Disable Hold Time
tREDH
tREDS
tSRE
7
RE Disable Setup Time
7
Read Port Read Enable Time
Read Port Read Data Hold Time
Access Time from RCLK
3000
12
—
2
tOH
tAC
Read Data Hold Time from OE
Access Time from OE
tDDOE
tDEOE
tRRS
—
5
RR-RCLK Active Setup Time
RR-RCLK Active Hold Time
tRRH
7
RR-RCLK Inactive Hold Time
RR-RCLK Inactive Setup Time
RXINC-RCLK Active Setup Time
RXINC-RCLK Active Hold Time
RXINC-RCLK Inactive Hold Time
RXINC-RCLK Inactive Setup Time
RADE/RX-RCLK Active Setup Time
RADE/RX-RCLK Active Hold Time
RADE/RX-RCLK Inactive Setup Time
RADE/RX-RCLK Inactive Hold Time
Transition Time (Rise and Fall)
tRRDH
tRRDS
tRINS
tRINH
tRINDH
tRINDS
tRRXS
tRRXH
tRRXDS
tRRXDH
tT
7
7
5
7
7
7
5
7
7
7
2
Note :
Measurement conditions
Input pulse level
: V = 2.1 V, V = 0.8 V
IH
IL
Input timing reference level
: V = 2.1 V, V = 0.8 V
IH IL
Output timing reference level : V
= 2.2 V, V = 0.6 V
OH
OL
Input rise/fall time
Load condition
: 2 ns
:CL=30pF(Oscilloscopeandtoolcapacityincluded)
13/23
tWCLK
tWWCLL
—
—
WCLK
WADE/RX
WXAD
WE
tWWCLH
tWADH
tWXAS
tWAH tWADS
tWAS
—
—
tWXAS
tWXAS
tWXAS
tWXAH
tWXAH
tWXAH
tWXAH
—
—
Valid
A8
Valid
Valid
Valid
A7
A1
A0
tWEDH
tWES
tSWE
—
—
tIES
tIEDH
—
—
IE
—
—
WR/TR
WXINC
Low
Low
—
—
tDS
tDS
Valid
tDH
tDH
—
—
Valid
DIN0 - 11
¡ Semiconductor
MSM548331
Write Cycle (WE Control)
tWCLK
(N-2)CYCLE (N-1)CYCLE N CYCLE
(N+1) CYCLE (N+2) CYCLE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WCLK
WADE/RX
IE
Low
High
Low
Low
WR/TR
WXINC
tWEH tWEDS tWEDH tWES
WE
Valid
Valid
Valid
D(N-1)
Valid
D(N)
Valid
Valid
DIN0 - 11
D(N-3)
D(N-2)
D(N+1)
D(N+2)
Note : IntheWE="L"cycle,thewriteaddresspointerisnotincrementedandnoDINdataiswritten.
Write Cycle (IE Control)
tWCLK
(N-2)CYCLE (N-1)CYCLE N CYCLE
(N+2) CYCLE (N+3) CYCLE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WCLK
WADE/RX
WE
Low
High
Low
Low
WR/TR
WXINC
tIEH tIEDS tIEDH tIES
IE
Valid
Valid
Valid
D(N-1)
Valid
D(N)
Valid
Valid
D(N+3)
DIN0 - 11
D(N-3)
D(N-2)
D(N+2)
Note : IntheIE="L"cycle,thewriteaddresspointerisincremented,thoughnoDINdataiswritten
and the memory data is held.
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¡ Semiconductor
MSM548331
Write Cycle (Write Transfer)
tWCLK
(N-2)CYCLE (N-1)CYCLE
N CYCLE
—
—
—
—
—
—
—
—
—
—
—
—
WCLK
WADE/RX
WR/TR
WXINC
WE
Low
Low
tWTRS tWTRH
tWTDH tWTDS
tWEH tWEDS
Valid
Valid
Valid
D(N-1)
Valid
D(N)
DIN0 - 11
D(N-3)
D(N-2)
Note :Whenfinishingthewriteoperationonaline, besuretoperformawritetransferoperation
because the write data on the line is stored in the memory cell.
16/23
tRCLK
tWRCLL
—
—
RCLK
RADE/RX
RXAD
RE
tWRCLH
tRAH tRADS
tRAS
—
—
tRADH
tRXAS
tRXAS
tRXAS
tRXAS
tRXAH
tRXAH
tRXAH
tRXAH
—
—
Valid
B8
Valid
Valid
Valid
B7
B1
B0
tREDH
tRES
tSRE
—
—
—
—
RR
Low
Low
—
—
RXINC
tAC
tOH
High-Z
—
—
Valid
Valid
DO0 - 11
¡ Semiconductor
MSM548331
Read Cycle (RE Control)
tRCLK
(N-2)CYCLE (N-1)CYCLE
N CYCLE
(N+1) CYCLE (N+2) CYCLE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RCLK
RADE/RX
RR
Low
Low
Low
RXINC
tREH tREDS tREDH tRES
RE
tOH
tAC
Valid
Valid
Valid
D(N-1)
Valid
D(N)
Valid
Valid
DO0 - 11
D(N-3)
D(N-2)
D(N+1)
D(N+2)
OE
High
Note :InthecycleofRE="L",thereadaddresspointerisnotincrementedandthedataattheaddress
is output continuously.
Read Cycle (OE Control)
tRCLK
(N-2)CYCLE (N-1)CYCLE
N CYCLE
(N+2) CYCLE (N+3) CYCLE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RCLK
RADE/RX
RR
Low
Low
Low
RXINC
OE
tOH
tDDOE
tDEOE tAC
High-Z
Valid
D(N-3)
Valid
Valid
D(N-1)
Valid
D(N)
Valid
Valid
DO0 - 11
D(N-2)
D(N+2)
D(N+3)
RE
High
Note : InthecycleofOE="L",thereadaddresspointerisincrementedandtheoutputentersthehigh
impedance state.
18/23
¡ Semiconductor
MSM548331
Write Reset Mode
tWCLK
tWWCLL
—
—
—
—
—
—
—
—
—
—
—
—
WCLK
tWWCLH
tWRXDH
tWRXH
tWRXS
tWRXDS
WADE/RX
WR/TR
WXINC
WE
tWRS tWRH
tWRDH
tWRDS
Low
tWES
tWEDH
tSWE
tDS
tDS
tDH
tDH
DIN0 - 11
Valid
Valid
Note :Both the line address and word address are reset to 0.
Write Line Increment Mode
tWCLK
tWWCLL
—
WCLK
—
—
—
—
—
—
—
tWWCLH
WADE/RX
WR/TR
tWRH
tWRS
tWRDH
tWRDS
tWINS tWINH
tWINDH
tWINDS
WXINC
tWES
tWEDH
—
—
—
—
tSWE
WE
tDS
tDS
tDH
tDH
DIN0 - 11
Valid
Valid
Note :The line address is incremented by 1 and the word address is reset to 0.
19/23
¡ Semiconductor
MSM548331
Write Address Jump Mode
tWCLK
tWWCLL
—
WCLK
—
—
tWWCLH
tWRXH
tWRXS
tWRXDH
tWRXDS
WADE/RX
WR/TR
—
—
tWRH
tWRS
tWRDH
tWRDS
—
—
—
—
—
—
—
tWINS tWINH
tWINDH
tWINDS
WXINC
WE
tWES
tWEDH
tSWE
tDS
tDS
tDH
tDH
DIN0 - 11
Valid
Valid
Note :The line address is reset to the initialized addresses and the word address is reset to 0.
20/23
¡ Semiconductor
MSM548331
Read Line Hold Mode
tRCLK
tWRCLL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RCLK
RADE/RX
RR
tWRCLH
Low
Low
tRRS tRRH
tRRDH
tRRDS
RXINC
RE
tRES
tREDH
tSRE
tAC
tOH
DO0 - 11
OE
Valid
Valid
High
Note :The line address is held and the word address is reset to 0.
Read Reset Mode
tRCLK
tWRCLL
—
RCLK
—
—
—
—
—
—
—
—
—
—
—
—
—
tWRCLH
tRRXH
tRRXS
tRRXDH
tRRXDS
RADE/RX
RR
tRRS tRRH
tRRDH
tRRDS
RXINC
RE
Low
tRES
tREDH
tSRE
tAC
tOH
DO0 - 11
OE
Valid
Valid
High
Note :Both the line address and word address are reset to 0.
21/23
¡ Semiconductor
MSM548331
Read Line Increment Mode
tRCLK
tWRCLL
—
RCLK
—
—
—
—
—
—
—
—
—
—
—
—
—
tWRCLH
RADE/RX
RR
Low
tRRH
tRRS
tRRDH
tRRDS
tRINS tRINH
tRINDH
tRINDS
RXINC
RE
tRES
tREDH
tSRE
tAC
tOH
DO0 - 11
OE
Valid
Valid
High
Note :The line address is incremented by 1 and the word address is reset to 0.
Read Address Jump Mode
tRCLK
tWRCLL
—
RCLK
—
—
—
—
—
—
—
—
—
—
—
—
—
tWRCLH
tRRXH
tRRXS
tRRXDH
tRRXDS
RADE/RX
RR
tRRH
tRRS
tRRDH
tRRDS
tRINS tRINH
tRINDH
tRINDS
RXINC
RE
tRES
tREDH
tSRE
tAC
tOH
DO0 - 11
OE
Valid
Valid
High
Note :The line address is reset to the initialized addresses and the word address is reset to 0.
22/23
¡ Semiconductor
PACKAGE DIMENSIONS
TSOPII44-P-400-0.80-K
MSM548331
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.54 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
23/23
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