MSM548512L [OKI]
524,288-Word X 8-Bit High-Speed PSRAM; 524,288字×8位高速PSRAM
| 型号： | MSM548512L |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 524,288-Word X 8-Bit High-Speed PSRAM |
| 文件： | 总12页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2L0044-17-Y1
This version: Jan. 1998
Previous version: Dec. 1996
¡ Semiconductor
MSM548512L
524,288-Word ¥ 8-Bit High-Speed PSRAM
DESCRIPTION
TheMSM548512LisfabricatedusingOKI’sCMOSsilicongateprocesstechnology. Thisprocess,
coupledwithsingle-transistermemorystoragecells,permitsmaximumcircuitdensity,minimum
chip size and high speed.
MSM548512L has Self-refresh mode in addition to Address-refresh mode and Auto-refresh
mode. In the Self-refresh mode the internal refresh timer and address counter refresh the
dynamic memory cells automatically. This series allows low power consumption when using
standby mode with Self-refresh.
The MSM548512L also features a static RAM-like write function that writes the data into the
memory cell at the rising edge of WE.
FEATURES
• Large capacity
• Fast access time
• Low power
:
:
:
:
:
:
:
:
4-Mbit (524,288-word ¥ 8 bits)
80 ns max.
200 µA max. (standby with Self-refresh)
Self refresh
SRAM WE pin, no address multiplex
5 V ±10%
2048 cycle/32 ms auto-address refresh
SRAM standard package
• Refresh free
• Logic compatible
• Single power supply
• Refresh
• Package compatible
• Package options:
32-pin 600 mil plastic DIP
32-pin 525 mil plastic SOP
(DIP32-P-600-2.54)
(SOP32-P-525-1.27-K) (Product : MSM548512L-xxGS-K)
xx indicates speed rank.
(Product : MSM548512L-xxRS)
PRODUCT FAMILY
Access Time (Max.)
Family
MSM548512L-80RS
MSM548512L-10RS
MSM548512L-12RS
MSM548512L-80GS-K
MSM548512L-10GS-K
MSM548512L-12GS-K
Package
80 ns
100 ns
120 ns
80 ns
600 mil 32-pin
Plastic DIP
525 mil 32-pin
Plastic SOP
100 ns
120 ns
1/12
¡ Semiconductor
MSM548512L
PIN CONFIGURATION (TOP VIEW)
A18
A16
A14
A12
A7
1
2
3
4
5
6
7
8
9
32 VCC
31 A15
30 A17
29 WE
28 A13
27 A8
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A14
A12
A7
VCC
A15
3
A17
A6
4
WE
A13
A5
26 A9
5
6
A6
A8
A4
25 A11
24 OE/RFSH
23 A10
22 CE
7
A5
A9
A3
8
A4
A11
9
A2 10
A1 11
A3
OE/RFSH
A10
10
11
12
13
14
15
16
A2
A1
CE
A0 12
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
A0
I/O7
I/O6
I/O5
I/O4
I/O3
I/O0
I/O1
I/O2
VSS
I/O0 13
I/O1 14
I/O2 15
VSS 16
32-Pin Plastic DIP
32-Pin Plastic SOP
Pin Name
A0 - A18
I/O0 - I/O7
CE
Function
Address Input
Data Input/Output
Chip Enable Input
OE/RFSH
WE
Output Enable / Refresh Input
Write Enable Input
VCC
Power Voltage (5 V)
Ground (0 V)
VSS
2/12
¡ Semiconductor
MSM548512L
BLOCK DIAGRAM
A0
Address
Latch
Control
Row
Decoder
Memory Matrix
(2048 ¥ 256) ¥ 8
A10
I/O0
I/O7
Column I/O
Input
Data
Control
Column Decoder
Address Latch Control
A11
A18
Refresh
Control
CE
Timing Pulse Generator
Read/Write Control
OE/RFSH
WE
3/12
¡ Semiconductor
MSM548512L
FUNCTION TABLE
CE
L
OE/RFSH
WE
H
I/O Pin
Low-Z
High-Z
High-Z
High-Z
High-Z
Mode
Read
L
X
H
L
L
L
Write
L
H
—
H
X
Refresh
Standby
H
H
X
L : Low Level Input
H : High Level Input
X : Don’t Care
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
V
Voltage on Any Pin from VSS *1
Power Dissipation
VT
PD
–1.0 to 7.0
1.0
W
Topr
Tstg
Operating Temperature
Storage Temperature
0 to 70
–55 to 125
–10 to 85
50
°C
°C
Tbias
IOS
Storage Temperature (biased)
Short Circuit Output Current
°C
mA
*1
To V
SS
Note:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to the conditions as detailed
in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Power Supply Voltage
Symbol
Min.
4.5
0
Typ.
5.0
0
Max.
5.5
0
Unit
VCC
VSS
VIH
VIL
V
V
V
V
2.4
–0.5
—
6.0
0.8
Input Voltage
—
4/12
¡ Semiconductor
MSM548512L
DC Characteristics
(VCC = 5 V 10ꢀ, VSS = 0 V, Ta = 0°C to 70°C)
Parameter
Symbol Min. Typ. Max. Unit
Condition
I
I/O = Open, tcyc = min.
Operating Current
ICC1
—
50
75
mA
CE = VIH, OE/RFSH = VIH,
VIN ≥ 0 V
ISB1
—
1
2
mA
Standby Current
CE ≥ VCC – 0.2 V, VIN ≥ 0 V,
OE/RFSH ≥ VCC – 0.2 V
CE = VIH, OE/RFSH = VIL,
VIN ≥ 0 V
ISB2
ICC2
ICC3
—
—
—
100
1
200
2
mA
mA
mA
Self Refresh Current
CE ≥ VCC – 0.2 V, VIN ≥ 0 V,
OE/RFSH £ 0.2 V
100
200
Input Leakage Current
Output Leakage Current
Output Low Level
ILI
–10
–10
—
—
—
—
—
10
10
0.4
—
mA
mA
V
VCC = 5.5 V, VIN = VSS to VCC
OE/RFSH = VIH, VI/O = VSS to VCC
IOL = 2.1 mA
ILO
VOL
VOH
Output High Level
2.4
V
IOH = –1 mA
Capacitance
Parameter
Input Capacitance
I/O Pin Capacitance
Symbol
CIN
Min.
—
Typ.
—
Max.
8
Unit
pF
Condition
VIN = 0 V
CI/O
—
—
10
pF
VI/O = 0 V
Note:
This parameter is periodically sampled and is not 100% tested.
5/12
¡ Semiconductor
MSM548512L
AC Characteristics
Measurement condition:
Input pulse level ........................... V = 2.4 V, V = 0.4 V
IH IL
Output reference level.................. V
= 2.0 V, V = 0.8 V
OH
OL
Rising and falling time................. 5 ns
Output load .................................... 1 TTL + 100 pF
Input timing reference level........ High = 2.2 V, Low = 0.8 V
(VCC = 5 V 10ꢀ, Ta = 0°C to 70°C)
MSM548512L MSM548512L MSM548512L
-80
-10
-12
Parameter
Symbol
Unit Note
Min.
160
220
—
—
—
20
—
0
Max.
—
—
80
30
25
—
25
—
10m
—
—
—
—
—
—
—
—
—
—
—
—
20
50
—
—
8m
—
—
Min. Max.
Min. Max.
tRC
tRWC
tCEA
tOEA
tCHZ
tCLZ
tOHZ
tOLZ
tCE
Random Read Write Cycle Time
Random Read Modify Write Cycle Time
CE Access Time
180
240
—
—
—
20
—
0
—
—
100
30
30
—
25
—
10m
—
—
—
—
—
—
—
—
—
—
—
—
25
50
—
—
8m
—
—
210
280
—
—
—
20
—
0
—
—
120
50
30
—
30
—
10m
—
—
—
—
—
—
—
—
—
—
—
—
30
50
—
—
8m
—
—
ns
ns
ns
ns
OE Access Time
Chip Disable to Output in High-Z
CE to Output in Low-Z
OE Disable to Output in High-Z
OE Output in Low-Z
ns
ns
ns
ns
s
6
6
CE Pulse Width
80n
70
0
100n
70
0
120n
80
0
tP
CE Precharge Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAS
Address Set-up Time
tAH
Address Hold Time
20
0
25
0
30
0
tRCS
tRCH
tOHC
tOCD
tWP
tCW
tDW
tDH
Read Command Set-up Time
Read Command Hold Time
OE Command Hold Time
OE Delay Time
0
0
0
15
0
15
0
15
0
Write Command Pulse Width
Chip Enable Time
25
80
20
0
35
120
30
0
30
100
25
0
Input Data Set Time
Input Data Hold Time
tOW
tWHZ
tT
Output Active from End of Write
Write Enable to Output in High-Z
Transition Time
5
5
5
—
3
—
3
—
3
6
ns 11
tRFD
tFP
tFAP
tFC
RFSH Delay Time from CE
RFSH Precharge Time
70
40
80n
160
8
70
40
80n
180
8
80
40
80n
210
8
ns
ns
s
RFSH Pulse Width (Auto-refresh)
Auto-refresh Cycle Time
RFSH Pulse Width (Self-refresh)
ns
ms
tFAS
CE Delay Time from RFSH
tRFS
tREF
600
—
—
32
600
—
—
32
600
—
—
32
ns
in Self-refresh Mode
Refresh Period (2048 cycle/32 ms)
ms
6/12
¡ Semiconductor
MSM548512L
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device.
2. All voltages are referenced to ground.
3. I
depends on output loading. Specified values are obtained with the output
CC1
open.
4. An initial pause of 100 µs is required after power-up followed by more than 8
initial cycles before proper device operation is achieved.
5. AC measurements assume t = 5 ns.
T
6. t
, t
and t
define the time at which the output achieves the open circuit
CHZ WHZ
OHZ
condition and is not referenced to output voltage levels.
7. In write cycles, the input data is latched at the earlier rising point of either CE
or WE. Write operation is achieved when both CE and WE are low.
8. The I/O state remains at high impedance after CE goes low if the transition occurs
at the same time as or after the falling edge of WE.
9. Use WE or OE or both signals to disable the output before input data is applied
during a write cycle when the input is not the same.
10. Data input must be set to floating state before I/O becomes low impedance by
WE or OE or both.
11. V (Min.) and V (Max.) are input timing reference levels for measurement. The
IH
IL
transition time is measured between V and V
.
IL
IH
12. 2048-cycle refresh must be applied within 15 µs after the end of self refreshing
to satisfy 2048 cycles/32 ms.
7/12
¡ Semiconductor
MSM548512L
TIMING WAVEFORM
Read Cycle
tRC
tCE
tP
CE
tAS
tAH
Address
A0 - A18
tRCS
tRCH
WE
tCEA
tOHC
OE/RSFH
tOEA
tCHZ
tOLZ
tOHZ
DOUT
Valid Data-out
"H" or "L"
Write Cycle 1 (OE High)
tRC
tCE
tP
CE
tAS
tAH
Address
A0 - A18
tCW
tWP
WE
OE/RFSH
tOCD
tDW
tDH
DIN
Valid Data-in
tWHZ
tOLZ
tCHZ
tOHZ
tCLZ
tOW
DOUT
"H" or "L"
8/12
¡ Semiconductor
Write Cycle 2 (OE Low)
CE
MSM548512L
tRC
tCE
tP
tAS
tAH
Address
A0 - A18
tCW
tWP
WE
tOHC
OE/RFSH
tDW
tDH
DIN
Valid Data-in
tWHZ
tCLZ
DOUT
"H" or "L"
Read Modify Write
tRWC
tP
CE
tAS
tAH
Address
A0 - A18
tCW
tRCH
tRCS
tWP
WE
tOCD
tOHC
OE/RFSH
tOHZ
tOEA
tOLZ
tDW
Valid Data-in
tDH
DIN
tCHZ
tWHZ
tOW
tCLZ
Valid
DOUT
Data-out
"H" or "L"
9/12
¡ Semiconductor
MSM548512L
Auto Refresh Cycle
tRFD
tFC
tFC
tFAP
CE
tFP
tFAP
tFP
OE/RFSH
"H" or "L"
Self Refresh Cycle
tRFD
CE
tRFS
tFP
tFAS
OE/RFSH
"H" or "L"
10/12
¡ Semiconductor
PACKAGE DIMENSIONS
DIP32-P-600-2.54
MSM548512L
(Unit : mm)
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
4.70 TYP.
11/12
¡ Semiconductor
MSM548512L
(Unit : mm)
SOP32-P-525-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.32 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
12/12
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