ML2110TC_技术文档

FEDL2110-01

Issue Date: Mar. 25, 2002

OKI Semiconductor

ML2110

Speech Control Processor

GENERAL DESCRIPTION

The ML2110 is a speech processor LSI device with internal D/A converter. It is optimized for text-to-speech

synthesis.

FEATURES

• Parallel and serial interfaces

• Single 3.3V power supply

• 5V interface available

• Internal 12bit D/A Converter

• Package:

144-pin plastic LQFP (LQFP144-P-2020-0.50-K) (ML2110TC)

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FEDL2110-01

OKI Semiconductor

ML2110

BLOCK DIAGRAM

CLK

CLKENA

RAM1KNB

PLL

TST

CLKEDBL

CLKA

CLKB

A23-0

D31-0

TSTM2-0

EXTINT1-0

ROM

SRAM

RD

BR3

CPU

BGT3

PD7-0

WR0-3

AS

PACK

PSTB

PCS

PIO

PIOA

PIBF

POBF

MFU32

RST

TMR

RAS

STBY

CAS3-0

WE

DRAMC

TXD

RXD

UPORT1-0

DOUT

DTR

DSR

RTS

USR

DAC

XSYNC

BCLK

SIO

CTS

DAO

SCLK

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FEDL2110-01

OKI Semiconductor

ML2110

PIN CONFIGURATION (TOP VIEW)

D25

D26

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

PIBF

PD7

PD6

PD5

PD4

PD3

V_DD

PD2

PD1

PD0

SCLK

D27

D28

D29

D30

GND

D31

A0

A1

A2

A3

A4

V_DD

A5

A6

A7

A8

A9

A10

GND

DTR

DSR

GND

RTS

CTS

RXD

TXD

CLKFDBL

CLKB

V_DD

CLKA

CLKENA

XO

17

16

15

14

13

12

11

10

9

8

7

6

5

A11

A12

A13

A14

A15

A16

V_DD

CLK

RST

STBY

GND

V_DD

A17

A18

A19

A20

A21

A22

A23

GND

V_DD

DAO

GND

4

3

2

1

144-PIN Plastic LQFP

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FEDL2110-01

OKI Semiconductor

ML2110

PIN DESCRIPTIONS

Symbol

D 31-0

I/O

Description

32-bit data bus. 8-bit devices are accessed through D31-24. 16-bit devices

are accessed through D31-D16.

I/O

O

A23-0

24-bit address bus. DRAM addresses are output from A13-0.

ROM select signal. ROM indicates that ROM space is assigned to the

O

ROM

specified address. It is used as a chip select signal.

SRAM select signal. SRAM indicates that SRAM space is assigned to the

O

SRAM

RD

specified address. It is used as a chip select signal.

Read signal. RD is active during both 8-bit and 16-bit reads.

Write signals. WR0 corresponds to writes from D31-24, WR1 corresponds to

writes from D23-16, WR2 corresponds to writes from D15-8, and WR3

corresponds to writes from D7-0.

O

WR0-3

RAS

Row address strobe.

Column address strobe. CAS0 corresponds to accesses from D31-24,CAS1

corresponds to accesses from D23-16, CAS2 corresponds to accesses from

D15-8, and CAS3 corresponds to accesses from D7-0.

Write enable. WE is active during writes to DRAM space as the DRAM write

signal.

CAS0-3

O

WE

O

Address strobe.

AS

TXD

O

Serial data output.

RXD

DTR

I

Serial data input.

O

Control signal indicating SIO can transmit and receive.

Input signal indicating that modem is in operable state.

SIO transmit request signal.

I

DSR

RTS

O

I

Input signal indicating that modem can transmit.

Synchronous transfer clock output.

CTS

SCLK

PD7-0

PACK

PSTB

PCS

O

I/O

Parallel port data input/output.

I

Parallel port read signal. Set high for Centronics interface.

Parallel port write signal. Strobe signal for Centronics interface.

Parallel port chip select signal.

I

PIOA

POBF

I

Parallel port address signal. Selects data or status during an access.

Output port buffer full. Indicates that data has been set in the output buffer.

3-state

Input port buffer full. Indicates that there is data in the input buffer.

Busy output signal for Centronics interface.

PIBF

O

I

General flag output signal.

Synchronous transmit clock.

Shift clock for DOUT.

UPORT1-0

XSYNC

BCLK

I

DOUT

O

Digital signal output.

DAO

D/A Converter output.

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ML2110

Symbol

CLK

I/O

I

Description

Clock input signal.

XO

O

I

Clock signal. Inverse of CLK.

Internal clock signal.

CLKA

CLKB

Internal clock signal. Inverse of CLK.

Clock change signal.

CLKENA

CLKFDBL

RST

I

Clock cycle change signal.

Reset input.

I

Standby signal. STBY suspends operation and places ML2110 in a standby

I

STBY

state.

I

I/O

I

External interrupt signal.

EXTINT1-0

WAIT

Wait signal. Normally, it is pulled up ‘H’ level.

Cache/BIU test signal.

BR3

BGT3

O

I

Cache/BIU test signal.

MD

16/32 bit select signal.

TSTM2-0

I

Test mode select input signal.

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ML2110

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

Input Voltage

Symbol

V_DD

V_in

Condition

Ta = 25

—

Rating

Unit

V

–0.3 to 4.5

–0.3 to 5.5

–55 to 125

Storage Temperature

T_stg

°C

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage

Operating Temperature

Symbol

V_DD

T_op

Condition

Rating

3.0 to 3.6

–40 to 85

Unit

V

°C

—

ELECTRICAL CHARACTERISTICS

DC Characteristics

(V_DD= 3.0 to 3.6 V, Ta = –40 to 85°C)

Parameter

"H" Input Voltage

"L" Input Voltage

Symbol

V_IH

V_IL

Condition

Excluding CLK

Min.

2.2

—

Typ.

—

Max.

—

Unit

V

—

0.8

V

"H" Input Voltage

V_IH

V_IL

V_OH

V_OL

I_LI

CLK

0.8 V_DD

—

0.2 V_DD

—

V

"L" Input Voltage

CLK

"H" Output Voltage

"L" Output Voltage

Input Leakage Current

Output Leakage Current

I_OH= –4 mA

I_OL= 4 mA

0 < V_IN< V_DD

2.4

V

—

0.4

V

–10

+10

µA

I_LO

0 < V_OUT< V_DD

V_DD= 3.6 V,

_OPE= 33 MHz

+10

Dynamic Supply Current

Static Supply Current

I_DO

I_DS

—

12

—

20

150

1.5

10

mA

mV

kΩ

f

—

D/A Output Relative

Accuracy

|V_DAE

R_DA

|

No load

—

D/A Output Impedance

28

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ML2110

AC Characteristics

(V_DD= 3.0 to 3.6 V, Ta = –40 to 85°C)

Parameter

Source Oscillation Frequency

Input Clock Low-Level

Minimum Width

Input Clock High-Level

Minimum Width

Symbol Condition

Min.

20

Typ.

—

Max.

33

Unit

MHz

f_OSC

—

t_{W_CLKL}

—

13

8

—

ns

t_{W_CLKH}

—

Operating Period

CLKA Delay Time

XO Delay Time

t_CYC

t_CLK

t_XO

t_{W_RST}

t_A

—

30

—

1024

—

50

12

7

—

29

ns

t_CYC

ns

Required RST Time

A Delay Time

D Setup Time

t_{S_D}

—

10

—

ns

D Hold Time

D Delay Time

RD Delay Time

t_{H_D}

t_D

t_RD

—

Falling

Rising

—

2

—

32

25

ns

—

2

22

22+0.5 t_CYC

23

t_WR

ns

WR Delay Time

t_UPORT

t_{S_EXINT}

ns

UPORT Delay Time

EXTINT Setup Time

—

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ML2110

ROM, SRAM Access

(V_DD= 3.0 to 3.6 V, Ta = –40 to 85°C)

Parameter

Symbol

t_{W_RD}

Condition

ROM, SRAM

3τ to 12τ access

ROM, SRAM

3τ to 12τ access

ROM, SRAM

3τ , 4τ access

ROM, SRAM

5τ to 12τ access

SRAM

3τ to 12τ access

SRAM

3τ to 12τ access

—

ROM

3τ to 12τ access

SRAM

3τ to 12τ access

SRAM

Min.

2

Typ.

Max.

Unit

—

11

t_CYC

RD Pulse Width

t_{W_WR}

1.5

—

1

10.5

—

t_CYC

WR Pulse Width

t_{W_ARD}

A to RD Time

2

—

t_{W_AWR}

1

—

A to WR Time

t_{W_WRSRAM}

1

—

WR to SRAM Time

t_ROM

t_SRAM

—

21+0.5 t_CYC

ns

ROM Delay Time

SRAM Delay Time

t_{W_ROM}

3

—

0

12

—

t_CYC

ROM Pulse Width

t_{W_SRAM}

SRAM Pulse Width

—

3τ access

ROM, SRAM

4τ to 12τ access

t_{W_WRD}

WR to D Time

1

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ML2110

DRAM Access

(V_DD= 3.0 to 3.6 V, Ta = –40 to 85°C)

Parameter

RAS Delay Time

RAS Pulse Width

A to RAS Time

Symbol

t_RAS

t_{W_RAS}

t_{W_ARAS}

Condition

Min.

—

3

Typ.

—

Max.

24

Note 1

—

Unit

ns

t_CYC

—

2nt access falling

edge

1

—

22+0.5t_CYC

ns

t_CAS

CAS Delay Time

Normal

Refresh

—

1.5

4

0.5

1.5

—

3

—

1

22

2

5

1

2

23

Note 1

—

ns

t_CYC

ns

t_CYC

ns

t_{W_CAS}

CAS Pulse Width

t_{W_ACAS}

t_{W_RASCAS}

t_{W_WECAS}

t_WE

t_{W_WE}

t_{W_AWE}

A to CAS Time

RAS to CAS Time

WE to CAS Time

WE Delay Time

WE Pulse Width

—

t_CYC

—

A to WE Time

Required

t_{W_PREC}

—

1

—

Note 2

t_CYC

Precharge Time

t_{W_CASRAS}

t_{W_EDO}

—

1

—

1

t_CYC

CAS to RAS Time

CAS to D Time

Hyper Mode

General Device Access

(V_DD= 3.0 to 3.6 V, Ta = –40 to 85°C)

Parameter

AS Delay Time

Symbol

t_AS

Condition

—

Min.

—

Typ.

—

Max.

27

Unit

ns

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ML2110

When DS bit = 0

(V_DD= 3.0 to 3.6 V, Ta = –40 to 85°C)

Parameter

Symbol

t_{W_AS}

Condition

4τ to 7τ Access

(X bit = 0)

8τ to 14τ Access

(X bit = 1)

4τ to 7τ Access

(X bit = 0)

8τ to 14τ Access

(X bit = 1)

4τ to 7τ Access

(X bit = 0)

8τ to 14τ Access

(X bit = 1)

4τ to 7τ Access

(X bit = 0)

8τ to 14τ Access

(X bit = 1)

4τ to 7τ Access

(X bit = 0)

8τ to 14τ Access

(X bit = 1)

4τ to 7τ Access

(X bit = 0)

8τ to 14τ Access

(X bit = 1)

4τ to 7τ Access

(X bit = 0)

8τ to 14τ Access

Min.

2

Typ.

Max.

Unit

—

5

t_CYC

AS Pulse Width

6

—

2

—

1

12

—

5

t_CYC

t_{W_AAS}

A to AS Time

RD Pulse Width

A to RD Time

WR Pulse Width

A to WR Time

D to WR Time

1

—

1

t_{W_RD}

6

12

—

5

—

2

t_{W_ARD}

t_{W_WR}

t_{W_AWR}

t_{W_DWR}

1

—

1

6

12

—

1

0

(X bit = 1)

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FEDL2110-01

OKI Semiconductor

ML2110

When DS bit = 1

(V_DD= 3.0 to 3.6 V, Ta = –40 to 85°C)

Parameter

Symbol

t_{W_AS}

Condition

4τ to 7τ Access

(X bit = 0)

8τ to 14τ Access

(X bit = 1)

4τ to 7τ Access

(X bit = 0)

8τ to 14τ Access

(X bit = 1)

4τ to 7τ Access

(X bit = 0)

8τ to 14τ Access

(X bit = 1)

4τ to 7τ Access

(X bit = 0)

8τ to 14τ Access

(X bit = 1)

4τ to 7τ Access

(X bit = 0)

8τ to 14τ Access

(X bit = 1)

4τ to 7τ Access

(X bit = 0)

8τ to 14τ Access

(X bit = 1)

4τ to 7τ Access

(X bit = 0)

8τ to 14τ Access

Min.

2

Typ.

Max.

Unit

—

5

t_CYC

AS Pulse Width

Note 3

6

—

2

—

1

12

—

5

t_CYC

t_{W_AAS}

A to AS Time

RD Pulse Width

A to RD Time

WR Pulse Width

A to WR Time

D to WR Time

1

—

1

t_{W_RD}

6

12

—

5

—

2

t_{W_ARD}

t_{W_WR}

t_{W_AWR}

t_{W_DWR}

1

—

2

6

12

—

3

1

2

(X bit = 1)

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ML2110

Serial Interface

(V_DD= 3.0 to 3.6 V, Ta = –40 to 85°C)

Parameter

RTS Delay Time

Required RXD Time

RXD Setup Time

RXD Hold Time

CTS Setup Time

CTS Hold Time

Symbol

t_RTS

Condition

Min.

—

1/bps

0.5/bps

0

—

1/bps

—

Typ.

—

Max.

22

—

21

—

23

20

—

Unit

ns

s

ns

s

ns

s

—

t_{W_RXD}

t_{S_RXD}

t_{H_RXD}

t_{S_CTS}

t_{H_CTS}

t_TXD

t_{W_TXD}

t_DTR

t_SCLK

TXD Delay Time

TXD Pulse Width

DTR Delay Time

SCLK Delay Time

SCLK Pulse Width

t_{W_SCLK}

1/bps

Parallel Interface

(V_DD= 3.0 to 3.6 V, Ta = –40 to 85°C)

Parameter

PACK to PD Delay Time

PACK to PD Hi Z Delay

Symbol

t_PACK

Condition

—

Min.

—

Typ.

—

Max.

22

Unit

ns

t_PRDZ

t_{S_PCS}

t_{H_PCS}

t_{S_PIOA}

t_{H_PIOA}

—

0

—

22

—

ns

Time

PCS Setup Time for

PSTB/PACK

PCS Hold Time for

PSTB/PACK

0

PIOA Setup Time for

PSTB/PACK

0

PIOA Hold Time for

PSTB/PACK

3

t_{W_PACK}

t_{W_PSTB}

—

30+t_CYC

30+2t_CYC

—

ns

Required PACK Time

Required PSTB Time

PD Setup Time for

PSTB

t_{S_PD}

t_{H_PD}

—

–t_CYC

8

—

ns

PD Hold Time for PSTB

Digital Signal Output Interface

(V_DD= 3.0 to 3.6 V, Ta = –40 to 85°C)

Parameter

Synchronous Clock

Cycle

Symbol

Condition

—

Min.

100

Typ.

Max.

Unit

t_BCYC

—

ns

Synchronous Clock

Width

t_WSYNC

—

1BCYC

—

ns

BCLK to XSYNC Time

DOUT Delay Time

t_BCKXS

t_DOUT

—

0

—

25

ns

Note 1 According to DRAM configuration

Note 2 Depending the DRAM access timing

Note 3 In case of writing, increased by 1 clock when X bit = 0 and by 2 clocks when X bit = 1.

Note 4 Flash memory access timing is the same with the SRAM timing.

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ML2110

TIMING DIAGRAM

Clock and Reset

t

W_CLKH

W_CLKL

t

OSC

CLK

XO

t

XO

t

CYC

CLKA

t

W_RST

RST

Note: t_OSC= 1/f_OSC

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ML2110

ROM Read

CLK

t

CLKA

t

A

t

A

D

t

H_D

S_D

t

W_ARD

t

W_ROM

t

ROM

RD

t

ROM

t

RD

t

W_RD

3τ/4τ Access

CLK

t

CLKA

t

A

D

t

H_D

S_D

t

W_ARD

t

W_ROM

t

ROM

RD

t

ROM

t

RD

t

W_RD

5τ/6τ/7τ/8τ/10τ/12τ Access

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ML2110

SRAM Read

CLK

t

CLKA

t

A

t

A

D

t

H_D

S_D

t

W_ARD

t

W_SRAM

t

SRAM

RD

t

RD

t

W_RD

3τ/4τ Access

CLK

t

CLKA

t

A

t

H_D

S_D

D

t

W_ARD

t

W_SRAM

t

SRAM

RD

t

RD

t

W_RD

5τ/6τ/7τ/8τ/10τ/12τ Access

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ML2110

SRAM Write

CLK

t

CLKA

t

A

t

A

D

t

D

t

W_AWR

t

W_SRAM

t

SRAM

WR

T

t

W_WRSRAM

WR

t

W_WR

3τ Access

CLK

t

CLKA

t

A

D

t

D

t

W_WRD

W_AWR

t

W_SRAM

t

SRAM

WR

t

W_WRSRAM

WR

t

W_WR

4τ/5τ/6τ/7τ/8τ/10τ/12τ Access

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ML2110

DRAM Read

t

OSC

CLK

CLKA

t

A

row address

column address

A

D

t

H_D

S_D

t

W_ARAS

t

W_PREC

W_RAS

t

RAS

W_ACAS

RAS

CAS

WE

t

RAS

t

CAS

W_CAS

CAS

W_RASCAS

2nτ Access

t

OSC

CLK

CLKA

t

A

t

A

row address

column address

A

t

H_D

S_D

H_D

S_D

D

t

W_ARAS

W_PREC

W_RAS

t

RAS

CAS

WE

W_ACAS

t

RAS

t

CAS

t

W_CAS

t

W_RASCAS

2nτ Access (Fast Page Mode)

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ML2110

t

OSC

CLK

CLKA

t

A

row address

column address

t

A

D

t

S_D

H_D

t

W_ARAS

t

W_RAS

W_PREC

t

W_ACAS

RAS

W_CAS

RAS

CAS

WE

t

RAS

t

CAS

t

W_RASCAS

3nτ Access

t

OSC

CLK

CLKA

t

A

t

A

row address

column address

A

D

t

H_D

S_D

H_D

S_D

t

W_ARAS

W_RAS

W_PREC

t

RAS

CAS

WE

W_ACAS

W_CAS

t

RAS

t

CAS

t

CAS

t

CAS

t

W_RASCAS

3nτ Access (Fast Page Mode)

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ML2110

DRAM Write

t

OSC

CLK

CLKA

t

A

row address

column address

A

D

t

H_D

t

D

t

W_ARAS

t

W_RAS

W_PREC

t

RAS

W_ACAS

RAS

CAS

t

RAS

t

CAS

WE

W_CAS

CAS

W_RASCAS

t

W_AWE

t

W_WE

WE

t

WE

2nτ Access

t

OSC

CLK

CLKA

t

A

t

A

row address

column address

t

column address

A

t

D

t

D

t

W_ARAS

W_PREC

W_RAS

t

RAS

CAS

WE

W_ACAS

t

RAS

CAS

t

CAS

t

W_CAS

t

W_RASCAS

t

W_AWE

t

WE

W_WE

t

WE

2nτ Access (Fast Page Mode)

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ML2110

t

OSC

CLK

CLKA

t

A

column address

row address

A

D

t

H_D

D

t

W_ARAS

t

W_RAS

t

W_PREC

t

RAS

W_ACAS

W_CAS

RAS

CAS

t

RAS

t

W_RASCAS

CAS

WE

CAS

t

W_WECAS

t

W_AWE

t

W_WE

WE

t

WE

3nτ Access

t

OSC

CLK

CLKA

t

A

row address

column address

A

t

D

t

D

t

W_PREC

W_RAS

t

W_ARAS

t

RAS

CAS

W_ACAS

W_CAS

t

RAS

t

W_RASCAS

t

CAS

t

CAS

t

W_CAS

t

W_AWE

t

WE

t

W_WE

WE

t

WE

3nτ Access (Fast Page Mode)

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ML2110

DRAM Refresh

t

OSC

CLK

CLKA

ignore

A

D

t

RAS

W_RAS

RAS

t

W_CASRAS

t

CAS

t

CAS

W_CAS

CAS

WE

2nτ CAS-Before-RAS Refresh

t

OSC

CLK

CLKA

ignore

A

D

t

RAS

W_RAS

RAS

t

W_CASRAS

t

CAS

t

CAS

W_CAS

CAS

WE

3nτ CAS-Before-RAS Refresh

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t

OSC

CLK

CLKA

ignore

A

D

t

RAS

W_RAS

RAS

t

W_CASRAS

t

CAS

t

W_CAS

CAS

WE

CAS-Before-RAS Self-Refresh

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General Device Access

CLK

t

CLKA

t

A

t

A

D

t

S_D

t

W_AS

W_AAS

W_ARD

t

W_AAS

t

AS

RD

AS

RD

t

W_RD

t

RD

Bus Read

CLK

t

CLKA

t

A

D

t

D

t

W_AAS

t

W_AAS

W_AS

t

AS

WR

t

W_AWR

t

WR

t

W_WR

t

WR

Bus Write (When DS bit in The SCR register is “0”)

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CLK

t

CLKA

t

A

t

A

D

t

D

t

W_AS

t

W_AAS

t

AS

t

AS

WR

AS

t

W_AWR

t

WR

t

W_WR

t

WR

t

W_DWR

Bus Write (When DS bit is “1” and X bit is “0”in the SCR register)

CLK

t

CLKA

t

A

t

A

D

t

D

t

W_AS

t

W_AAS

t

AS

t

AS

WR

AS

t

W_AWR

t

WR

t

W_WR

t

WR

W_DWR

Bus Write (When DS bit is “1” and X bit is “1” in the SCR register)

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Parallel Interface

t

OSC

CLK

t

CLKA

t

CLKA

t

H_PCS

t

S_PCS

t

H_PCS

t

S_PCS

t

S_PCS

H_PCS

PCS

t

S_PIOA

H_PIOA

S_PIOA

t

H_PIOA

PIOA

t

W_PACK

PACK

PSTB

t

W_PSTB

t

PRDZ

t

H_PD

t

S_PD

PACK

t

PD

t

PRDZ

PACK

PIBF

t

PACK

t

PRDZ

POBF

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Serial Interface

t

OSC

CLK

t

CLKA

t

S_RXD

H_RXD

t

H_RXD

S_RXD

t

S_RXD

H_RXD

RXD

Start_bit(=0)

bit 0

bit 1

bit 6

bit 7

Stop_bit(=1)

t

RTS

t

W_RXD

RTS

W_RXD

RTS

t

OSC

CLK

t

CLKA

t

TXD

t

TXD

bit 1

t

TXD

RXD

Start_bit(=0)

bit 0

bit 6

bit 7

Stop_bit(=1)

t

S_CTS

t

W_TXD

t

H_CTS

RTS

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CLK

t

CLKA

SCLK

t

SCLK

t

W_SCLK

t

SCLK

t

W_SCLK

SCLK

Synchronous Transfer Output

General Port Output

CLK

t

CLKA

t

UPORT

General Port Output

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Digital Signal Output

t

BCYC

BCLK

t

BCKXS

XSYNC

t

WSYNC

t

DOUT

D15

t

DOUT

MSD

D2

* BCLK and XSYNC must be synthesized.

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Standby Operation

CLK

XO

CLKA

t

W_RST

RST*

t

RSTSTBY_H

RSTSTBY_S

STBY

t

STBYCLKA

CPU Operation

Operating

Suspend

Operating

Resume

Process

Suspend

Process

RAS

CAS

Maintain the pin level on the STBY signal until the CPU has completed its suspend process and clock

Signal CLKA has stopped.

After the STBY signal is released, the CPU will not resume until oscillation has stabilized (1024t_CYC).

* The RST signal is not necessary for self-refresh DRAM.

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Interrupt Process

CLK

XO

CLKA

EXTINT

The external interrupt signal EXTINT requests an interrupt to the CPU. The pin level on EXTINT

must be maintained until the CPU accepts the interrupt. Also, be sure to clear the interrupt source

within the interrupt routine.

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FUNCTIONAL DESCRIPTION

CPU Core

1. Features

The SCP (Speech Control Processor) uses a CPU core with an Oki-original 32-bit RISC architecture.

2. Register Configuration

The CPU core registers are configured as 32 words for general registers, 7 words for privileged

registers, and 1 word for a special register.

Privileged Registers

General Register

%r0 (link)

%PSR

%VBA

%prPSR

%IRR

%r1 (pre-PC)

%r2 (pre-nPC)

%r3 (long-immed.)

%r4

%BPA

%PC

%r5

%nPC

Special Register

%NOP

%r30

%r31

2.1 General Registers

The general registers are a set of 32 registers with 32-bit width. Of these registers %r0 to %r3 can be

used as general registers, but they do have special functions pre-assigned by the system. Registers

%r4 to %r31 can be used freely. Contents are undefined after reset.

bit 31

0

GR

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%r0: Link register (stores subroutine return address). Also stores %PC+4 during bl instruction

execution.

%r1: Stores value of %PC when an exception, interrupt, or trap is accepted.

%r2: Stores value of %nPC when an exception, interrupt, or trap is accepted.

%r3: Stores the immediate value of SETLI (Set Long Immediate) instructions.

2.2 Privileged Registers

Reads are allowed at any processor level (PL:Processor Level: 0 = user mode, 1 or above = supervisor

mode), but write accesses are allowed only when the processor level is supervisor mode. The

privileged registers are configured as 7 words, and are used primarily for processor control. If the

processor attempts a write access to a privileged register while in user mode, then the instruction will

not be executed and a privileged instruction exception will be issued.

2.2.1 PSR (Processor Status Register)

This register sets and displays the state of the processor.

bit31

28272625 2423222120191817 161514131211 10 9 8 7 6 5 4 3

M M

0

I

I N

E

F F

U U

3216

0 0 0 0 0

0 0 0 0 0 V C N Z 0 C C O 0 0 B

PL

VER

M

P L P

P

• bit[31:28] VER: Version (read-only)

Indicates the CPU core version. Currently fixed to "3".

• bit[22] MFU32 (read-only)

Indicates whether the32-bit multiplier unit is present ("1")or not("0"). This is "0"for theML2110.

• bit[21] MFU16 (read-only)

Indicates whether the16-bit multiplier unit is present ("1")or not("0"). This is "1"for theML2110.

• bit[15] V: Overflow (read-only)

Indicates that execution of an addition or subtraction instruction resulted in an arithmetic

overflow.

• bit[14] C: Carry (read-only)

Indicates that execution of an addition or subtraction instruction resulted in an arithmetic carry or

borrow.

• bit[13] N: Negative (read-only)

Indicates that execution of an addition or subtraction instruction resulted in a negative value

(bit[31] is "1").

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• bit[12] Z: Zero (read-only)

Indicates that execution of an addition or subtraction instruction resulted in a zero value (bit[31:0]

are all "0").

• bit[10] ICP: Instruction Cache Purge (read/write)

Invalidates all instruction cache entries. Writing "1" to this bit purges the contents of the instruction

cache. After this process (after one cycle) this bit is automatically cleared to "0" by hardware. The

instruction cache is purged during reset.

• bit[9] ICL: Instruction Cache Lock (read/write)

Freezes all instruction cache entries. After "1" is written to this bit, instruction cache contents are

frozen and then instruction execution continues. This bit will be "1" after reset.

• bit[8] NOP: Non-Operation (read-only)

When set to "1", forces the next instruction to a NOP regardless of the instruction. There is no way

to directly set this bit to "1". This bit will be "0" after reset.

• bit [5] EBP: Breakpoint Trap Enable (read/write)

Enables breaks. If this bit is set to "1", then a trap will occur when the value of the instruction

execution address (%PC) equals the value of the breakpoint address (%BPA). The instruction that

generated the break will not be executed. This bit will be "0" after reset.

• bit[4] EM: Master Enable (read/write)

Disables all exceptions, interrupts, and traps. This bit automatically becomes "0" at the point when

the processor accepts an exception, interrupt, or trap. While this bit is "0", further exceptions,

interrupts or traps will not be accepted, with instruction execution continuing in the normal

instruction sequence. An instruction must be used to return this bit to "1". It will be "0" after reset.

• bit[3:0] PL: Processor Level (read/write)

Sets and provides the processor’s instruction execution level. Processor levels are 0-15. An external

interrupt will be accepted if its level has a higher priority than the processor level at that time.

External interrupt levels are 1-16, so when PL is 0 all external interrupts will be accepted, and when

PL is 1 external interrupts of level 2 and above will be accepted. When an external interrupt is

accepted, the processor level will become the same as the external interrupt level. For example, if

PL is 5 and a level 7 external interrupt is accepted, then PL will transition to 7 at that point. When

PL is restored to its previous state, its saved value in %prPSR will be restored to %PSR.

Alternatively PL can be set to its previous value explicitly by an instruction in the interrupt process

routine. However, %PSR is a privileged register, so writes are only permitted in supervisor mode.

PL will be set to 15 after reset.

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2.2.2 VBA: Vector Base Address (read/write)

This read/write register sets the leading address of the dispatch table (vector table) to exception,

interrupt, and trap process routines.

bit31

1211

0

VBA

0 0 0 0 0 0 0 0 0 0 0 0

The dispatch table is 256 entries of 4K bytes size, with 16 bytes (4 instructions) save for each entry’s

dispatch routine. Entry points are generated by an OR operation with this register, so they are set

at4K-byte boundaries. As a result, only the upper20bitsof an argument will be written to the VBA

register (the lower 12 bits will be ignored).

Entry_point = VBA[31:12] ||(vector_number << 4)

This register is undefined after reset.

2.2.3 prPSR: Pre-Processor Status Register (read/write)

This read/write register saves the value of %PSR at the time an exception, interrupt, or trap is

accepted. In order to accept overlapping exceptions, interrupts, and traps, the valueof %prPSR must

be pushed on a stack and then EM of %PSR must be set to "1".

bit 31

28272625 2423222120191817 161514131211 10 9 8 7 6 5 4 3

0

p p p

p

M M

F F

U U

3216

p

E

M

p p p p

V C N Z

I

I N

E

B

P

pPL

0 0 0 0 0

0

0 0

VER

C C O

P L P

The upper 16 bits of %prPSR are always identical to %PSR. Refer to the descriptions of the same bit

positions in %PSR for an explanation of %prPSR bits.

2.2.4 IRR: Interrupt Request Register (read-only)

This register indicates whether there is an interrupt request at each of the 16 levels of external

interrupts. It is read-only, and shows interrupt requests regardless of PL(processor level). The IRR

value will continue until an interrupt source is released.

6 5 4 3 2 1 0

161514131211 10 9 8 7

bit 31

I

I I I I I I I

I

N

M

I

R R R R R R R R R R R R R R R

Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q

1514131211 10 9 8 7 6 5 4 3 2 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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The ML2110 uses only 7 interrupts of the 16 interrupt levels.

bit 31

161514131211 10 9 8 7 6 5 4 3 2 1 0

I

R

Q

9

R

Q

7

R

Q

5

R

Q

3

0

0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0

Q

13

Q

15

Q

11

2.2.5 BPA: Breakpoint Address (read/write)

This read/write register sets and shows the instruction address (byte address) where a breakpoint

Trap occurred. The lowest 2 bits will alwaysbe"0". When EBP of %PSRis"1",a trap will be generated

immediately before execution of the instruction at the breakpoint set by this register. This register

will be undefined after reset.

bit 31

2 1 0

0 0

BPA

2.2.6 PC: Program Counter (read-only)

This read-only register provides the instruction address (byte address) in the execution phase. Its

lowest 2 bits will always be "0".

bit 31

2 1 0

0 0

PC

2.2.7 nPC: Next Program Counter (read-only)

This read-only register provides the instruction address(byte address) in the instruction decode

phase. Its lowest 2 bits will always be "0".

bit 31

2 1 0

0 0

nPC

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2.3 Special Registers

These are not privileged registers, but they are special registers used for specific functions.

2.3.1 NOP: Non-Operation (read/write)

When this register is specified as a destination register, execution results will not be stored anywhere.

When specified as a source register, it will read as an undefined value.

bit 31

0

NOP

3. Data Formats

There are two data format types: one for internal processor core calculations and one for memory

accesses.

3.1 Internal Data Format

The CPU core handles all data as 32 bits (word format). Therefore, when the format of data stored

in memory is byte (8 bits) or half-word (16 bits) it must be used internally as 32-bit data through a

signed load instruction or unsigned load instruction. Similarly when internal core processing results

are stored to memory, a store instruction corresponding to the data format in memory must be

executed. Also, bit addresses specified for bit test instructions and bit manipulation instructions are

shown in the diagram below.

bit 313029282726252423222120191817 161514131211 10 9 8 7 6 5 4 3 2 1 0

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3.2 Memory Data Format

The following memory data formats are supported: byte (8 bits), half-word (16 bits), and word (32

bits). Memory addresses are always byte addresses regardless of data format. However, half-word

accesses must be on 16-bit boundaries (least significant bit is "0"), and word accesses must be on 32-

bit boundaries (least significant 2 bits are "00"). If a load or store instruction execution attempts a

memory access that violates these boundaries, then a data address invalid exception will occur.

Memory addressing is big-endian. The diagrams below show memory data formats for byte data

access, half-word data access, and word data access.

Byte Data Access

bit 31

2423

16 15

8

7

0

byte

n+2

byte

n

byte

n+3

byte

n+1

Address

Half-Word Data Access

bit31

16 15

0

half word

n

half word

n+1

Address

Word Data Access

bit 31

0

word

n

Address

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3.3 Memory Addressing Modes

Memory addresses are byte addresses, so memory addressing is performed with three types of load

instructions and two types of store instructions. Swap instructions have the same memory

addressing as store instructions.

3.3.1 Load Instruction Addressing

Base + Index

The effective address (EA) is obtained by adding the values of any two general registers %r0-31

specified.

EA = [reg_S1 + reg_S2]

Base + Displacement

The effective address (EA) is obtained by adding the value of any general register %r0-31 specified

and a displacement given by the instruction’s immediate value field.

EA = [reg_S1] + offS

3.3.2 Store Instruction Addressing

Base + Displacement

The effective address (EA) is obtained by adding the value of any general register %r0-31 specified

and a displacement given by the instruction’s immediate value field.

EA = [reg_S1] + offS

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4. Instruction Set

All instructions are fixed 32-bit length

Category

Instruction

Function

Register-register move

mov S,D

Move

movh S1,D’

Move upper bits

Store immediate value

Store

seti imm17S,D

setih const16.D’

setli const25

sb S2/immS,[S1+offS]

shw S2/immS,[S1+offS]

sw S2/immS,[S1+offS]

swap S2,[S1+offS]

lb [S1+offS].D’

Store immediate value

Store immediate value to upper 16 bits.

Store immediate value left-shifted 7 bitsto %r3

Byte store

Half-word store

Word store

Swap

Load

Swap

Bye load

lhw [S1+offS].D’

Half-word load

lw [S1+offS].D’

Word load

Multiplication

mul0 S1,S2/immS,D’

Mul16 S1,S2/immS,D’

Mul32 S1,S2/immS,D’

mulu0 S1,S2/immS,D’

Mulu16 S1,S2/immS,D’

Mulu32 S1,S2/immS,D’

Signed multiply

Unsigned multiply

Multiply instructions need two clocks for execution time.

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5. Exceptions, Traps, and Interrupts

The CPU core of SCP provides error exceptions, traps, external interrupts, and software traps (by

trap instructions). Each type has a corresponding interrupt priority level and instruction dispatch

address.

Vector

number

Synchronous/asynchronous

(Sense)

Asynchronous (level)

Asynchronous (edge)

Synchronous

Source

System reset

CPU reset (INIT)

Instruction access exception

Branch address

Priority

0x00000000

VBA+0x000

VBA+0x010

0

1

2

0

1

Instruction

exception

address

invalid

2

VBA+0x020

3

Synchronous

Reserved instruction exception

Privileged instruction exception

Data address invalid exception

Data access exception

Reserved

3

4

5

6

7

8

VBA+0x030

VBA+0x040

VBA+0x050

VBA+0x060

VBA+0x070

VBA+0x080

VBA+0x090

to VBA+0x200

VBA+0x210

VBA+0x220

VBA+0x230

VBA+0x240

VBA+0x250

VBA+0x260

VBA+0x270

VBA+0x280

VBA+0x290

VBA+0x2a0

VBA+0x2b0

VBA+0x2c0

VBA+0x2d0

VBA+0x2e0

VBA+0x2f0

VBA+0x300

VBA+0x000

to VBA+0xff0

4

5

8

9

Synchronous

Asynchronous (edge)

Breakpoint trap

6

Synchronous

Reserved

9 to 32

External interrupt 1

External interrupt 2

External interrupt 3

External interrupt 4

External interrupt 5

External interrupt 6

External interrupt 7

External interrupt 8

External interrupt 9

External interrupt 10

External interrupt 11

External interrupt 12

External interrupt 13

External interrupt 14

External interrupt 15

External interrupt 16 (NMI)

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

Asynchronous (level)

TRAP instruction

0 to 255

7

Synchronous

The system reset vector is at absolute address 0. All others are ORed with VBA as the base address.

Synchronous detection is acceptance of a request within an instruction cycle.

Asynchronous detection is acceptance of a request between instruction cycles or at any point in time

after.

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5.1 RST: System Reset

A system reset resets all states under all circumstances.

Type: Asynchronous hardware reset after RST pin level detection.

Vector address: Absolute address 0 (0x00000000).

Conditions: Non-maskable (unconditional)

PL after interrupt transition: 15

5.2 IAE: Instruction Access Exception

An instruction access exception is generated when an instruction is fetched from an undefined

memory space. If the instruction is converted to a NOP by delayed instruction control (x-bit

manipulation), then no exception will be generated.

Type: Instruction-synchronous exception caused by memory access error during instruction fetch.

Vector number/address: Vector number = 1 / VBA+0x010

Conditions: Non-maskable (unconditional). Invalidated by delayed instruction control (x-bit).

Saved address: Address of the instruction that caused the exception.

PL after interrupt transition: 15

5.3 IAIE: Instruction Address Invalid Exception

An instruction address invalid exception is generated when a register indirect branch instruction

attempts an instruction fetch at an address that is not on a word boundary. If the instruction is

converted to a NOP by delayed instruction control (x-bit manipulation), then no exception will be

generated.

Type: Instruction-synchronous exception caused by an illegal JLR or RT instruction.

Vector number/address: Vector number = 2 / VBA+0x020

Conditions: Non-maskable (unconditional). Invalidated by delayed instruction control (x-bit).

Saved address: Address of the instruction that caused the exception.

PL after interrupt transition: 15

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5.4 PIE: Privileged Instruction Exception

A privileged instruction exception is generated when an action that can only be performed in

supervisor mode attempted in user mode: (a) in user mode a privileged register is specified as a

destination, or (b) in user mode a number 64 or below is specified for a TRAP instruction vector. If

the instruction is converted to a NOP by delayed instruction control (x-bit manipulation), then no

exception will be generated.

Type: Instruction-synchronous exception caused by an illegal privileged instruction.

Vector number/address: Vector number = 4 / VBA+0x040

Conditions: Non-maskable (unconditional). Invalidated by delayed instruction control (x-bit).

Saved address: Address of the instruction that caused the exception.

PL after interrupt transition: 15

5.5 DAIE: Data Address Invalid Exception

A data address invalid exception is generated when a memory access instruction attempts to access

a memory address not on a word boundary.

Type: Asynchronous exception caused by an illegal memory access instruction.

Vector number/address: Vector number = 5 / VBA+0x050

Conditions: EM == 1. However, exception must be maintained until accepted.

Saved address: Address being executed when the exception was accepted.

PL after interrupt transition: 15

5.6 DAE: Data Access Exception

A data access exception is generated when data is accessed in an undefined memory space.

Type: A synchronous exception caused by a memory access instruction error.

Vector number/address: Vector number = 6 / VBA+0x060

Conditions: EM == 1. However, exception must be maintained until accepted.

Saved address: Address being executed when the exception was accepted.

PL after interrupt transition: 15

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5.7 BPT: Breakpoint Trap

A breakpoint trap is generated when the instruction execution address matches the address pointed

to by the %BPA register. However, the EBP bit in the %PSR register must be enabled. The instruction

at the address that causes the trap will not be executed. The trap will be generated even if the

instruction is converted to a NOP by delayed instruction control (x-bit manipulation).

Type: Instruction-synchronous trap caused by hardware.

Vector number/address: Vector number = 8 / VBA+0x080

Conditions: EM == 1 && EBP == 1. Not invalidated by delayed instruction control (x-bit).

Saved address: Address pointed to by the %BPA register.

PL after interrupt transition: 15

5.8 EINT: External Interrupt 1-15

External interrupts are generated by inputs. However, an external interrupt will be accepted only

when its level has higher priority than the current processor level. When an external interrupt is

accepted, the processor level becomes the same as its level.

Type: A synchronous interrupt when level on INT1-INT15 pins is detected.

Vector number/address: Vector number = 33-47 / VBA+0x210-0x2f0

Conditions: EM == 1 && PL < external_interrupt_number

Saved address: Address being executed when the interrupt was accepted.

PL after interrupt transition: External interrupt number

The ML2110 assigns interrupt levels as follows. It does not use other interrupts (including NMI).

Interrupt Source

EXTINT1

D/A Converter

DOUT

EXTINT0

Serial I/O

Parallel I/O

TMR1

Priority

Interrupt Number

1

2

3

4

5

6

7

INT15

INT13

INT11

INT9

INT7

INT5

INT3

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5.9 Return From Interrupt

In order to return from an interrupt process caused by an exception, external interrupt, or software

trap, the pipeline at the time of the interrupt must be regenerated before execution.

There are two types of returns: (1) re-execution of an instruction that was in its execution phase at

the time an exception, external interrupt, or asynchronous trap caused an interrupt, and (2) re-

execution of the instruction after the instruction that was in its execution phase at the time a software

trap caused an interrupt. However, if breakpoints are supported by software traps then case (1)

applies.

The return sequence from an interface process is described below.

Also, an rt instruction must not be executed while the EM bit of %PSR is 1 (the state permitting

overlapping interrupts). If an interrupt occurred during the rt instruction in such a case, then the

contents of %PSR would be corrupted.

1. Resume from interrupted instruction

brst

jlr

%psr, 4, %psr

%r1, %nop

; EM-bit reset

; delay slot, branch %r1 (old %PC),

; return address not saved

rt

%r2

; return to %r2 (old %nPC), %prPSR move to %PSR

2. Return from instruction after interrupt

add

brst

jlr

%r2, 4, %r1

%psr, 4, %psr

%r2, %nop

; %r2+4 (old %nPC+4)®%r1

; EM-bit reset

; delay slot, branch %r2 (old %nPC), return address not saved

rt

%r1

; return to %r1 (old %nPC+4), %prPSR move to %PSR

In this case the pNOP bit of %prPSR must be cleared in advance of rt instruction execution. If the

pNOP bit of %prPSR is set and then the rt instruction is executed, then the instruction at the return

point would not be executed.

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Bus Interface Unit

1. Features

The SCP’s bus interface unit (BIU) manages address space and outputs control signals that enable

optimal memory access. This allows ROM, SRAM, DRAM and other general devices to be accessed.

2. Address Space

The address space that can be directly accessed by load/store instructions is 4 gigabytes. The BIU

manages this address space by dividing it into several.

0x00000000

ROM

256MB

0x0FFFFFFF

0x10000000

SRAM

0x1FFFFFFF

0x20000000

256MB

DRAM

External

0x2FFFFFFF

0x30000000

Reserved

0x3FFFFFFF

0x40000000

General devices

Reserved

1GB

4GB

0x7FFFFFFF

0x80000000

0xBFFFFFFF

0xC0000000

256MB

Internal ROM

Internal RAM

0xCFFFFFFF

0xD0000000

Internal

0xDFFFFFFF

0xE0000000

Registers

512MB

0xFFFFFFFF

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2.1 ROM Space

ML2110

ROM space is assigned to 0x00000000-0x0FFFFFFF. When this space is accessed the ROM signal goes

"L".

2.2 SRAM Space

SRAM space is assigned to 0x10000000-0x1FFFFFFF. When this space is accessed the SRAM signal

goes "L".

2.3 DRAM Space

DRAM space is assigned to 0x20000000-0x2FFFFFFF. When this space is accessed the DRAM

controller outputs a signal required for DRAM access.

2.4 General Device Space

General device space is assigned to 0x40000000-0x7FFFFFFF. When this space is accessed the AS

signal goes "L". This space is used to access general devices external to the ML2110.

2.5 Internal ROM Space

Internal ROM space is assigned to 0xC0000000-0xCFFFFFFF. It is used to access internal ROM.

This space is not used by the ML2110. Accesses to this space will cause instruction access

exceptions or data access exceptions.

2.6 Internal RAM Space

Internal RAM space is assigned to 0xD0000000-0xDFFFFFFF. It is used to access internal RAM.

This space is not used by the ML2110. Access to this will cause instruction access exceptions or data

access exceptions.

2.7 Register Space

Register space is assigned to 0xE0000000-0xFFFFFFFF. Within this space, 0xF8000000-0xFFFFFFFF

is assigned for standard I/O and system registers.

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0xF8000000

TMR

0xF8FFFFFF

0xF9000000

0xF9FFFFFF

0xFA000000

0xFAFFFFFF

0xFB000000

BSR

BEA

ECR

SCR

SIO

PIO

0xFF000000

0xFF000004

0xFF000008

0xFF00000C

0xFF000010

0xFF000014

0xFF000018

0xFF00001C

0xFBFFFFFF

0xFC000000

0xFCFFFFFF

0xFD000000

0xFDFFFFFF

0xFE000000

0xFEFFFFFF

0xFF000000

0xFF000020

0xFF00003F

DRAMC

0xFFFFFFFF

0xFF000040

0xFF00005F

System Registers

0xFF000080

0xFF0000FF

Test Circuit

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3.Registers

This is a register group used for bus control.

3.1 BEA: Bus Error Address

This register provides the address at the time a bus error occurred.

bit 31

0

BEA

3.2 BSR: Bus Status Register

This register provides bus status information.

bit31

191817 161514 1211

C

8 7 6

0

4 3 2 1 0

S 0

P

ST

PEB

BES 0 0 H R

XSP

• bit[18:17] XSP: Sleep (read/write)

When the STBY signal is "L", these bits either stop the clock without CPU intervention (XSP = 00)

or stop the clock after waiting for the CPU suspend process (XSP = 11).

• bit[16] CSP: CPU Sleep (read/write)

This bit indicates whether the CPU core is operating or suspended. Writing "1" will stop the CPU

core’s clock.

• bit[14:12] ST: Status (read-only)

These bits save the status signals when an access by the CPU core causes a bus error.

• bit[11:8] PEB: Parity Error Byte (read-only)

These bits provide the byte position when a parity error occurs.

• bit[6:4] BES: Bus Error Status (read-only)

These bits provide the source of a bus error.

BES = 000

BES = 001

BES = 010

BES = 100

No error

BIU register privilege violation

Parity error

Invalid space access

These bits will be "000" after reset.

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• bit[1] H: Hold (read/write)

This bit sets whether or not bus rights will be passed upon a CPU core bus rights request. This bit

will be "0" after reset.

3.3 ECR: Extra Configuration Register

This register sets bus operation.

bit

31

11 10 9 8 7 6

4 3 2 1 0

O A

X X

P

M

O A D

A

0

BM

V V V

• bit[10] OX: Internal ROM (read-only)

This bit indicates whether or not internal ROM will be accessed in 2 clocks.

ML2110 does not use this bit.

• bit[9] AX: Internal RAM (read-only)

This bit indicates whether or not internal RAM will be accessed in 2 clocks.

ML2110 does not use this bit.

• bit[7] PM: Parity Mode (read/write)

This bit sets parity.

PM = 0

PM = 1

Even parity

Odd parity

This bit will be "0" after reset.

ML2110 does not use parity checking, so it ignores this field.

• bit[3] A: All Internal ROM (read/write)

This bit sets whether or not internal ROM will be accessed instead of external ROM.

ML2110 has no internal ROM, so this bit is always "0".

• bit[2] OV: Internal ROM Valid (read-only)

This bit shows whether internal ROM is enabled or disabled.

This bit is "0" for ML2110.

• bit[1] AV: Internal RAM Valid (read-only)

This bit shows whether internal RAM is enabled or disabled.

This bit is "1" for ML2110.

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3.4 SCR: Space Configuration Register

This register sets ROM space, SRAM space, and general device space.

bit 31

2625 2423 2120 1817 1615141312 10 9 8 7 6 5 4 3 2 1 0

A A

C D

O O

C D

D P S

S C D

ARW AWW AS

0

ORW OS

X WT SZ

• bit[25] AC: SRAM Parity Check (read/write)

This bit sets parity checking of SRAM space. It will be "0" after reset.

AC = 0

AC = 1

Ignore parity checks.

Generate a bus error if a parity error is detected.

• bit[24] AD: SRAM Dummy Cycle (read/write)

This bit sets whether or not SRAM space may be accessed continuously after ROM space or DRAM

space has been read.

AD = 0

AD = 1

Continuous access allowed.

Open an interval of at least one clock.

This bit will be "1" after reset.

• bit[23:21] ARW: SRAM Read Wait (read/write)

These bits set the wait count when SRAM space is accessed by a read.

ARW = 000 2t access (1 wait)

ARW = 001 3t access (2 waits)

ARW = 010 4t access (3 waits)

ARW = 011 5t access (4 waits)

ARW = 100 6t access (5 waits)

ARW = 101 8t access (7 waits)

ARW = 110 10t access (9 waits)

ARW = 111 12t access (11 waits)

These bits will be "111" after reset.

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• bit[20:18] AWW: SRAM Write Wait (read/write)

These bits set the wait count when SRAM space is accessed by a write.

AWW = 000 2t access (1 wait)

AWW = 001 3t access (2 waits)

AWW = 010 4t access (3 waits)

AWW = 011 5t access (4 waits)

AWW = 100 6t access (5 waits)

AWW = 101 8t access (7 waits)

AWW = 110 10t access (9 waits)

AWW = 111 12t access (11 waits)

These bits will be "111" after reset.

• bit[17:16] AS: SRAM Device Size (read/write)

These bits set the device size of SRAM space.

AS = 00 No SRAM (space is invalid)

AS = 01 8-bit wide device

AS = 10 16-bit wide device

AS = 11 32-bit wide device

These bits will be "00" after reset. When this field is "00", attempting to access SRAM space will

cause an instruction access exception or data access exception.

• bit[14] OC: ROM Parity Check (read/write)

This bit sets parity checking for ROM space. It will be "0" after reset.

OC = 0 Ignore parity errors.

OC = 1 Generate a bus error if a parity error is detected.

This bit will be "0" for the ML2110.

• bit[13] OD: ROM Dummy Cycle (read/write)

This bit sets whether or not a ROM space access will immediately follow an SRAM space or DRAM

space read.

OD = 0 Consecutive access enabled.

OD = 1 Force an interval of at least one clock.

This bit will be "1" after reset.

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• bit[12:10] ORW: ROM Read Wait (read/write)

These bits set the wait count when ROM space is accessed by a read.

ORW = 000

ORW = 001

ORW = 010

ORW = 011

ORW = 100

ORW = 101

ORW = 110

ORW = 111

2t access (1 wait)

3t access (2 waits)

4t access (3 waits)

5t access (4 waits)

6t access (5 waits)

8t access (7 waits)

10t access (9 waits)

12t access (11 waits)

These bits will be "111" after reset.

• bit[9:8] OS: ROM Device Size (read/write)

These bits set the device size of ROM space.

OS = 00 No ROM (space is invalid)

OS = 01 8-bit wide device

OS = 10 16-bit wide device

OS = 11 32-bit wide device

When this field is "00", attempting to access ROM space will cause an instruction access exception

or data access exception.

• bit[7] DS: Other Data Setup (read/write)

This bit sets whether or not the data setup time to the write strobe signal WR is guaranteed during

writes to general device space.

DS = 0 Not guaranteed.

DS = 1 Guaranteed.

This bit will be "1" after reset.

• bit[6] PC: Other Parity Check (read/write)

This bit sets parity checking for general device space. It will be "0" after reset.

PC = 0 Ignore parity errors.

PC = 1 Generate a bus error if a parity error is detected.

This bit will be "0" for the ML2110.

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• bit[5] SD: Other Dummy Cycle (read/write)

This bit sets whether or not a general device space access will immediately follow an SRAM space

or DRAM space read.

SD = 0 Consecutive access enabled.

SD = 1 Force an interval of at least one clock.

This bit will be "1" after reset.

• bit[4] X: External Bus Clock Unit (read/write)

This bit sets the operating clock unit for general device space.

X = 0

X = 1

Use 1 clock as the unit.

Use 2 clocks as the unit.

This bit will be "0" after reset.

• bit[3:2] WT: Other Wait (read/write)

These bits set the wait count when general device space is accessed.

WT = 00 4t access

WT = 01 5t access

WT = 10 6t access

WT = 11 7t access

These bits will be "11" after reset.

• bit[1:0] SZ: Other Device Size (read/write)

These bits set the device size of general device space.

SZ = 00 No general device (space is invalid)

SZ = 01 8-bit wide device

SZ = 10 16-bit wide device

SZ = 11 32-bit wide device

These bits will be "11" after reset. When this field is "00", attempting to access general device space

will cause an instruction access exception or data access exception.

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3.2 DRAM: DRAM Configuration Register

This register sets DRAM space.

bit 31 2928272625 2423222120 1817 1615 131211 10 9

R

0

E

D

P

REF

0 0 0 DT

TP

MD

RA

CS

CA

SZ F

M

After this register has been written, DRAM must not be accessed until the DRAM is operating

properly. Refer to the data sheet of the DRAM used to obtain the required conditions for proper

DRAM operation.

• bit[28:27] DT: Device Type (read/write)

These bits set the DRAM device type.

DT = 00 Fast page mode

DT = 01 Hyper-page mode (EDO DRAM)

These bits will be "00" after reset.

• bit[26] PR: Parity Check (read/write)

This bit sets parity checking for DRAM space. It will be "0" after reset.

PR = 0 Ignore parity errors.

PR = 1 Generate a bus error if a parity error is detected.

This bit will be "0" for the ML2110.

• bit[25:24] TP: Type (read/write)

This bit sets the DRAM’s RAS signal and byte position control signal.

TP = 00 1 RAS mode, byte position CAS control

TP = 01 2 RAS mode, byte position CAS control

TP = 10 1 RAS mode, byte position WE control

TP = 11 2 RAS mode, byte position WE control

These bits will be "00" after reset.

• bit[23] DP: Data Priority (read/write)

This bit sets the priority of processing when data access is requested by a load/store instruction

during a one-line instruction cache read from DRAM due to an instruction cache miss.

DP = 0 Give priority to the instruction cache read from DRAM.

DP = 1 Give priority to the data access.

This bit will be "0" after reset.

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• bit[22:21] MD: Mode (read/write)

These bits set the number of clocks for a DRAM access.

MD = 01 2n clock access

MD = 10 3n clock access

These bits will be "10" after reset.

• bit[20:18] RA: Row Address (read/write)

These bits set the most significant bit position of the row address.

RA = 000 A17

RA = 001 A18

RA = 010 A19

RA = 011 A20

RA = 100 A21

RA = 101 A22

RA = 110 A23

These bits will be "000" after reset.

• bit[17:16] RS: Row Shift (read/write)

These bits set how many bits to shift the row address to output it as a DRAM address.

RS = 00 8-bit shift

RS = 01 9-bit shift

RS = 10 10-bit shift

RS = 11 11-bit shift

These bits will be "00" after reset.

• bit[15:13] CA: Column Address (read/write)

These bits set the most significant bit position of the column address.

CA = 000 A08

CA = 001 A09

CA = 010 A10

CA = 011 A11

CA = 100 A12

These bits will be "000" after reset.

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• bit[12:11] SZ: Device Size (read/write)

These bits set the device size of DRAM space.

SZ = 00 No DRAM (space is invalid)

SZ = 01 8-bit wide device

SZ = 10 16-bit wide device

SZ = 11 32-bit wide device

These bits will be "00" after reset. When this field is "00", attempting to access DRAM space will

cause an instruction access exception or data access exception.

• bit[10] RFM: Refresh Mode (read/write)

This bit sets the refresh operation mode.

RFM = 0 CAS-before-RAS refresh

RFM = 1 CAS-before-RAS self-refresh

This bit will be "0" after reset.

• bit[9:0] RFC: Refresh Counter (read/write)

These bits set the initial value of the refresh counter. It should be set as an integer value obtained

by:

[(refresh period) ÷ (clock period) ÷ 16] – 1

These bits will be "0000000000" after reset.

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4. ROM Access

The ML2110 interface with ROM is shown below.

Axx

ROM

Dxx

ROM

RD

CS

OE

Data

External Bus

ML2110

The ROM signal will become "0" when the address signal and specified ROM space match. Refer to

the timing diagram for basic timing of ROM accesses.

5. SRAM Access

The ML2110 interface with SRAM is shown below.

Axx

SRAM

Dxx

SRAM

WE

CS

WE

OE

RD

Data

External Bus

ML2110

The SRAM signal will become "0" when the address signal and specified SRAM space match. Refer

to the timing diagram for basic timing of SRAM accesses.

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6. DRAM Access

ML2110

There are two ML2110 interfaces with DRAM: one when byte position is specified by CAS, and one

when byte position is specified by WE. This is set by the DRAM register’s TP field.

An interface example when byte position is specified by CAS is shown below.

Axx

DRAM

Dxx

RAS

CAS[0:3]

WE

RAS

CAS

WE

Data

External Bus

ML2110

An interface example when byte position is specified by WE is shown below.

Axx

DRAM

Dxx

RAS

CAS

WE

CAS[0:3]

Data

ML2110

External Bus

Refer to the timing chart for basic timing of DRAM accesses.

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The table below shows how address signals are connected for different DRAM configurations.

Configuration

256Kx8

256Kx16

Row

Column

08-00

09-01

08-01

10-02

09-02

08-00

09-01

10-02

09-00

10-01

09-01

08-01

11-02

10-02

09-02

09-00

08-00

10-01

09-01

11-02

10-02

10-00

09-00

11-01

10-01

12-02

11-02

Address lines

A[08:00]

A[09:01]

A[10:02]

A[11:02]

A[09:00]

A[10:01]

A[11:02]

A[09:00]

A[10:01]

A[11:01]

A[12:01]

A[11:02]

A[12:02]

A[13:02]

A[10:00]

A[11:00]

A[11:01]

A[12:01]

A[12:02]

A[13:02]

A[10:00]

A[11:00]

A[11:01]

A[12:01]

A[12:02]

A[13:02]

CA

000

001

000

010

001

000

001

010

001

010

001

000

011

010

001

000

010

001

011

010

001

011

010

100

011

RS

01

00

01

00

01

10

01

00

10

01

00

10

01

10

01

10

01

11

10

11

10

11

10

RA

000

001

010

001

010

011

010

011

100

011

100

101

100

101

110

17-09

18-10

18-09

19-11

19-10

18-09

19-10

20-11

19-10

20-11

20-10

20-09

21-12

21-11

21-10

20-10

20-09

21-11

21-10

22-12

22-11

21-11

21-10

22-12

22-11

23-13

23-12

256Kx32

512Kx8

512Kx16

512Kx32

1Mx8

1Mx16

1Mx32

2Mx8

2Mx16

2Mx32

4Mx8

4Mx16

4Mx32

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Serial Interface

1. Features

The serial interface (SIO) performs both clock synchronized and start-stop transfers.

2. SIO Functions

2.1 Port Configuration

• Independent transmit and receive circuits

• Double buffer configuration for receive buffer

Because the transmit and receive circuits are independent, start-stop transfers are all full-duplex

communication.

2.2 Transfer Methods

• Start-stop transfer

Data length:

7 bits or 8 bits selectable

Transfer sequence: LSB first

Stop bits:

Parity bit:

Flag bit:

1 bit or 2 bits selectable

No parity, even parity, or odd parity selectable

Enables inter-processor communication using the serial port.

However, cannot be used together with parity bit.

• Clock synchronized transfer

Data length:

8 bits fixed

Transfer sequence: LSB first

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The chart below shows the data format with start-stop transfers.

0

bit0

bit1

bit2 bit3

1

bit4 bit5

bit6

1

7N1

7N2

7F1

7P1

7F2

0

bit0

bit1

bit2 bit3

1

bit4 bit5

bit6 Flag

bit6 Parity

bit6 Flag

1

0

bit0

bit1

bit2 bit3

1

bit4 bit5

1

7P2

0

bit0

bit1

bit2 bit3

1

bit4 bit5

bit6 Parity

1

8N1(*)

bit6

bit7

8N2

8F1

8P1

8F2

8P2

0

bit0

bit1

bit2 bit3

1

bit4 bit5

bit6

1

bit7 Flag

bit7 parity

0

bit0

bit1

bit2 bit3

1

bit4 bit5

bit6

bit7 Flag

bit7 parity

1

Stop bits

Flag/parity

Data size

1: 1 Stop Bit, 2: 2 Stop Bits

N: Non, F: Flag, P: Parity

7: 7 Bits, 8: 8 Bits

(*)After reset the format will be 8 bits, no parity, 1 stop bit.

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2.3 Baud Rate

• Internal baud rate generator

• Clock synchronized transfers

B = f/(8 × n × (256 – P))

Where

B : baud rate (bps)

f : processor (SCP) clock frequency (Hz)

n : baud rate parameter

One of 1, 2, 4, 8, 16, 32, and 64. Selected by SBR’s SBRP field.

(Refer to the register description.)

P : baud rate adjustment value (0 ≤ P ≤ 255)

Set by SBR’s SBRV field. (Refer to the register description.)

At a processor (SCP) clock of 20 MHz, the maximum transfer rate is 2.5 Mbps. At 40 MHz, the maximum transfer

rate is 5 Mbps.

• Start-stop transfers

B = f/(16 × n × (256 – SBR))

Where

B : baud rate (bps)

f : processor (SCP) clock frequency (Hz)

n : baud rate parameter

One of 1, 2, 4, 8, 16, 32, and 64. Selected by SBR’s SBRP field.

(Refer to the register description.)

SBR : baud rate adjustment value (0 ≤ SBR ≤ 255)

Set by SBR’s SBRV field. (Refer to the register description.)

2.4 Error Detection

• Parity errors (start-stop transfers)

A parity error will be detected when a parity bit generated from received data does not match the received parity

bit.

• Framing errors (start-stop transfers)

A framing error will be detected when a received stop bit is "0". When 2 stop bits have been selected, only the first

bit received will be checked.

• Overrun errors (start-stop and clock synchronized transfers)

An overrun error will be detected when the next receive frame's stop bit is detected before the receive buffer has

been read.

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2.5 Interrupts

The SIO is the source of the following interrupts.

• Interrupts

- Receive error interrupt

A receive error interrupt will be generated whenever a parity error, framing error, or overrun error is detected.

- Receive buffer full interrupt

A receive buffer full interrupt will be generated whenever the valid receive data has been transferred to the

receive buffer.

- Transmit buffer empty interrupt

A transmit buffer empty interrupt will be generated whenever the transmit buffer becomes empty.

- Transmit end interrupt

A transmit end interrupt will be generated whenever an SIO data transfer ends.

- Modem status interrupt

A modem status interrupt will be generated whenever a change in a modem control input signal (CTS, DSR) is

detected.

• Interrupt enable/disable

Each interrupt source can be independently enabled or disabled. Also, all interrupts can be disabled at once.

• Interrupt requests

Whenever any of the five interrupts above is enabled and its conditions are fulfilled, the CPU will get an SIO

interrupt request.

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3. SIO Registers

These registers control SIO.

3.1 SIB: SIO Input Buffer

This register holds data that has been input externally. It is undefined after reset.

bit 7

0

SIB

3.2 SOB: SIO Output Buffer

This register holds data to be output externally. It is undefined after reset.

bit 7

0

SOB

3.3 SSTS: SIO Status Register

This register provides SIO status.

bit 15

11 10 9 8 7 6 5 4 3 2 1 0

S S S

O F P

V R T

E E E

S S S S S S S

M O I E R T T

S S S R X X E

0 0 0 0 0

0

I T T I

I

• bit[10] SOVE

0 : No overrun error

1 : Overrun error generated

This bit can only be written with "0". It will be "0" after reset.

• bit[9] SFRE

0 : No framing error

1 : Framing error generated

This bit can only be written with "0". It will be "0" after reset.

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• bit[8] SPTE

ML2110

0 : No parity error

1 : Parity error generated

This bit can only be written with "0". It will be "0" after reset.

• bit[6] SMSI

0 : No modem status interrupt

1 : Modem status interrupt requested

This bit is read-only. It will be "0" after reset.

• bit[5] SOST

0 : Transmit buffer full

1 : Transmit buffer empty

This bit can only be written with "0". It will be "1" after reset.

• bit[4] SIST

0 : Receive buffer empty

1 : Receive buffer full

This bit can only be written with "0". It will be "0" after reset.

• bit[3] SERI

0 : No receive error interrupt

1 : Receive error interrupt requested

This bit is read-only. It will be "0" after reset.

• bit[2] SRXI

0 : No receive buffer full interrupt

1 : Receive buffer full interrupt requested

This bit is read-only. It will be "0" after reset.

• bit[1] STXI

0 : No transmit buffer empty interrupt

1 : Transmit buffer empty interrupt requested

This bit is read-only. It will be "0" after reset.

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• bit[0] STEI

ML2110

0 : No transmit end interrupt

1 : Transmit end interrupt requested

This bit can only be written with "0". It will be "0" after reset.

3.4 SCMD: SIO Command Register

bit 1514131211 10 9 8 7 6 5 4 3 2 1 0

S S S S

S S

R T

E E

N N

S

I

E

N

S S S S

M F F F

O B B L

D M

S

T

P

S

P

T

E R T T

0

R X X E 0

I

Y

E E E E

• bit[15] SREN

0 : Data receive disabled

1 : Data receive enabled

This bit will be "0" after reset.

• bit[14] STEN

0 : Data transmit disabled

1 : Data transmit enabled

This bit will be "0" after reset.

• bit[12] SIEN

0 : Interrupts disabled

1 : Interrupts enabled

This bit will be "0" after reset.

• bit[11] SERIE

0 : Receive error interrupts disabled

1 : Receive error interrupts enabled

This bit will be "0" after reset.

• bit[10] SRXIE

0 : Receive buffer full interrupts disabled

1 : Receive buffer full interrupts enabled

This bit will be "0" after reset.

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• bit[9] STXIE

ML2110

0 : Transmit buffer empty interrupts disabled

1 : Transmit buffer empty interrupts enabled

This bit will be "0" after reset.

• bit[8] STEIE

0 : Transmit end interrupts disabled

1 : Transmit end interrupts enabled

This bit will be "0" after reset.

• bit[6] SMOD

0 : Start-stop transfer mode

1 : Clock synchronized transfer mode

This bit will be "0" after reset.

• bit[5] SFBM

0 : Clear flag bit mode

1 : Set flag bit mode

This bit will be "0" after reset.

• bit[4] SFB

0 : Flag bit value set to "0"

1 : Flag bit value set to "1"

This bit will be "0" after reset.

• bit[3] SFL

0 : Transfer data length is 8 bits

1 : Transfer data length is 7 bits

This bit will be "0" after reset.

• bit[2:1] SPTY

00 : No parity

10 : Even parity

11 : Odd parity

These bits will be "00" after reset.

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• bit[0] SSTP

ML2110

0 : 1 stop bit

1 : 2 stop bits

This bit will be "0" after reset.

3.5 SBR: Baud Rate Adjustment Register

This register sets values that adjust the baud rate.

bit

15

11 10

8 7

0

0 0 0 0 0 SBRP

SBRV

• bit[10:8] SBRP

000 : Baud rate parameter n = 1

001 : Baud rate parameter n = 2

010 : Baud rate parameter n = 4

011 : Baud rate parameter n = 8

100 : Baud rate parameter n = 16

101 : Baud rate parameter n = 32

110 : Baud rate parameter n = 64

These bits will be undefined after reset.

• bit[7:0] SBRV

These bits are the baud rate adjustment value. They will be undefined after reset.

3.6 MSTS: Modem Status Register

This register provides the states of modem signals.

bit

15

1211 10 9

4 3 2 1 0

D D

C D

T S

S R

C D

0 0 0 0 0 0 T S 0 0

S R

0 0 0 0

• bit[11] DCTS

0 : CTS signal has not changed

1 : CTS signal has changed

This bit is read-only. It will be "0" after reset.

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• bit[10] DDSR

ML2110

0 : DSR signal has not changed

1 : DSR signal has changed

This bit is read-only. It will be "0" after reset.

• bit[3] CTS

0 : CTS input signal value = "0"

1 : CTS input signal value = "1"

This bit is read-only. It will be the CTS pin input value after reset.

• bit[2] DSR

0 : DSR input signal value = "0"

1 : DSR input signal value = "1"

This bit is read-only. It will be the DSR pin input value after reset.

3.7 MCMD: Modem Command Register

This register enables/disables modem status interrupts and auto-enable mode, and controls RTS and DTR output

signals.

bit 15

10 9 8 7

S

2 1 0

S

M

R D

0 0 0 0 0 0 T T

S R

A

E

S

0 0 0 0 0 0

I

E N

• bit[9] SMSIE

0 : Disables modem status interrupts

1 : Enables modem status interrupts

This bit will be "0" after reset.

• bit[8] SAEN

0 : Disables auto-enable mode

1 : Enables auto-enable mode

This bit will be "0" after reset.

• bit[1] RTS

0 : Output RTS signal "0"

1 : Output RTS signal "1"

This bit will be "0" after reset.

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• bit[0] DTR

ML2110

0 : Output DTR signal "0"

1 : Output DTR signal "1"

This bit will be "0" after reset.

3.8 SCNT: SIO Control Register

This register controls SIO.

bit

15

0

C

S

T

P

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

• bit[0] CSTP

0 : Enable SIO clock supply

1 : Disable SIO clock supply

This bit will be "0" after reset.

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4. SIO Register Addresses

SIO register addresses for the ML2110 are shown below.

0xFA000000

0xFA000004

0xFA000008

0xFA00000C

0xFA000010

0xFA000014

0xFA000018

0xFA00001C

SIO Input Buffer

SIO Output Buffer

Baud Rate Adjustment Register

SIO Status Register

SIO Command Register

Modem Status Register

Modem Command Register

SIO Control Register

5. SIO Operation

There are two methods of SIO operation: start-stop transfers where communication is performed synchronized to

characters, and clock synchronized transfers where communication is performed synchronized to the clock.

5.1 Clock Synchronized Transfers

Clock synchronized transfer mode is selected by setting the SCMD (Command Register) SMOD bit to "1". In this

mode 8-bit data will be input/output synchronized to the clock output from the SCLK pin.

With clock synchronized transfers, transfer data is only 8 bits, so parity bits and flag bits cannot be

added. The SCMD (Command Register) SFBM bit, SFL bit, and SPTY bits will be set to "0", "0", and

"00" respectively.

5.1.1 Clock Synchronized Transfer Baud Rate

f

B =

8× n × (256 − P)

where

B : baud rate

f : SCP clock frequency

n : baud rate parameter (set by SBR register’s SBRP bit)

P : baud rate adjustment value (set by SBR register’s SBRV bit)

Set SBR (Baud Rate Adjustment Register) to achieve the required baud rate.

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5.1.2 Clock Synchronized Transmit Operation

1) Verify that the SSTS (Status Register) SOST bit is "1", and then write the data to be transferred to

the transmit buffer SOB.

2) Write "0" to SOST to indicate that SOB has valid data.

3) If using SIO interrupts, set the SCMD (Command Register) SIEN bit to "1". If using the transmit buffer empty

interrupt, write "1" to the SCMD STXIE bit. If using the transmit end interrupt, write "1" to the SCMD STEIE bit.

4) If the MCMD (Modem Command Register) SAEN bit is "0", then setting the SCMD (Command Register)

STEN bit to "1" will start the transfer. If the MCMD SAEN bit is "1", then the transfer will start when the SCMD

STEN bit is "1" and the CTS input is "1".

5) SOB (Transmit Buffer) data will be transferred LSB first from the TXD output. Also, a synchronous clock will

be transmitted from the SCLK pin. Data on the TXD output will change synchronous to the falling edge of SCLK.

The receiving device should sample TXD data on the rising edge of SCLK.

6) When the next data can be written to the transmit buffer, the SSTS (Status Register) SOST bit will change from

"0" to "1". If the SCMD (Command Register) STXIE and SIEN bits are "1" at this time, then the SSTS STXI bit

will become "1" and an interrupt request to the CPU will be generated.

7) For continuous transfers, after the SSTS (Status Register) SOST bit becomes "1" write new data to SOB

(Transmit Buffer) and write "0" to the SOST bit.

8) If there is no more data to be transmitted, then write "0" to the SCMD (Command Register) STXIE bit. This will

disable interrupt requests from SIO.

9) When transfer of the eighth bit of data ends, the SSTS (Status Register) SOST bit will become "1" (transmit

buffer SOB is empty), SCLK will stop, and the transmit operation will end. If the SCMD’s STEIE and SIEN bits

are "1" at this time, then the SSTS’s STEI bit will become "1" and an interrupt request to the CPU will be generated.

This interrupt can be released by writing "0" to the SSTS’s STEI bit or the SCMD’s STEIE bit.

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5.1.3 Clock Synchronized Receive Operation

1) The receive operation will begin if the MCMD’s SAEN bit is "0" (auto-enable mode disabled) and the SCMD’s

SREN bit is "1" (data receive enabled).

2) When the receive operation begins, a synchronous clock will be output from SCLK.

3) If using SIO interrupts, set SCMD’s SIEN bit to "1". If using the receive buffer full interrupt, set SCMD’s

SRXIE bit to "1".

4) The transmitting device should input the data to be transferred on RXD on the falling edge of SCLK, LSB first.

The SIO will sample RXD data on SCLK’s rising edge, shifting it into the Receive Shift Register.

5) When the eighth bit of data has been received, the receive shift register’s data is transferred to SIB.

However, it will not be transferred to SIB if an overrun error occurs.

6) After data has transferred from the receive shift register to the receive buffer SIB, SIST will change from "0" to

"1", indicating that there is valid data in the receive buffer SIB. If SCMD’s SRXI bit and SIEN bit are both "1" at

this time, an interrupt request to the CPU will be generated.

7) To continue receiving data, read the SIB data after SIS becomes "1", and then write "0" to SIST.

8) To end the receive operation, write "0" to SCMD’s SREN bit. At the time "0" is written to SREN, data currently

being received will be transferred to SIB and the receive operation will end.

9) When SSTS’s SIST bit is "1" and the SIO enters the state in which data is ready to be transferred from the

receive shift register to the receive buffer, the SIO will assume that an overrun error (receipt of further data before

the value of the receive buffer SIB is read) has occurred.

SSTS’s SOVE bit will then be set to "1". In this case the receive shift register value will not be transferred to the

receive buffer SIB. If SCMD’s SERIE bit and SIEN bit are "1", then SSTS's SERI bit will be set to "1" and an

interrupt request to the CPU will be generated. To release the interrupt, write "0" to SSTS’s SOVE bit or to

SCMD’s SERIE or SIEN bit.

Start-Stop Transfers

Start-stop transfer mode is selected by setting the SCMD (Command Register) SMOD bit to "0". In this mode data

is output LSB first from TXD, and input LSB first from RXD.

5.2.1 Start-Stop Transfer Baud Rate

f

B =

16× n × (256 − P)

where

B : baud rate

f : SCP clock frequency

n : baud rate parameter (set by SBR register’s SBRP bit)

P : baud rate adjustment value (set by SBR register’s SBRV bit)

Set SBR (Baud Rate Adjustment Register) to achieve the required baud rate.

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5.2.2 Start-Stop Transmit Operation

1) Verify that the SSTS (Status Register) SOST bit is "1", and then write the data to be transferred to the transmit

buffer SOB. Next write "0" to SOST to indicate that SOB has valid data.

2) If the MCMD (Modem Command Register) SAEN bit is "0", then setting the SCMD (Command Register)

STEN bit to "1" will start the transfer. If the MCMD SAEN bit is "1", then the transfer will start when the SCMD

STEN bit is "1" and the CTS input is "1".

3) For start-stop transmit operation, a start bit "0" will be output from TXD. Then the data written in SOB will be

output LSB first. If SCMD’s SFL bit is "0", then 8 bits of data will be output. If the SFL bit is "1", then 7 bits will

be output.

4) When SCMD (Command Register) SFBM bit is "0", a parity bit will be output after the SOB data.

The parity will be even if the SPTY field is "10", and odd if the SPTY field is "11". If SCMD’s SFBM bit is "1" and

SPTY is "00", then the value set in SCMD’s SFB bit will be output after the SOB data.

If SCMD’s SFBM bit is "0" and the SPTY field is "0", then neither a parity bit nor flag bit will be output after SOB

data.

5) Finally, one stop bit will be output if the SCMD (Command Register) SSTP bit is "0", or two stop bits will be

output if the SSTP bit is "1". This will end the transfer of one frame of data.

6) When the next data can be written to the transmit buffer, the SSTS (Status Register) SOST bit will change from

"0" to "1". If the SCMD (Command Register) STXIE and SIEN bits are "1" at this time, then the SSTS STXI bit

will become "1" and an interrupt request to the CPU will be generated.

7) For continuous transfers, after the SSTS (Status Register) SOST bit becomes "1" write new data to SOB

(Transmit Buffer) and write "0" to the SOST bit. This will disable interrupt requests from SIO.

8) If there is no more data to be transmitted, then write "0" to the SCMD (Command Register) STXIE bit. The will

disable interrupt requests from SIO.

9) When transfer of the stop bit ends, the transmit operation will end if the SOST bit is "1". If the SCMD's STEIE

and SIEN bits are "1" at this time, then the SSTS's STEI bit will become "1" and an interrupt request to the CPU

will be generated. This interrupt can be released by writing "0" to the SSTS's STEI bit or the SCMD's STEIE or

SINT bit.

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5.2.3 Start-Stop Receive Operation

1) The receive operation can begin if the MCMD’s SAEN bit is "0" and the SCMD’s SREN bit is "1".

SCMD’s SRXIE bit to "1". If using the receive error interrupt, set SCMD’s SERIE bit to "1".

2) The SIO receive operation will start when a falling edge is detected on RXD. The first bit of data is received as

the start bit. If the received value is "1", then it will not be recognized as a start bit, the receive operation will be

suspended, and the device will wait for another RXD falling edge to be detected. If the received value is "0", then

data will continue to be received.

3) When the start bit is received, receive of data will start. If SCMD’s SFL bit is "0", then 8 bits of data will be

input serially into the receive shift register. If the SFL bit is "1", then 7 bits of data will be input.

4) When SCMD (Command Register) SFBM bit is "0", a parity bit will be received after the data. The parity will

be even if the SPTY field is "10", and odd if the SPTY field is "11". If SCMD’s SFBM bit is "1" and SPTY is "00",

one flag bit will be received. If SCMD’s SFBM bit is "0" and the SPTY field is "00", then neither a parity bit nor

flag bit will be received.

5) Finally one stop bit will be received. Even if SCMD’s SSTP bit is "1", only the first stop bit will be received.

6) When all bits have been received, the data input in the receive shift register will be transferred to the receive

buffer SIB. However, if either of the following two conditions applies, then data will not be transferred to SIB, and

SIB will retain its previous value.

1. SCMD’s SFBM bit is "1", its SPTY field is "00", and the received flag bit does not match SCMD’s SFB bit.

2. An overrun error occurred.

7) When data has been transferred from the receive shift register to the receive buffer SIB, SSTS’s SIST will

change from "0" to "1". If SCMD’s SRXIE and SIEN bits are both "1", then SSTS’s SRXI bit will become "1" and

an interrupt request to the CPU will be generated. To release the interrupt, write "0" to SSTS’s SIST bit or to

SCMD’s SRXIE or SIEN bit.

8) When SSTS’s SIST bit is "1" and the SIO enters the state in which data is ready to be transferred from the

receive shift register to the receive buffer, the SIO will assume that an overrun error (receipt of further data before

the value of the receive buffer is read) has occurred. SSTS’s SOVE bit will then be set to "1".

9) If the received stop bit is "0", then it will be considered indication of a framing error. SSTS’s SFRE bit will then

be set to "1".

10) When SCMD’s SPTY field is "10" or "11", a mismatch between parity generated from the receive data and the

parity bit will be considered a parity error. SSTS’s SPTE bit will then be set to "1".

11) If one or more of the SOVE, SFRE, and SPTE bits are "1" and the SCMD' s SERIE and SIEN bits are "1", then

SSTS's SERI bit will be set to "1" and an interrupt request to the CPU will be generated.

12) To release the interrupt for any error, write "0" to all of SSTS’s SOVE, SFRE, and SPTE bits, or write "0" to

SCMD’s SERIE or SIEN bits.

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Parallel Interface

1. Features

The parallel interface (PIO) inputs and outputs 8-bit wide parallel data. It has three data transfer

methods: software control mode where input/output is specified with 1-bit ports, handshake

control mode through strobe/acknowledge signals and flags indicating buffer status, and bus

control mode through read/write signals.

2. PIO Functions

2.1 PIO Data Size

• 8 bits

2.2 PIO Control Modes

• Software control mode

In software control mode, the PIO controls input and output of bits in accordance with the value

written in the direction register. If a direction register bit is "0", then the corresponding pin level will

be an input. If "1", then the value in the corresponding output buffer will be output to the pin.

• Handshake control mode

In handshake control mode, the PIO inputs external data through a handshake using a strobe signal

(PSTB) and input buffer full signal (PIBF). It outputs data externally through a handshake using an

output buffer full signal (POBF) and acknowledge signal (PACK).

• Bus control mode

In bus control mode, the PIO controls data input/output with a chip select signal (PCS), flag/buffer

select signal (PIOA), read signal (PACK), and write signal (PSTB).

2.3 PIO Interrupts

Interrupts to the CPU core are available when handshake control mode or bus control mode is

selected.

• Input buffer full interrupts

When PCMD’s PIEN bit is "1", writing "0" to the PIIE bit will disable input buffer full interrupts, and

writing "1" will enable them. When the PIEN bit is "0", input buffer full interrupts will be disabled

regardless of the value of the PIIE bit.

If input buffer full interrupts are enabled, then one will be generated whenever the input buffer is

written from an external device.

To release input buffer full interrupts, write "0" to the status register PSTS’s PIST bit, to the command

register PCMD’s PIIE bit, or to PCMD’s PIEN bit.

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• Output buffer empty interrupts

When PCMD’s POENbitis"1", writing"0"tothe POIE bit will disable output buffer empty interrupts,

and writing "1" will enable them. When the POEN bit is "0", output buffer empty interrupts will be

disabled regardless of the value of the POIE bit.

If output buffer empty interrupts are enabled, then one will be generated whenever the output buffer

is read by an external device.

To release output buffer empty interrupts, write "0" to the status register PSTS’s POST bit, to the

command register PCMD’s POIE bit, or to PCMD’s POEN bit.

PIO Registers

These registers control the PIO.

3.1 PIB: PIO Input Buffer

This buffer saves data input from an external device. It will be undefined after reset.

bit 7

0

PIB

3.2 POB: PIO Output Buffer

This buffer saves data to be output to an external device. It will be undefined after reset.

bit 7

0

POB

3.3 PDIR: PIO Direction Register

This register specifies under software control whether each parallel port bit is input or output. It will

be "00000000" after reset.

bit 7

0

PDIR

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3.4 PSTS: PIO Status Register

This register provides the PIO status.

bit

7 6 5 4 3 2 1 0

P

I

N

T

I

P

I

N

T

P

A

C

K

P

O

S

T

P

S

T

B

P

I

0 0

S

T

O

• bit[5] PINTI

0 : No input buffer full interrupt

1 : Input buffer full interrupt occurred

This bit will be "0" after reset.

• bit[4] PINTO

0 : No output buffer empty interrupts

1 : Output buffer empty interrupt occurred

This bit will be "0" after reset.

• bit[3] PACK

0 : No acknowledge

1 : Acknowledge

This bit will be undefined after reset.

• bit[2] POST

0 : Output buffer full

1 : Output buffer empty

This bit can only be written with "0". It will be "1" after reset.

• bit[1] PSTB

0 : No strobe

1 : Strobe

This bit will be undefined after reset.

• bit[0] PIST

0 : Input buffer empty

1 : Input buffer full

This bit can only be written with "0". It will be "0" after reset.

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3.5 PCMD: PIO Command Register

This register specifies the parallel port mode and specifies whether interrupts are enabled or

disabled. It will be "00000000" after reset.

bit 7 6 5 4 3 2 1 0

P

M

O

D

P P

O I

E E

N N

P P

O I

0 0

I

E E

• bit[7:6] PMOD

00 : Bus control mode

01 : Handshake control mode

1x : Software control mode

• bit[5] POEN

0 : Output operation disabled

1 : Output operation enabled

• bit[4] PIEN

0 : Input operation disabled

1 : Input operation enabled

• bit[1] POIE

0 : Output buffer empty interrupts disabled

1 : Output buffer empty interrupts enabled

• bit[0] PIIE

0 : Input buffer full interrupts disabled

1 : Input buffer full interrupts enabled

4. PIO Register Addresses

For the ML2110, PIO register addresses are listed below.

0xFB000000

0xFB000004

0xFB000008

0xFB00000C

0xFB000010

PIO Input Buffer

PIO Output Buffer

PIO Direction Register

PIO Status Register

PIO Command Register

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5. PIO Operation

5.1 Software Control Mode

In software control mode data input/output and control signals are all controlled by software.

5.1.1 Data Input from External Device

1) Write "1x" to the PCMD (Command Register) PMOD bits ("x" indicates that either "0" or "1" is acceptable).

2) Read the input buffer PIB to read the parallel port’s pin levels at that time.

5.1.2 Data Output to External Device

1) Write "1x" to the PCMD (Command Register) PMOD bits ("x" indicates that either "0" or "1" is acceptable).

2) Write a value to the output buffer POB.

3) Write "1" to the bits in PDIR (Direction Register) that correspond to parallel port pins that will be outputs. This

starts to drive the parallel port for data to be output.

4) If "0" is written to any bits in PDIR, then the corresponding parallel port pins will stop being driven.

5.2 Handshake Control Mode

In handshake control mode data input is controlled by handshake using a strobe (PSTB), input buffer

full (PIBF), acknowledge (PACK), and output buffer full (POBF) for input/output.

5.2.1 Data Input from External Device

(A) SCP operation

1) Write "01" to the PCMD (Command Register) PMOD bits. Also write "1" to PCMD’s PIEN bit to enable input

operation.

2) When data is written to the input buffer PIB from the external device, the PSTS (Status Register) PIST bit will

become "1" to indicate that there is valid data in PIB. When PSTS’s PIST bit becomes "1", the input buffer full

output (PIBF) will become "1".

3) If PSTS’s PIST bit is "1" and input buffer full interrupts have been enabled (PCMD’s PIIE bit is "1"), then a PIO

interrupt to the CPU core will be generated.

4) The CPU core verifies that PSTS’s PIST bit is "1" in the PIO interrupt vector process routine and reads the input

buffer PIB. It then writes "0" to PSTS’s PIST bit to release the interrupt.

5) When PSTS’s PIST bit becomes "0", the input buffer full output (PIBF) also becomes "0".

6) Repeat the operation from step 2).

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(B) External operation

1) Verify that the input buffer full output (PIBF) is "0".

2) Drive the parallel input/output bus (PD[7:0]) with input data.

3) Set the strobe input (PSTB) to "1". This writes the data to the input buffer PIB.

4) When the input buffer full output (PIBF) becomes "1", stop driving the parallel input/output bus and set the

strobe input (PSTB) to "0".

5) Repeat the operation from step 1).

5.2.2 Data Output to External Device

(A) SCP operation

1) Write "01" to the PCMD (Command Register) PMOD bits. Also write "1" to PCMD’s POEN bit to enable

output operation.

2) Verify that the PSTS (Status Register) POST bit is "1", indicating that the output buffer POB is empty.

3) Write data to the output buffer POB.

4) Write "0" to PSTS’s POST bit. When POST becomes "0", the output buffer full output (POBF) will become

"1".

5) If PSTS’s POST bit is "1" and output buffer full interrupts have been enabled (PCMD’s POIE bit is "1"), then a

PIO interrupt to the CPU core will be generated. This interrupt will be released by writing "0" to PSTS’s POST bit

or writing "0" to PCMD’s POIE bit.

6) Write data to the output buffer POB and repeat the operation from step 4).

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(B) External operation

1) Verify that the output buffer full output (POBF) is "1".

2) Set the acknowledge input (PACK) to "1". When the acknowledge input is set to "1", the PIO will output the

value of the output buffer (POB) to the parallel input/output bus (PD[7:0]).

3) Verify that the output buffer full output (POBF) is "0".

4) Read the value on the input/output bus.

5) Set the acknowledge input (PACK) to "0". When the acknowledge input becomes "0", the PIO will stop driving

the input/output bus.

6) Repeat the operation from step 1).

5.3 Bus Control Mode

In bus control mode data input/output is controlled externally by the chip select input (PCS), flag/buffer select

input (PIOA), read input (PACK), and write input (PSTB).

(A) SCP operation

1) Write "00" to the PCMD (Command Register) PMOD bits. Also write "1" to PCMD’s PIEN bit to enable input

operation.

2) When an external device writes data to the input buffer PIB, the PSTS (Status Register) PIST bit will become

"1", indicating that there is valid data in the input buffer PIB.

3) If PCMD’s PIIE bit is "1", then a PIO interrupt to the CPU core will be generated.

4) The CPU core verifies that PSTS’s PIST bit is "1" in the PIO interrupt vector process routine and reads the input

buffer PIB. It then writes "0" to PSTS’s PIST bit to release the interrupt.

5) Repeat the operation from step 2).

(B) External operation

1) Read the input buffer full output (PIBF).

Chip select input

Flag/buffer select input

Read input

PCS

0

1

PIOA

PACK

PSTB

Write input

2) Verify that the input buffer full output (PIBF) is "0".

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3) Write data to the input buffer (PIB).

Chip select input

Flag/buffer select input

Read input

PCS

0

1

0

PIOA

PACK

PSTB

Write input

Input/output bus

PD[7:0] Write data

4) Repeat the operation from step 1).

5.3.2 Data Output to External Device

(A) SCP operation

1) Write "00" to the PCMD (Command Register) PMOD bits. Also write "1" to PCMD’s POEN bit to enable

output operation.

2) Verify that the PSTS (Status Register) POST bit is "1", indicating that the output buffer POB is empty.

3) Write data to the output buffer POB.

4) Write "0" to PSTS’s POST bit. When POST is "0", the output buffer full output (POBF) will become "1".

5) When POST becomes "1" and PCMD’s POIE bit is "1", then a PIO interrupt to the CPU core will be generated.

This interrupt will be released by writing "0" to PSTS’s POST bit or by writing "0" to PCMD’s POIE bit.

6) Repeat the operation from step 3).

(B) External operation

1) Read the output buffer full output (POBF).

Chip select input

Flag/buffer select input

Read input

PCS

0

1

PIOA

PACK

PSTB

Write input

2) Verify that the output buffer full output (POBF) is "1".

3) Read the output buffer (POB).

Chip select input

Flag/buffer select input

Read input

PCS

0

1

0

1

PIOA

PACK

PSTB

Write input

Input/output bus

PD[7:0] Read data

4) When the output buffer is read, PSTS's POST bit will become "1".

5) Repeat the operation from step 1).

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Timer Unit

1. Features

The timer unit (TMR) is a 16-bit programmable timer. It has two modes: an interval timer mode

which requests interrupts to the CPU core, and a clock division mode which generates a 50% duty,

frequency divided clock.

2. TMR Functions

2.1 Counter

• 16-bit up counter

2.2 Counter Clock Period

• φ (SCP operating frequency × 1)

• 4φ (SCP operating frequency × 4)

• 16φ (SCP operating frequency × 16)

• 64φ (SCP operating frequency × 64)

2.3 Interval Timer Interrupts

When the counter overflows (counter value changes from 0xFFFF to 0x0000), it will request an

interrupt to the CPU core.

2.4 Divided Clock Generation

When the counter overflows (counter value changes from 0xFFFFto0x0000),it will invert the value

currently being output.

3. TMR Registers

3.1 TIR: Timer Initial Value Register

This register saves the counter’s initial value. When this register is written, the same value will be

written to the Timer Value Register (TCR). This register will be undefined after reset.

bit 15

0

TIR

3.2 TCR: Timer Value Register

This register provides the counter’s current value. It will be undefined after reset.

bit 15

0

TCR

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3.3 TSTS: Timer Status Register

This register provides TMR status.

bit

7

1 0

T

D

A

T

C

A

0 0 0 0 0 0

• bit[1] TDAT

0 : No timer interrupt request occurred (interval timer mode)

Divided clock output is "0" (divided clock mode)

1 : Timer interrupt request occurred (interval timer mode)

Divided clock output is "1" (divided clock mode)

• bit[0] TCA

0 : Timer counter operation is suspended

1 : Timer counter is operating

3.4 TCMR: Command Register

This register sets TMR operation.

bit 7 6 5 4 3 2 1 0

T T

T

C 0

G

T

C

S

M C

O A

D I

0 0

• bit[7] TCG

0 : Disable timer counter operation

1 : Enable timer counter operation

This bit will be "0" after reset.

• bit[5] TMOD

0 : Interval timer mode

1 : Divided clock mode

This bit will be "0" after reset.

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• bit[4] TCAI

ML2110

0 : Disable auto-initialization of timer value register

1 : Enable auto-initialization of timer value register

This bit will be "0" after reset.

• bit[1:0] TCS

00 : Count clock Φ

01 : Count clock 4 Φ

10 : Count clock 16 Φ

11 : Count clock 64 Φ

These bits will be "00" after reset.

4. TMR Register Addresses

The ML2110 has two timers. The register addresses for each are listed below.

TMR1 Timer Initial Value Register

Timer Value Register

0xF8000000

0xF8000004

0xF8000008

0xF800000C

0xF8000010

0xF8000014

0xF8000018

0xF800001C

Timer Status Register

Timer Command Register

TMR2 Timer Initial Value Register

Timer Value Register

Timer Status Register

Timer Command Register

5. TMR Operation

5.1 Interval Timer Mode

In interval timer mode counting begins from the value set in the Timer Initial Value Register, and a

timer interrupt is generated to the CPU when the counter overflows.

1) Set the TCMR (Command Register) TCG bit to "0", disabling counting.

2) Set TCMR’s TCS bits to select the counter’s increment clock.

3) Set TCMR’s TMOD bit to "0", setting interval timer mode as the operating mode

4) To generate periodic interrupts set TCMR’s TCAI bit to "1", which will set the counter to be loaded with the

value of the Timer Initial Value Register each time the counter overflows. For a one-shot interrupt set the TCAI bit

to "0".

5) Set the timer’s initial value in the Timer Initial Value Register TIR. Writing to this register will simultaneously

write the same value to the Timer Value Register TCR.

6) Write "1" to TCMR’s TCG bit to start counting. An interrupt will be generated when the counter overflows.

7) To release the interrupt set the TSTS (Status Register) TDAT bit to "0" in software.

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5.2 Divided Clock Mode

In divided clock mode counting begins from the value set in the Timer Initial Value Register, and the divided clock

output value inverts when the counter overflows.

1) Set the TCMR (Command Register) TCG bit to "0", disabling counting.

2) Set TCMR’s TCS bits to select the counter’s increment clock.

3) Set TCMR’s TMOD bit to "1", setting divided clock mode as the operating mode.

4) To generate a periodic divided clock set TCMR’s TCAI bit to "1", which will set the counter to be loaded with

the value of the Timer Initial Value Register each time the counter overflows. For a one-shot divided clock set the

TCAI bit to "0".

5) Set the timer’s initial value in the Timer Initial Value Register TIR. Writing to this register will simultaneously

write the same value to the Timer Value Register TCR.

6) Write "1" to TCMR’s TCG bit to start counting and generating a divided clock.

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Speech Data Registers

1. Features

This is a register group and control circuit used for speech output.

2. Speech Data Registers Functions

2.1 Speech Output Registers

These are 12-bit registers that store speech output data. There are two registers and one output

register configured to operate at the speech sampling frequency.

Use of two registers reduces the frequency of interrupt generation during waveform output, which

lightens the CPU load. The output stage is provided in the register, which corrects the inaccuracies

in the sampling frequencies that are caused by interrupts.

DATA

CLK

Interrupt to

D WR CPU

TMR2 output

12-bit REG

(DAREG1)

12-bit REG

(DAREG2)

1

1/2

12-bit REG

(DAREGO)

DAC

The two registers are in parallel, continuously written with D/A conversion data. The output

register reads the data from the two registers alternately in every sampling cycle.

The output level registers' clock is generated by TMR2. This clock is multiplied by 1/2 to output

interrupt signals. The interrupt signals are used to write the waveform output data to the speech

output registers.

Note the following when the MSM7576 mode (described later) is not used when using the speech

output registers :

– The TMR2 must be set to the divided clock mode.

– To write data to DAC1 and DAC2, write to DAC2 first, then DAC1.

– Do not clear the status register of the TMR2. If it is cleared by an interrupt routine, the sampling

frequency for the speech output will change.

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TMR2 output

0xxxx

0x0001

DAREG0

DAREG1

DAREG2

0x0002

0x0003

0x0002

0x0001

0x0000

Interrupt to

CPU

2.2 MSM7576 Mode

This mode forces operation to be the sameasMSM7576operation. Interrupt signalsfromTMR2are

output directly as interrupts to the CPU.

DATA

CLK

TMR2 output

Interrupt to CPU

12-bit REG

DAC

2.3 Digital Signal Output

There are 16-bit registers that store digital signal output data. There are two registers and one output register.

Use of two registers reduces the frequency of interrupt generation during digital signal output, which lightens

the CPU load.

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DATA

CLK

Interrupt to

D WR CPU

XSYNC

16-bit REG

(ULAW_REG1)

(ULAW_REG2)

1

1/2

16-bit REG

(DOUT_REG)

Shifter

DOUT

BCLK

The two registers are in parallel, continuously written with digital signal output data. The output register

reads the data from the two registers alternately in XSYNC.

The output register’s clock is XSYNC. This clock is multiplied by 1/2 to output interrupt signals. The interrupt

signals are used to write the digital signal output data to two registers.

Interrupt to CPU

(XSYNC/2,CLKA synchronous)

ULAW_REG1

ULAW_REG2

0x0003

0x0002

0x0001

0x0000

XSYNC

0xxx

0x0000

0x0001

0x0002

DOUT_REG

DOUT

0xxx

0x0002

0x0000

0x0001

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3. Speech Data Registers Details

3.1 DAC1: Speech Output Register 1

This register stores speech output data. It will be "000000000000" after reset.

bit 15

1211

0

0 0 0 0

DAC1

3.2 DAC2: Speech Output Register 2

This register stores speech output data. It will be "000000000000" after reset.

bit 15

1211

0

0 0 0 0

DAC2

3.3 DACO: D/A Conversion Register

This register stores data to be input to the D/A converter. It will be "000000000000" after reset.

bit 15

1211

0

0 0 0 0

DACO

3.4 USTAT: Status Register

This register indicates whether or not the speech output registers/circuits have generated an

interrupt to the CPU.

Writing "0" to this register releases the interrupt from the speech output registers/circuits. In

MSM7576 mode USTAT will become "0" when the TMR2 interrupt is released.

bit 7

2

1 0

0 0 0 0 0 0

• bit[1] ULAWINT: Interrupt during digital signal output.

• bit[0] USTAT: Interrupt during speech data output with D/A converter.

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3.5 UPORT: General Register

This is a general register. It will be "0" after reset.

9 8 7

1 0

bit 15

0 0 0 0 0 0 0

3.6 UCOM: Command Register

This register sets operation mode of speech data register control.

bit 7

4

0

0 0 0 0 0

• bit[2]: DOINT

This is allows interrupts during digital signal output.

0: Interrupt disable

1: Interrupt signal output

• bit[1]: DADO

This bit switches speech output with D/A converter or digital signal output.

0: Speech output with D/A converter

1: Digital signal output

• bit[0]: MODE7576 This bit sets MSM7576 mode.

3.7 ULAWREG1: Digital Signal Output Register 1

This register stores digital signal output data. It will be “0000000000000000” after reset.

0

bit 15

ULAWREG1

3.8 ULAWREG2: Digital Signal Output Register 2

This register stores digital signal output data. It will be “0000000000000000” after reset.

0

bit 15

ULAWREG2

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4. Speech Output Registers Address Configuration

The addresses used by the speech output registers/circuits are assigned at 0x80000000. Accesses to

this space will be 3τ access.

Speech Output Register 1

Speech Output Register 2

D/A Conversion Register

Status Register

Command Register

General Register

Digital Signal Output Register 1

Digital Signal Output Register 2

Digital Signal Output Register

DAC1

DAC2

DACO

USTAT

0x80000000

0x80000004

0x80000008

0x8000000C

0x80000010

0x80000020

0x80000014

0x80000018

0x8000001C

UCOM

UPORT

ULAWREG1

ULAWREG2

DOUTREG

Speech Output

1. Output Waveform from DAO1

The speech output pin directly outputs the output of the DA converter.

The output waveform from DAO1 will be a staircase synchronized to the sampling frequency.

Maximum output amplitude will be (4095/4096 × V_DD).

2. Output Filter

Because the output from DAO1 is a staircase described above, add a low-pass filter. The diagram

below shows a reference circuit for a Butterworth low-pass filter.

1200p

R

2200p

R

0.1µ

R

2

3

1

-

15

14

R

11

12

-

4

10

8

+

6

7

9

16

+

-

+

5

1K

13

+

300p

1000p

220p

1K

MC14573P

Butterworth low-pass filter

R=47k, f=4.8kHz (95 model: for 12kHz sampling)

R=36k, f=6.4kHz (96 model: for 16kHz sampling)

R=27k, f=9.6kHz (97 model: for 22kHz sampling)

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Oscillation Circuit

There are two methods to generate the ML2110 system clock: adding an external crystal oscillator

or supplying an external clock.

1. Crystal Oscillator

The diagram below shows a connection example for a crystal oscillator.

22pF

ML2110

CLK

Crystal

1MΩ

22pF

XO

GND

2. External Clock

The diagram below shows an example using an external clock.

ML2110

External Clock

CLK

XO

Open

The external clock is input on the CLK pin. Leave the XO pin open.

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SYSTEM CONFIGURATION EXAMPLE

From page 96 to page 98 is indicated the circuit diagram of a text-to-speech printed circuit board conforming to

ISA for PCs that uses the ML2110.

P R

C L

1 0

1 3

1 4

7

1 4

7

1 4

7

P R

C L

4

1

1 4

7

1 4

7

1 4

7

1 4

7

1

2

1

2

1

2

1

2

1 4

7

1

2

G

2

1

3

2

1

2

1

2

1

G

2

G

2

1

2

1

2

1

2

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3

1

9

4

1 3

G N D

9

G N D

6

9

V C C

7

4

1 3

1

2

8

4

1 3

1

2

1

2

8

4

1 3

G N D

1 4 3

1 3 4

1 3 3

1 2 1

1 0 8

9 3

7 9

6 5

5 1

3 7

2 3

9

V D D

1 4 0

1 3 7

1 2 8

1 1 4

1 0 0

8 6

7 2

5 8

4 4

3 0

1 6

7

6

8

A V D D

1

A G N D

3

1

2

1

2

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PACKAGE DIMENSIONS

(Unit: mm)

LQFP144-P-2020-0.50-K

Mirror finish

Package material

Lead frame material

Pin treatment

Package weight (g)

Rev. No./Last Revised

Epoxy resin

42 alloy

Solder plating (≥5µm)

1.37 TYP.

5

5/Nov. 28, 1996

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity

absorbed in storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product

name, package name, pin number, package code and desired mounting conditions (reflow method,

temperature and times).

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REVISION HISTORY

Page

Previous Current

Document

No.

Date

Description

Edition

Version 1

Dec. 2000

Apr. 2001

–

Version 1

Preliminary first edition

–

3

–

3

PEDL2110-01

Partially changed the pin configuration.

Changed as follows:

• The Max. value of Parameter “Dynamic

Supply Current” from 120 to 150 according to

a change of the condition.

6

• Symbol “|V_DAE|” from V_DAEto |V_DAE|.

Changed the Min. and Max. values from 25 and

50 to 20 and 33, respectively, by a change of

Parameter “Source Oscillation Period” to

“Source Oscillation Frequency”.

Changed as follows:

• The Min. value of Parameter “Operating

Period” from 25 to 30.

• The Max. value of Parameter “A Delay Time”

from 22 to 29.

• The Min. value of Parameter “D Setup Time”

from 2 to 10.

7

• The Min. value of Parameter “D Hold Time”

from 6 to 2.

• The Max. value of Parameter “D Delay Time”

from 25 to 32.

• The Min. value of Parameter “RD Delay Time”

from 20 to 25.

• The Max. value of Parameter “UPORT Delay

Time” from 20 to 23.

Changed the Max. values of Parameters “ROM

Delay Time” and “SRAM Delay Time” from 20 +

FEDL2110-01

Mar. 25, 2002

8

9

8

9

0.5 t_CYCto 21 + 0.5 t_CYC

.

Changed as follows:

• The Max. value of Parameter “RAS Delay

Time” from 18 to 24.

• The Max. value of Parameter CAS Delay

Time” from 18 + 0.5 t_CYCto 22 + 0.5 t_CYCand

from 18 to 22.

• The Max. value of Parameter “WE Delay

Time” from 20 to 23.

Changed the Max. Value of Parameter “AS

Delay Time” from 18 to 27.

Changed as follows:

• The Max. value of Parameter “RTS Delay

Time” from 20 to 22

12

• The Max. value of Parameter “TXD Delay

Time” from 20 to 21.

• The Max. value of Parameter “DTR Delay

Time” from 20 to 23

13

71

–

13

70

Added Note.

Changed the field names in the MCMD register

of Section 3.7.

96 to 98 Added the circuit diagrams.

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NOTICE

1. The information contained herein can change without notice owing to product and/or technical improvements.

Before using the product, please make sure that the information being referred to is up-to-date.

2. The outline of action and examples for application circuits described herein have been chosen as an

explanation for the standard action and performance of the product. When planning to use the product, please

ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.

3. When designing your product, please use our product below the specified maximum ratings and within the

specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating

temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation

resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or

unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified

maximum ratings or operation outside the specified operating range.

5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is

granted by us in connection with the use of the product and/or the information and drawings contained herein.

No responsibility is assumed by us for any infringement of a third party’s right which may result from the use

thereof.

6. The products listed in this document are intended for use in general electronics equipment for commercial

applications (e.g., office automation, communication equipment, measurement equipment, consumer

electronics, etc.). These products are not authorized for use in any system or application that requires special

or enhanced quality and reliability characteristics nor in any system or application where the failure of such

system or application may result in the loss or damage of property, or death or injury to humans.

Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace

equipment, nuclear power control, medical equipment, and life-support systems.

7. Certain products in this document may need government approval before they can be exported to particular

countries. The purchaser assumes the responsibility of determining the legality of export of these products

and will take appropriate and necessary steps at their own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.

101/101


型号：	ML2110TC
厂家：	OKI ELECTRONIC COMPONETS
描述：	Speech Control Processor 语音控制处理器消费电路商用集成电路
文件：	总101页 (文件大小：531K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML2110TC [OKI]

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