XC9850VF [NXP]
500MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100, MAPBGA-100;
| 型号： | XC9850VF |
| 厂家： | 
NXP |
| 描述： | 500MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100, MAPBGA-100 时钟 外围集成电路 晶体 |
| 文件： | 总12页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MOTOROLA
Order number: XC9850
Rev 0, 07/2004
SEMICONDUCTOR TECHNICAL DATA
Clock Generator for PowerQUICC III
XC9850
The XC9850 is a PLL based clock generator specifically designed for
Motorola Microprocessor And Microcontroller applications including the
PowerQUICC III. This device generates a microprocessor input clock plus the
500 MHz Rapid I/O clock. The microprocessor clock is selectable in output
frequency to any of the commonly used microprocessor input and bus
frequencies. The Rapid I/O outputs are LVDS compatible. The device offers
eight low skew clock outputs organized into two output banks, each
configurable to support different clock frequencies. The extended temperature
range of the XC9850 supports telecommunication and networking
requirements.
MICROPROCESSOR
CLOCK GENERATOR
Features
•
•
•
•
•
8 LVCMOS outputs for processor and other circuitry
2 differential LVDS outputs for Rapid I/O interface
Crystal oscillator or external reference input
25 or 33 MHz Input reference frequency
Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83,
66, 50, 33 or 16 MHz
VF SUFFIX
VM SUFFIX (Pb-FREE)
100 MAPBGA PACKAGE
CASE 1462-01
•
•
•
•
•
•
•
•
Buffered reference clock output
Rapid I/O (LVDS) Output = 500, 250 or 125 MHz
Low cycle-to-cycle and period jitter
100-lead PBGA package
100-lead Pb-free Package Available
3.3V supply with 3.3V or 2.5V output LVCMOS drive
Supports computing, networking, telecommunications applications
Ambient temperature range –40°C to +85°C
Functional Description
The XC9850 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency is
selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers, divide
this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60 or 120 to produce output frequencies of 200, 166, 133, 125, 111, 100, 83 66
50 33 or 16 MHz. The single-ended LVCMOS outputs are divided into two banks of 4 low skew outputs each, for use in driving a
microprocessor or microcontroller clock input as well as other system components. The 2 GHz PLL output frequency is also divided
to produce a 125, 250 or 500 MHz clock output for Rapid I/O applications such as found on the PowerQUICC III communications
processor. The input reference, either crystal or external input is also buffered to a separate output that my be used as the clock source
for a Gigabit Ethernet PHY if desired.
The reference clock may be provided by either an external clock input of 25 MHz or 33 MHz. An internal oscillator requiring a 25
MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and selected
via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal oscillator or
external clock input is selected via the input pin of REF_SEL. Other than the crystal, no external components are required for crystal
oscillator operation. The REF_33MHz configuration pins is used to select between a 33 and 25 MHz input frequency.
The XC9850 is packaged in a 100 lead MAPBGA package to optimize both performance and board density.
For More Information On This Product,
© Motorola, Inc. 2004
Go to: www.freescale.com
Freescale Semiconductor, Inc.
XC9850
0
1
CLK
1
0
0
PCLK
PCLK
÷N
QA0
QA1
Ref
1
REF_CLK_SEL
PLL
2000 MHz
XTAL_IN
XTAL_OUT
REF_SEL
QA2
QA3
OSC
÷N
QB0
QB1
PLL_BYPASS
REF_33MHz
QB2
QB3
÷4, 8, 16, 40
QC0
QC0
CLK_A[0:5]
CLK_B[0:5]
RIO_C[0:1]
QC1
QC1
MR
REF_OUT
Figure 1. XC9850 Logic Diagram
Table 1. Pin Configurations
Pin
I/O
Input
Input
Type
Function
Supply
VDD
Active/State
CLK
PCLK, PCLK
LVCMOS PLL Reference Clock Input (pull-down)
LVPECL PLL Reference Clock Input (PCLK - pull-down, PCLK - pull-up and
pull-down)
VDD
QA0, QA1, QA2, QA3 Output
QB0, QB1, QB2, QB3 Output
QC0, QC1, QC0, QC1 Output
LVCMOS Bank A Outputs
LVCMOS Bank B Outputs
VDDOA
VDDOB
VDDOC
VDD
LVDS
Bank C Outputs
REF_OUT
XTAL_IN
Output
Input
Output
Input
Input
Input
Input
Input
Input
Input
Input
LVCMOS Reference Output (25 MHz or 33 MHz)
LVCMOS Crystal Oscillator Input Pin
VDD
XTAL_OUT
REF_CLK_SEL
REF_SEL
REF_33MHz
MR
LVCMOS Crystal Oscillator Output Pin
VDD
LVCMOS Select between CLK and PCLK Input (pull-down)
VDD
High
LVCMOS Select between External Input and Crystal Oscillator Input (pull-down) VDD
High
High
Low
High
High
High
LVCMOS Selects 33 MHz Input (pull-down)
LVCMOS Master Reset (pull-up)
LVCMOS Select PLL or static test mode (pull-down)
LVCMOS Configures Bank A clock output frequency (pull-up)
LVCMOS Configures Bank B clock output frequency (pull-up)
LVCMOS Configures Bank C clock output frequency (pull-down)
3.3 V Supply
VDD
VDD
VDD
VDD
VDD
VDD
PLL_BYPASS
CLK_A[0:5]1
CLK_B[0:5]2
RIO_C [0:1]
VDD
VDDA
VDDOA
VDDOB
GND
Analog Supply
Supply for Output Bank A
Supply for Output Bank B
Ground
1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
2. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
PowerPC bit ordering (bit 0 = msb, bit 1 = lsb)
TIMING SOLUTIONS
MOTOROLA
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Freescale Semiconductor, Inc.
XC9850
Table 2. Function Table
Control
REF_CLK_SEL
REF_SEL
Default
0
CLK
1
0
0
0
0
1
PCLK
XTAL
CLK or PCLK
Normal
PLL_BYPASS
REF_33MHz
MR
Bypass
Selects 25 MHz Reference
Reset
Selects 33 MHz Reference
Normal
CLK_A, CLK_B, and RIO_C control output frequencies. See Table 3 and Table 4 for specific device configuration
Table 3. Output Configurations (Banks A & B)
CLK_x[0]
(msb)
CLK_x[5]
(lsb)
Frequency
(MHz)
CLK_x[0:5]1
CLK_x[1]
CLK_x[2]
CLK_x[3]
CLK_x[4]
N
111111
111100
101000
011110
010100
001111
001100
001010
001001
001000
000111
000110
000101
000100
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
126
120
80
60
40
30
24
20
18
16
15
12
10
15.87
16.67
25.00
33.33
50.00
66.67
83.33
100.00
111.11
125.00
133.33
166.67
200.00
250
82
1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
2. Minimum value for N
Table 4. Output Configurations (Bank C)
RIO_C[0:1]
Frequency (MHz)
50 (test output)
00
01
10
11
125
250
500
MOTOROLA
TIMING SOLUTIONS
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Freescale Semiconductor, Inc.
XC9850
OPERATION INFORMATION
Output Frequency Configuration
CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to
00111 or 7.
The XC9850 was designed to provide the commonly used
frequencies in PowerQUICC, PowerPC and other
Crystal Input Operation
microprocessor systems. Table 3 lists the configuration values
that will generate those common frequencies. The XC9850 can
generate numerous other frequencies that may be useful in
specific applications. The output frequency (fout) of either Bank
A or Bank B may be calculated by the following equation.
TBD
Power-Up and MR Operation
Figure 2 defines the release time and the minimum pulse
length for MR pin. The MR release time is based upon the
power supply being stable and within VDD specifications. See
Table 11 for actual parameter values. The XC9850 may be
configured after release of reset and the outputs will be stable
for use after lock indication is obtained.
fout = 2000 / N
where fout is in MHz and N = 2 * CLK_x[0:5]
This calculation is valid for all values of N from 8 to 126. Note
that N = 15 is a modified case of the configuration inputs
VDD
MR
treset_rel
treset_pulse
Figure 2. MR Operation
Power Supply Bypassing
The XC9850 is a mixed analog/digital product. The
architecture of the XC9850 supports low noise signal operation
at high frequencies. In order to maintain its superior signal
quality, all VDD pins should be bypassed by high-frequency
ceramic capacitors connected to GND. If the spectral
frequencies of the internally generated switching noise on the
supply pins cross the series resonant point of an individual
bypass capacitor, its overall impedance begins to look inductive
and thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the noise
bandwidth.
VDD
VDD
22 µF
15 Ω
0.1 µF
0.1 µF
XC9850
VDDA
Figure 3. VCC Power Supply Bypass
TIMING SOLUTIONS
MOTOROLA
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Freescale Semiconductor, Inc.
XC9850
Table 5. Absolute Maximum Ratings1
Symbol
Characteristics
Min
Max
Unit
Condition
VDD
Supply Voltage (core)
–0.3
3.8
V
VDDA
VDDOx
VIN
Supply Voltage (Analog Supply Voltage)
Supply Voltage (LVCMOS output for Bank A or B)
DC Input Voltage
–0.3
–0.3
–0.3
–0.3
VDD
VDD
V
V
VDD+0.3
VDDx+0.3
±20
V
DC Output Voltage2
DC Input Current
VOUT
IIN
IOUT
TS
V
mA
mA
°C
DC Output Current
±50
Storage Temperature
–65
125
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
2. VDDx references power supply pin associated with specific output pin.
Table 6. General Specifications
Symbol
Characteristics
Output Termination Voltage
Min
Typ
Max
Unit
Condition
VTT
V
VDD ÷ 2
MM
HBM
CDM
LU
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
Latch-Up Immunity
125
2000
500
V
V
V
100
mA
pF
CIN
Input Capacitance
4
Inputs
Per Output
CPD
θJA
TA
Power Dissipation Capacitance
Thermal Resistance (junction-to-ambient)
Ambient Temperature
10
pF
54.5
°C/W Air flow = 0
°C
–40
85
Table 7. DC Characteristics (TA = –40°C to 85°C)
Symbol
Supply Current for VDD = 3.3 V ± 5%, VDDOA = 3.3 V ± 5 and VDDOB = 3.3 V ± 5%
DD + IDDA Maximum Quiescent Supply Current (Core)
Characteristics
Min
Typ
Max
Unit
Condition
I
200
mA
VDD + VDDA
pins
IDDA
Maximum Quiescent Supply Current (Analog Supply)
Maximum Bank A and B Supply Current
15
mA
mA
VDDIN pins
IDDOA
,
175
VDDOA and
IDDOB
VDDOB pins
Supply Current for VDD = 3.3 V ± 5%, VDDOA = 2.5 V ± 5% and VDDOB= 2.5 V ± 5%
IDD + IDDA Maximum Quiescent Supply Current (Core)
200
mA
VDD + VDDA
pins
IDDA
Maximum Quiescent Supply Current (Analog Supply)
Maximum Bank A and B Supply Current
15
mA
mA
VDDIN pins
IDDOA
,
100
VDDOA and
IDDOB
VDDOB pins
MOTOROLA
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Freescale Semiconductor, Inc.
XC9850
Table 8. LVDS DC Characteristics (TA = –40°C to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Differential LVDS Clock Outputs (QC0, QC0 and QC1, QC1) for VDD = 3.3 V ± 5%
Output Differential Voltage1 (peak-to-peak)
Output Offset Voltage
(LVDS)
(LVDS)
VPP
VOS
100
400
mV
mV
1050
1600
1. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew.
Table 9. LVPECL DC Characteristics (TA = –40°C to 85°C)1
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Differential LVPECL Clock Inputs (CLK1, CLK1) for VDD = 3.3 V ± 0.5%
Differential Voltage2 (peak-to-peak)
Differential Input Crosspoint Voltage3
(LVPECL)
(LVPECL)
VPP
250
1.0
mV
V
VCMR
VDD – 0.6
1. AC characteristics are design targets and pending characterization.
2. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew.
3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range
and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and
part-to-part skew.
Table 10. LVCMOS I/O DC Characteristics (TA = –40°C to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS for VDD = 3.3 V ± 5%
VIH
VIL
IIN
Input High Voltage
Input Low Voltage
2.0
VDD + 0.3
0.8
V
V
LVCMOS
LVCMOS
Input Current1
± 200
µA
VIN = VDDL or GND
LVCMOS for VDD = 3.3 V ±5%, VDDOA = 3.3 V ± 5 and VDDOB = 3.3 V ± 5%
VOH
VOL
Output High Voltage
Output Low Voltage
Output Impedance
2.4
V
V
Ω
IOH = –24 mA
IOL = 24 mA
0.5
0.4
ZOUT
14 – 17
18 – 22
LVCMOS for VDD = 3.3 V ±5%, VDDOA = 2.5 V ± 5% and VDDOB= 2.5 V ± 5%
VOH
VOL
Output High Voltage
Output Low Voltage
Output Impedance
1.9
V
V
Ω
IOH = –15 mA
IOL = 15 mA
ZOUT
1. Inputs have pull-down resistors affecting the input current.
TIMING SOLUTIONS
MOTOROLA
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Freescale Semiconductor, Inc.
XC9850
Table 11. AC Characteristics (VDD = 3.3 V ± 5%, VDDOA = 3.3 V ± 5%,VDDOB = 3.3 V ± 5%, TA= –40°C to +85°C)1 2
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Input and Output Timing Specification
fref
Input Reference Frequency (25 MHz input)
Input Reference Frequency (33 MHz input)
XTAL Input
Input Reference Frequency in PLL Bypass Mode3
VCO Frequency Range4
25
33
25
MHz
MHz
MHz
MHz
250
PLL bypass
fVCO
fMCX
2000
MHz
Output Frequency
Bank A output
15.87
15.87
50
200
200
500
MHz
MHz
MHz
PLL locked
Bank B output
Bank C output
frefPW
frefCcc
tr, tf
Reference Input Pulse Width
Input Frequency Accuracy
Output Rise/Fall Time
Output Duty Cycle
2
ns
ppm
ns
100
500
150
20% to 80%
DC
43
47
50
50
57
53
%
Bank A and B
Bank C
PLL Specifications
tLOCK
treset_ref
treset_pulse
Maximum PLL Lock Time
10
ms
ns
ns
MR Hold Time on Power Up
MR Hold Time
10
10
Skew and Jitter Specifications
tsk(O) Output-to-Output Skew (within a bank)
tsk(O) Output-to-Output Skew (across banks A and B)
50
ps
ps
400
VDDOA = 3.3 V
VDDOB = 3.3 V
tJIT(CC)
Cycle-to-Cycle Jitter
200
150
ps
ps
Bank A and B
Bank C
tJIT(PER)
tJIT(∅)
Period Jitter
200
50
ps
ps
Bank A and C
Bank A and C
I/O Phase Jitter
RMS (1 σ)
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50Ω to VTT
3. In bypass mode, the XC9850 divides the input reference clock.
.
4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = (fVCO ÷ M) ⋅ N.
ZO = 50Ω
Pulse
ZO = 50Ω
Generator
Z = 50Ω
RT = 100Ω
DUT XC9850
RT = 50Ω
VTT
Figure 4. XC9850 AC Test Reference (LVDS Outputs)
ZO = 50Ω
ZO = 50Ω
Pulse
Generator
Z = 50Ω
DUT XC9850
RT = 50Ω
VTT
RT = 50Ω
VTT
Figure 5. XC9850 AC Test Reference (LVCMOS Outputs)
MOTOROLA
TIMING SOLUTIONS
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Freescale Semiconductor, Inc.
XC9850
Table 12. XC9850 Pin Diagram (Top View)
1
2
3
4
5
6
7
8
9
10
VDDOB
VDDOB
CLKA[1]
CLKA[3]
CLKA[5]
VDD
QA1
QA2
VDDOB
VDDOB
A
B
C
D
E
F
VDDOB
RSVD
VDDOB
RSVD
CLKA[0]
VDD
CLKA[2]
VDD
CLKA[4]
VDD
QA0
VDD
VDD
VDD
QA3
VDD
VDD
VDD
VDD
VDD
VDD
QB3
QB2
VDDOB
VDD
VDDOB
REF_OUT
QC0
VDDA
VDDA
VDD
GND
GND
GND
GND
GND
GND
VDD
GND
GND
GND
GND
VDD
QC0
REF_SEL
PCLK
CLK
VDD
GND
GND
VDD
GND
PCLK
VDD
GND
GND
QC1
QC1
REF_CLK_SEL
XTAL_IN
VDDOB
REF_33MHz
XTAL_OUT
VDDOB
VDD
GND
GND
PLL_BYPASS
RIO_C[1]
VDDOB
VDDOB
MR
G
H
J
VDD
VDD
VDD
RIO_C[0]
VDDOB
VDDOB
CLKB[0]
CLKB[1]
CLKB[2]
CLKB[3]
CLKB[4]
CLKB[5]
QB0
VDDOB
QB1
VDDOB
VDDOB
VDDOB
K
Table 13. XC9850 Pin List
100 Pin
Signal
100 Pin
MAPBGA
100 Pin
MAPBGA
100 Pin
MAPBGA
100 Pin
MAPBGA
Signal
Signal
Signal
Signal
MAPBGA
VDDOB
VDDOB
CLKA[1]
CLKA[3]
CLKA[5]
VDD
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
RSVD
RSVD
VDD
C1
REF_SEL
CLK
E1
REF_CLK_SEL
REF_33MHz
VDD
G1
VDDOB
VDDOB
CLKB[0]
CLKB[2]
CLKB[4]
QB0
J1
J2
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
E2
E3
E4
E5
E6
E7
E8
E9
E10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
VDD
J3
VDD
GND
GND
GND
GND
VDD
GND
J4
VDD
GND
J5
VDD
GND
J6
QA1
VDD
GND
VDDOB
QB3
J7
QA2
VDD
VDD
J8
VDDOB
VDDOB
VDDOB
VDDOB
CLKA[0]
CLKA[2]
CLKA[4]
QA0
VDD
VDD
PLL_BYPASS
MR
VDDOB
VDDOB
VDDOB
VDDOB
CLKB[1]
CLKB[3]
CLKB[5]
VDD
J9
REF_OUT
VDDA
VDDA
VDD
GND
PCLK
PCLK
VDD
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
XTAL_IN
XTAL_OUT
VDD
GND
GND
GND
GND
VDD
GND
GND
GND
GND
VDD
VDD
VDD
VDD
VDDOA
QA3
VDD
QB1
VDD
QB2
VDDOB
VDDOB
QC0
QC1
QC1
RIO_C[1]
RIO_C[0]
VDDOB
VDDOB
QC0
TIMING SOLUTIONS
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Freescale Semiconductor, Inc.
XC9850
OUTLINE DIMENSIONS
VF SUFFIX
100 MAP PBGA PACKAGE
CASE 1462-01
ISSUE O
B
C
11
A1 INDEX
AREA
K
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED
PARALLEL TO DATUM A.
11
4. DATUM A, SEATING PLANE, IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGING.
4X
0.2
TOP VIEW
SIDE VIEW
9X
1
0.5
5
0.35
A
K
J
(1.18)
H
G
F
9X
1
1.7 MAX
E
D
C
B
A
0.43
0.29
100X
SEATING
PLANE
4
A
0.12
A
0.5
0.55
0.45
3
100X
DETAIL K
ROTATED 90˚ CLOCKWISE
M
M
0.25
A B C
1
2
3
4
5
6
7
8
9
10
A1 INDEX
AREA
0.10
A
BOTTOM VIEW
TIMING SOLUTIONS
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XC9850
NOTES
MOTOROLA
10
TIMING SOLUTIONS
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Freescale Semiconductor, Inc.
XC9850
NOTES
TIMING SOLUTIONS
11
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XC9850
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