XC9893FA [MOTOROLA]
PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, LQFP-48;
| 型号： | XC9893FA |
| 厂家： | 
MOTOROLA |
| 描述： | PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, LQFP-48 驱动 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: XC9893/D
Rev 0, 06/2002
SEMICONDUCTOR TECHNICAL DATA
The XC9893 is a 2.5V and 3.3V compatible, PLL based intelligent
dynamic clock switch and generator specifically designed for redundant
clock distribution systems. The device receives two LVCMOS clock
signals and generates 12 phase aligned output clocks. The XC9893 is
able to detect a failing reference clock signal and to dynamically switch to
a redundant clock signal. The switch from the failing clock to the
redundant clock occurs without interruption of the output clock signal
(output clock slews to alignment). The phase bump typically caused by a
clock failure is eliminated.
LOW VOLTAGE 2.5V AND 3.3V
IDCS AND PLL
CLOCK GENERATOR
The device offers 12 low skew clock outputs organized into two output
banks, each configurable to support the different clock frequencies.
The extended temperature range of the XC9893 supports
telecommunication and networking requirements. The device employs a
fully differential PLL design to minimize jitter.
Features
• 12 output LVCMOS PLL clock generator
• 2.5V and 3.3V compatible
FA SUFFIX
48–LEAD LQFP PACKAGE
CASE 932
• IDCS - on-chip intelligent dynamic clock switch
• Automatically detects clock failure
• Smooth output phase transition during clock failover switch
• 7.5 - 200 MHz output frequency range
• LVCMOS compatible inputs and outputs
• External feedback enables zero-delay configurations
• Supports networking, telecommunications and computer applications
• Output enable/disable and static test mode (PLL bypass)
• Low skew characteristics: maximum 50 ps output-to-output (within bank)
• 48 lead LQFP package
• Ambient operating temperature range of –40 to 85°C
Functional Description
The XC9893 is a 3.3V or 2.5V compatible PLL clock driver and clock generator. The clock generator uses a fully integrated
PLL to generate clock signals from redundant clock sources. The PLL multiplies the input reference clock signal by one, two,
three, four or eight. The frequency-multiplied clock drives six bank A outputs. Six bank B outputs can run at either the same
frequency than bank A or at half of the bank A frequency. Therefore, bank B outputs additionally support the frequency
1
multiplication of the input reference clock by 3÷2 and 1÷2. Bank A and bank B outputs are phase-aligned . Due to the external
2
PLL feedback, the clock signals of both output banks are also phase-aligned to the selected input reference clock, providing
virtually zero-delay capability. The integrated IDCS continuously monitors both clock inputs and indicates a clock failure
individually for each clock input. When a false clock signal is detected, the XC9893 switches to the redundant clock input, forcing
the PLL to slowly slew to alignment and not produce any phase bumps at the outputs. Both clock inputs are interchangeable, also
supporting the switch to a failed clock that was restored. The XC9893 also provides a manual mode that allows for user-controlled
clock switches.
The PLL bypass of the XC9893 disables the IDCS and PLL-related specifications do not apply. In PLL bypass mode, the
XC9893 is fully static in order to distribute low-frequency clocks for system test and diagnosis. Outputs of the XC9893 can be
disabled (high-impedance tristate) to isolate the device from the system. Applying output disable also resets the XC9893. On
power-up this reset function needs to be applied for correct operation of the circuitry. Please see the application section for
power-on sequence recommendations.
2
The device is packaged in a 7x7 mm 48-lead LQFP package.
The XC9893 is an interim production version release.
1. At coincident rising edges
Motorola, Inc. 2002
XC9893
QA0
QA1
QA2
0
1
0
1
CLK0
(pulldown)
(pulldown)
(pulldown)
Ref
D
Q
CLK1
FB
PLL
240 – 400 MHz
QA3
QA4
QA5
FB
IDCS
REF_SEL
(pulldown)
(pullup)
MAN/A
ALARM_RST
QB0
QB1
QB2
QB3
QB4
QB5
(pullup)
D
Q
PLL_EN
(pulldown)
(pulldown)
FSEL[0:3]
Data Generator
D
Q
QFB
ALARM0
ALARM1
CLK_IND
(pulldown)
OE/MR
Figure 1. XC9893 Logic Diagram
36 35 34 33 32 31 30 29 28 27 26 25
GND
QA0
QA1
VCC
GND
QA2
QA3
VCC
GND
QA4
QA5
VCC
GND
37
38
39
40
41
42
43
44
45
46
47
48
24
QB0
QB1
VCC
GND
QB2
QB3
VCC
GND
QB4
QB5
VCC
23
22
21
20
19
18
17
16
15
14
13
XC9893
1
2
3
4
5
6
7
8
9 10 11 12
It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see application section for details.
Figure 2. 48–Lead Package Pinout (Top View)
MOTOROLA
2
TIMING SOLUTIONS
XC9893
Table 1: PIN CONFIGURATION
Pin
CLK0, CLK1
FB
I/O
Type
LVCMOS
Function
Input
Input
Input
PLL reference clock inputs
LVCMOS
LVCMOS
PLL feedback signal input, connect directly to QFB output
Selects the primary reference clock
REF_SEL
MAN/A
Input
Input
LVCMOS
LVCMOS
Selects automatic switch mode or manual reference clock selection
Reset of alarm flags and selected reference clock
ALARM_RST
PLL_EN
Input
Input
LVCMOS
LVCMOS
Select PLL or static test mode
FSEL[0:3]
Clock frequency selection and configuration of clock divider modes
OE/MR
QA[0:5]
QB[0:5]
QFB
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Output enable/disable and device reset
Bank A clock outputs
Output
Output
Output
Bank B clock outputs
Clock feedback output. QFB must be connected to FB for correct operation
Indicates clock failure on CLK0
ALARM0
Output
LVCMOS
ALARM1
CLK_IND
GND
Output
Output
Supply
Supply
LVCMOS
LVCMOS
Ground
VCC
Indicates clock failure on CLK1
Indicates currently selected input reference clock
Negative power supply
VCC_PLL
Positive power supply for the PLL (analog power supply). It is recommended to
use an external RC filter for the analog power supply pin VCC_PLL. Please see
the application section for details.
VCC
Supply
VCC
Positive power supply for I/O and core
Table 2: FUNCTION TABLE
Control
Inputs
Default
0
1
PLL_EN
0
PLL enabled. The input to output frequency
relationship is that according to Table 3 if the PLL is
frequency locked.
PLL bypassed and IDCS disabled. The VCO output is
replaced by the reference clock signal fref. The
XC9893 is in manual mode.
MAN/A
1
1
Manual clock switch mode. IDCS disabled. Clock
failure detection and output flags ALARM0, ALARM1, failure detection and output flags ALARM0, ALARM1,
CLK_IND are enabled.
Automatic clock switch mode. IDCS enabled. Clock
CLK_IND are enabled. IDCS overrides REF_SEL on
a clock failure. IDCS operation requires PLL_EN = 0.
ALARM_RST
ALARM0, ALARM1 and CLK_IND flags are reset:
ALARM0=H, ALARM1=H and CLK_IND=REF_SEL.
ALARM_RST is an one-shot function.
ALARM0, ALARM1 and CLK_IND active
REF_SEL
FSEL[0:3]
0
Selects CLK0 as the primary clock source
Selects CLK1 as the secondary clock source
0000
See Following Table
OE/MR
0
Outputs enabled (active)
Outputs disabled (high impedance tristate), reset of
data generators and output dividers. The XC9893
requires reset at power-up and after any loss of PLL
lock. Loss of PLL lock may occur when the external
feedback path is interrupted. The length of the reset
pulse should be greater than two reference clock
cycles (CLK0,1). MR/OE does not tristate the QFB
output.
Outputs (ALARM0, ALARM1, CLK_IND are valid if PLL is locked)
ALARM0
CLK0 failure
ALARM1
CLK_IND
CLK1 failure
CLK0 is the reference clock
CLK1 is the reference clock
TIMING SOLUTIONS
3
MOTOROLA
XC9893
Table 3: CLOCK FREQUENCY CONFIGURATION
QAx
QBx
f
Name
FSEL0 FSEL1 FSEL2 FSEL3
f
range [MHz]
15—25
QFB
REF
Ratio
*8
f
[MHz]
Ratio
[MHz]
QBX
QAX
f
f
f
f
f
* 8
120—200
60—100
120—200
60—100
120—200
60—100
60—100
30—50
f
M8
M82
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
f
120—200
120—200
120—200
60—100
120—200
15—25
REF
* 4
* 4
* 2
* 3
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
M4
30—50
f
f
f
f
* 4
* 3
* 2
* 2
REF
REF
REF
REF
M42
M3
40—66.6
30—50
f
* 3 ÷ 2
M32
REF
f
* 2
M2M
M22M
M2H
M22H
M1L
REF
f
f
* 1
REF
* 2
120—200
60—100
15—25
REF
f
60—100
15—25
REF
f
REF
f
f
f
REF
f
f
f
÷ 2
7.5—12.5
20—50
M12L
M1M
M12M
M1H
M12H
REF
f
REF
30—50
30—50
REF
REF
÷ 2
15—25
REF
f
60—100
30—50
REF
60—100
60—100.0
÷ 2
REF
Table 4: GENERAL SPECIFICATIONS
Symbol
Characteristics
Output Termination Voltage
Min
Typ
Max
Unit
V
Condition
V
TT
V
2
CC
MM
HBM
CDM
LU
ESD Protection (Machine Model)
200
V
ESD Protection (Human Body Model)
2000
1500
200
V
ESD Protection (Charged Device Model)
Latch–Up Immunity
V
mA
pF
pF
C
Power Dissipation Capacitance
Input Capacitance
10
4.0
Per output
Inputs
PD
C
IN
a
Table 5: ABSOLUTE MAXIMUM RATINGS
Symbol
Characteristics
Min
-0.3
-0.3
-0.3
Max
Unit
V
Condition
V
CC
Supply Voltage
3.6
V
IN
DC Input Voltage
V
V
+0.3
V
CC
V
OUT
DC Output Voltage
DC Input Current
+0.3
V
CC
I
IN
±20
mA
mA
°C
I
DC Output Current
Storage Temperature
±50
OUT
T
S
-65
125
a. Absolutemaximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
MOTOROLA
4
TIMING SOLUTIONS
XC9893
Table 6: DC CHARACTERISTICS (V
CC
= 3.3V ± 5%, T = –40° to 85°C)
A
Symbol
Characteristics
Min
Typ
Max
V + 0.3
CC
Unit
V
Condition
LVCMOS
LVCMOS
V
IH
Input high voltage
2.0
V
IL
Input low voltage
0.8
V
a
=-24 mA
OH
V
Output High Voltage
Output Low Voltage
2.4
V
I
OH
V
0.55
0.30
V
V
I = 24 mA
OL
I = 12 mA
OL
OL
Z
Output impedance
Input Current
14-17
2.0
OUT
I
±200
5.0
µA
mA
mA
V
V
V
=V
or GND
Pin
IN
CC_PLL
IN CC
I
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Output termination voltage
CC_PLL
I
4.0
All V
Pins
CC
CC
V
V
CC
÷2
TT
a. The XC9893 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission
line to a termination voltage of V . Alternatively, the device drives up to two 50Ω series terminated transmission lines.
TT
Table 7: DC CHARACTERISTICS (V
CC
= 2.5V ± 5%, T = –40° to 85°C)
A
Symbol
Characteristics
Min
Typ
Max
V + 0.3
CC
Unit
V
Condition
LVCMOS
LVCMOS
V
IH
Input high voltage
1.7
V
IL
Input low voltage
Output High Voltage
Output Low Voltage
Output impedance
Input Current
0.7
V
a
=-15 mA
V
OH
1.8
V
I
OH
= 15 mA
OL
V
OL
0.6
V
I
Z
OUT
17-20
2.0
I
±200
5.0
µA
mA
mA
V
V
V
=V
or GND
Pin
IN
CC_PLL
IN CC
I
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Output termination voltage
CC_PLL
I
4.0
All V
Pins
CC
CC
V
TT
V
CC
÷2
a. The XC9893 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission
line to a termination voltage of V . Alternatively, the device drives up to two 50Ω series terminated transmission lines per output.
TT
TIMING SOLUTIONS
5
MOTOROLA
XC9893
a
= 2.5V ± 5%, T = –40° to 85°C)
CC A
Table 8: AC CHARACTERISTICS (V
= 3.3V ± 5% or V
CC
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
b
f
Input Frequency
FSEL= 000x
15.0
30.0
40.0
30.0
60.0
15.0
30.0
60.0
25.0
50.0
66.6
50.0
100.0
12.5
50.0
100.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
ref
FSEL= 001x
FSEL= 010x
FSEL= 011x
FSEL= 100x
FSEL= 101x
FSEL= 110x
FSEL= 111x
f
Maximum Output Frequency
PLL locked
MAX
FSEL= 000x
FSEL= 001x
FSEL= 010x
FSEL= 011x
FSEL= 100x
FSEL= 101x
FSEL= 110x
FSEL= 111x
60.0
60.0
60.0
30.0
60.0
7.5
200.0
200.0
200.0
100.0
200.0
25.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
15.0
30.0
50.0
100.0
f
Reference Input Duty Cycle
CLK0, 1 Input Rise/Fall Time
40
60
%
refDC
tr, tf
1.0
ns
0.8 to 2.0V
PLL locked
t
(
Propagation Delay (static phase offset, CLKx to FB)
=3.3V±5% and FSEL=111x
)
V
CC
-125
-200
-400
+25
+100
+100
ps
ps
ps
V
CC
V
CC
=3.3V±5%
=2.5V±5%
∆ t
Rate of period change (phase slew rate)
QAx outputs
QBx outputs (FSEL=xxx0)
QBx outputs (FSEL=xxx1)
Failover
switch
150
150
300
ps/cycle
c
t
Output-to-output Skew
(within bank)
(bank-to-bank)
(any output to QFB)
50
100
125
ps
ps
ps
sk(O)
DC
Output duty Cycle
45
50
55
1.0
10
10
%
ns
ns
ns
O
t , t
r f
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
0.1
0.55 to 2.4V
t
PLZ, HZ
t
PZL, LZ
t
FSEL=xxx0
FSEL=xxx1
200
TBD
ps
ps
JIT(CC)
t
Period Jitter
FSEL=xxx0
FSEL=xxx1
150
TBD
ps
ps
JIT(PER)
d
t
I/O Phase Jitter
FSEL=111x RMS (1 σ)
40
125
ps
ps
JIT(
)
any other FSEL setting RMS (1 σ)
e
BW
PLL closed loop bandwidth
FSEL=111x
0.8-4.0
MHz
ms
t
Maximum PLL Lock Time
10
LOCK
a. AC characteristics apply for parallel output termination of 50Ω to V
.
TT
=200 to 400 MHz.
b. Next die revision will have a wider frequency range with f
c. See application section for part-to-part skew calculation.
VCO
d. See application section for calculation for other confidence factors than 1
e. -3dB point of PLL transfer characteristics.
.
MOTOROLA
6
TIMING SOLUTIONS
XC9893
APPLICATIONS INFORMATION
Definitions
signal. The feedback and newly selected reference clock
edge will start to slew to alignment at the next positive edge of
both signals. Output runt pulses are eliminated.
IDCS: Intelligent Dynamic Clock Switch. The IDCS monitors
both primary and secondary clock signals. Upon a failure of
the primary clock signal, the IDCS switches to a valid
secondary clock signal and status flags are set.
Reset
Reference clock signal fref: The clock signal that is selected
by the IDCS or REF_SEL as the input reference to the PLL.
ALARM_RST is asserted by a negative edge. It generates a
one-shot reset pulse that clears both ALARMx latches and
the CLK_IND latch. If both CLK0 and CLK1 are invalid or fail
when ALARM_RST is asserted, both ALARMx flags will be
latched after one FB signal period and CLK_IND will be
latched (L) indicating CLK0 is the reference signal. While
neither ALARMx flag is latched (ALARMx = H), the CLK_IND
can be freely changed with REF_SEL.
Manual mode: The reference clock frequency is selected by
REF_SEL.
Automatic mode: The reference clock frequency is
determined by the internal IDCS logic.
Primary clock: The input clock signal selected by REF_SEL.
The primary clock may or may not be the reference clock,
depending on switch mode and IDCS status.
OE/MR: Reset the data generator and output disable. Does
not reset the IDCS flags.
Secondary clock: The input clock signal not selected by
REF_SEL
Acquiring frequency lock at startup
Selected clock: The CLK_IND flag indicates the reference
clock signal: CLK_IND = 0 indicates CLK0 is the clock
reference signal, CLK_IND =1 indicates CLK1 is the
reference clock signal.
1. On startup, OE/MR must be asserted to reset the output
dividers. The IDCS should be disabled (MAN/A=0) during
startup to select the manual mode and the primary clock.
2. The PLL will attempt to gain lock if the primary clock is
present on startup. PLL lock requires the specified lock time.
Clock failure: A valid clock signal that is stuck (high or low) for
at least one input clock period. The primary clock and the
secondary clock is monitored for failure. Valid clock signals
must be within the AC and DC specification for the input
reference clock. A loss of clock is detected if as well as the
loss of both clocks. In the case of both clocks lost, the
XC9893 will set the alarm flags and the PLL will stall. The
XC9893 does not monitor and detect changes in the input
frequency.
3. Applying a high to low transition to ALARM_RST will clear
the alarm flags.
4. Enable the IDCS (MAN/A=1) to enable to IDCS.
Power Supply Filtering
The XC9893 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the VCC_PLL (PLL) power supply impacts the device
characteristics, for instance I/O jitter. The XC9893 provides
Automatic mode and IDCS commanded clock switch
MAN/A = 1, IDCS enabled: Both primary and secondary
clocks are monitored. The first clock failure is reported by its
ALARMx status flag (clock failure is indicated by a logic low).
The ALARMx status is flag latched and remains latched until
reset by assertion of ALARM_RST.
separate power supplies for the output buffers (V ) and the
CC
phase-locked loop (VCC_PLL) of the device. The purpose of
this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it is
more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the
VCC_PLL pin for the XC9893. Figure 3. illustrates a typical
power supply filter scheme. The XC9893 frequency and
phase stability is most susceptible to noise with spectral
content in the 100kHz to 20MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
If the clock failure occurs on the primary clock, the IDCS
attempts to switch to the secondary clock. The secondary
clock signal needs to be valid for a successful switch. Upon a
successful switch, CLK_IND indicates the reference clock,
which may now be different as that originally selected by
REF_SEL.
Manual mode
MAN/A = 0, IDCS disabled: PLL functions normally and both
clocks are monitored. The reference clock signal will always
be the clock signal selected by REF_SEL and will be
indicated by CLK_IND.
drop across the series filter resistor R . From the data sheet
F
the I
current (the current sourced through the
CC_PLL
VCC_PLL pin) is typically 3 mA (5 mA maximum), assuming
that a minimum of 2.325V (V =3.3V or V =2.5V) must be
maintained on the VCC_PLL pin. The resistor R shown in
F
Figure 3. “VCC_PLL Power Supply Filter” must have a
resistance of 9-10 to meet the voltage drop criteria.
CC
CC
Clock output transition
A clock switch, either in automatic or manual mode, follows
the next negative edge of the newly selected reference clock
TIMING SOLUTIONS
7
MOTOROLA
XC9893
R = 9–10Ω
C = 22 µF
F
t
= t
+ t
+ t
+ t
CF
This maximum timing uncertainty consist of 4
F
SK(PP)
( )
SK(O)
PD, LINE(FB)
JIT( )
R
F
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
VCC_PLL
XC9893
VCC
C
F
10 nF
CCLK
Common
t
PD,LINE(FB)
–t
(
)
VCC
33...100 nF
QFB
Device 1
t
JIT(
)
Any Q
Figure 3. VCC_PLL Power Supply Filter
The minimum values for R and the filter capacitor C are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 3. “VCC_PLL Power Supply Filter”, the
filter cut-off frequency is around 3-5 kHz and the noise
attenuation at 100 kHz is better than 42 dB.
Device 1
+t
SK(O)
F
F
+t
( )
QFB
Device2
t
JIT(
)
Any Q
Device 2
+t
SK(O)
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the XC9893 has several
design features to minimize the susceptibility to power supply
noise (isolated power and grounds and fully differential PLL)
there still may be applications in which overall performance is
being degraded due to system power supply noise. The
power supply filter schemes discussed in this section should
be adequate to eliminate power supply noise related
problems in most designs.
Max. skew
t
SK(PP)
Figure 4. XC9893 max. device-to-device skew
Due to the statistical nature of I/O jitter a RMS value (1 ) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 10.
Table 10: Confidence Facter CF
CF
± 1
± 2
± 3
± 4
± 5
± 6
Probability of clock edge within the distribution
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
Using the XC9893 in zero–delay applications
Nested clock trees are typical applications for the XC9893.
Designs using the XC9893 as LVCMOS PLL fanout buffer
with zero insertion delay will show significantly lower clock
skew than clock distributions developed from CMOS fanout
buffers. The external feedback option of the XC9893 clock
driver allows for its use as a zero delay buffer. One example
configuration is to use a ÷4 output as a feedback to the PLL
and configuring all other outputs to a divide-by-4 mode. The
propagation delay through the device is virtually eliminated.
The PLL aligns the feedback clock output edge with the clock
input reference edge resulting a near zero delay through the
device. The maximum insertion delay of the device in
zero-delay applications is measured between the reference
clock input and any output. This effective delay consists of
the static phase offset, I/O jitter (phase or long-term jitter),
feedback path delay and the output-to-output skew error
relative to the feedback output.
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% (± 3 ) is assumed,
resulting in a worst case timing uncertainty from input to any
1
output of -445 ps to 345 ps relative to CCLK:
t
=
[–200ps...100ps] + [–125ps...125ps] +
[(40ps –3)...(40ps 3)] + t
SK(PP)
PD, LINE(FB)
[–445ps...345ps] + t
PD, LINE(FB)
t
=
SK(PP)
Due to the frequency dependence of the I/O jitter,
Figure 5. “Max. I/O Jitter versus frequency” can be used for a
more precise timing performance analysis.
TBD
Calculation of part-to-part skew
See MPC961C application section for
an example I/O jitter characteristics
The XC9893 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
XC9893 are connected together, the maximum overall timing
uncertainty from the common CCLK input to any output is:
Figure 5. Max. I/O Jitter versus frequency
1. Final skew data pending specification.
MOTOROLA
8
TIMING SOLUTIONS
XC9893
Driving Transmission Lines
line impedances. The voltage wave launched down the two
lines will equal:
The XC9893 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
V
Z
R
R
V
= V ( Z ÷ (R +R +Z ))
S 0 S 0 0
L
0
S
0
L
= 50Ω || 50Ω
= 36Ω || 36Ω
= 14Ω
= 3.0 ( 25 ÷ (18+17+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
3.0
50Ω resistance to V ÷2.
CC
OutA
OutB
= 3.9386
t
D
= 3.8956
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the XC9893 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 6. “Single
versus Dual Transmission Lines” illustrates an output driving
a single series terminated line versus two series terminated
lines in parallel. When taken to its extreme the fanout of the
XC9893 clock driver is effectively doubled due to its capability
to drive multiple lines.
2.5
2.0
1.5
1.0
0.5
0
t
D
In
XC9893
OUTPUT
BUFFER
2
4
6
8
10
12
14
Z
O
= 50Ω
R = 36Ω
S
14Ω
TIME (nS)
IN
IN
OutA
Figure 7. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 8. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
XC9893
OUTPUT
BUFFER
Z
= 50Ω
= 50Ω
O
R = 36Ω
S
OutB0
OutB1
14Ω
Z
O
R = 36Ω
S
Figure 6. Single versus Dual Transmission Lines
XC9893
OUTPUT
BUFFER
Z
= 50Ω
= 50Ω
O
R = 22Ω
S
The waveform plots in Figure 7. “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the XC9893 output buffer is more than
sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the XC9893. The output waveform in Figure 7. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36Ω series resistor plus the output
impedance does not match the parallel combination of the
14Ω
Z
O
R = 22Ω
S
14Ω + 22Ω 22Ω = 50Ω 50Ω
25Ω = 25Ω
Figure 8. Optimized Dual Line Termination
TIMING SOLUTIONS
9
MOTOROLA
XC9893
XC9893 DUT
Pulse
Generator
Z = 50
Z
O
= 50Ω
Z = 50Ω
O
R = 50Ω
T
R = 50Ω
T
V
TT
V
TT
Figure 9. CLK0, CLK1 XC9893 AC test reference for V = 3.3V and V = 2.5V
cc cc
V
CC
V
2
2
CC
GND
V
CC
CLK0,
CLK1
V
CC
GND
2
2
V
CC
V
CC
GND
V
CC
V
FB
CC
GND
t
SK(O)
The pin–to–pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
t
(
)
Figure 11. Propagation delay (t , static phase
Figure 10. Output–to–output Skew t
( )
SK(O)
offset) test reference
V
CC
CLK0, 1
V
CC
GND
2
t
P
FB
T
0
DC = t /T x 100%
P 0
T
JIT(
= |T –T mean|
0 1
)
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
The deviation in t for a controlled edge with respect to a t mean in a
random sample of cycles
0
0
Figure 12. Output Duty Cycle (DC)
Figure 13. I/O Jitter
T
= |T –T
N+1
|
T
= |T –1/f |
JIT(CC)
N
JIT(PER) N 0
T
N
T
N+1
T
0
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
Figure 14. Cycle–to–cycle Jitter
Figure 15. Period Jitter
V =3.3V
CC
V =2.5V
CC
2.4
0.55
1.8V
0.6V
t
F
t
R
Figure 16. Output Transition Time Test Reference
MOTOROLA
10
TIMING SOLUTIONS
XC9893
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 932-03
ISSUE F
4X
NOTES:
0.200 AB T–U Z
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE AB IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS T, U, AND Z TO BE DETERMINED AT
DATUM PLANE AB.
DETAIL Y
P
9
A
A1
48
37
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE AC.
1
36
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE AB.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350.
T
U
B
V
AE
AE
B1
V1
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076.
12
25
9. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
MILLIMETERS
13
24
DIM MIN
MAX
7.000 BSC
3.500 BSC
Z
A
A1
B
B1
C
D
E
F
G
H
J
K
L
S1
7.000 BSC
3.500 BSC
T, U, Z
1.400 1.600
0.170 0.270
1.350 1.450
0.170 0.230
0.500 BSC
0.050 0.150
0.090 0.200
0.500 0.700
S
DETAIL Y
4X
0.200 AC T–U Z
0
7
0.080 AC
M
N
P
R
S
S1
V
V1
W
AA
12 REF
G
AB
AC
0.090 0.160
0.250 BSC
0.150 0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
AD
1.000 REF
M
BASE METAL
TOP & BOTTOM
R
N
J
E
C
F
D
M
0.080
AC T–U Z
SECTION AE–AE
W
H
L
K
DETAIL AD
AA
TIMING SOLUTIONS
11
MOTOROLA
XC9893
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
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Motorola, Inc. 2002.
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