SCN2681T [NXP]
Dual asynchronous receiver/transmitter DUART; 双重异步接收器/发送器DUART
| 型号： | SCN2681T |
| 厂家： | 
NXP |
| 描述： | Dual asynchronous receiver/transmitter DUART |
| 文件： | 总14页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
SCN2681T
Dual asynchronous receiver/transmitter
(DUART)
Product specification
1998 Sep 04
Supersedes data of 1995 May 01
IC19 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
DESCRIPTION
The Philips Semiconductors SCN2681 Dual Universal
• Programmable baud rate for each receiver and transmitter
selectable from:
Asynchronous Receiver/Transmitter (DUART) is a single-chip
MOS-LSI communications device that provides two independent
full-duplex asynchronous receiver/transmitter channels in a single
package. The SCN2681T features a faster bus cycle time than the
standard SCN2681. The quick bus cycle eliminates or reduces the
need for wait states with fast CPUs and permits high throughput in
I/O intensive systems. Higher external clock rates may be used with
the transmitter, receiver and counter timer which in turn provide
greater versatility in baud rate generation. The SCN2681T
interfaces directly with microprocessors and may be used in a polled
or interrupt driven system.
– 22 fixed rates: 50 to 115.2k baud
– Non-standard rates to 115.2
– Non-standard user-defined rate derived from programmable
counter/timer
– External 1X or 16X clock
• Parity, framing, and overrun error detection
• False start bit detection
• Line break detection and generation
• Programmable channel mode
– Normal (full-duplex)
– Automatic echo
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16X clock derived from a programmable counter/timer,
or an external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
– Local loopback
– Remote loopback
• Multi-function programmable 16-bit counter/timer
• Multi-function 7-bit input port
– Can serve as clock or control inputs
– Change of state detection on four inputs
– 100kΩ typical pull-up resistors
Each receiver is quadruple buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable
a remote DUART transmitter when the receiver buffer is full.
• Multi-function 8-bit output port
– Individual bit set/reset capability
Also provided on the SCN2681T are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
– Outputs can be programmed to be status/interrupt signals
• Versatile interrupt system
– Single interrupt output with eight maskable interrupting
conditions
For a complete functional description and programming information
for the SCN2681T, refer to the SCN2681 product specification.
– Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
• Maximum data transfer rates:
FEATURES
1X – 1MB/sec transmitter and receiver; 16X – 500kB/sec receiver
and 250kB/sec transmitter
• Fast bus cycle times reduce or eliminate CPU wait states
• Automatic wake-up mode for multidrop applications
• Start-end break interrupt/status
• Dual full-duplex asynchronous receiver/transmitters
• Quadruple buffered receiver data registers
• Detects break which originates in the middle of a character
• On-chip crystal oscillator
• Programmable data format
– 5 to 8 data bits plus parity
– Odd, even, no parity or force parity
– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
• Single +5V power supply
• Commercial and industrial temperature ranges available
• 16-bit programmable Counter/Timer
ORDERING INFORMATION
DESCRIPTION
V
CC
= +5V +10%, T = 0°C to +70°C
DWG #
A
40-Pin Plastic Dual In-Line Package (600mil-wide DIP)
44-Pin Plastic Lead Chip Carrier (PLCC)
SCN2681TC1N40
SCN2681TC1A44
SOT129-1
SOT187-2
NOTE: For a full register description and programming information see the SCN2681.
2
1998 Sep 04
853–1002 19970
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
PIN CONFIGURATIONS
INDEX
CORNER
6
40
1
A0
IP3
A1
1
2
3
4
5
40
V
CC
7
39
39 IP4
38 IP5
37 IP6
36 IP2
PLCC
IP1
A2
A3
IP0
6
7
8
9
35 CEN
34 RESET
33 X2
29
17
18
28
TOP VIEW
WRN
RDN
32 X1/CLK
31 RxDA
30 TxDA
29 OP0
PIN/FUNCTION
PIN/FUNCTION
RxDB 10
TxDB 11
OP1 12
1
2
3
4
5
6
7
8
9
NC
A0
IP3
A1
IP1
A2
A3
IP0
WRN
23 NC
DIP
24 INTRN
25 D6
26 D4
27 D2
28 D0
29 OP6
30 OP4
31 OP2
32 OP0
33 TxDA
34 NC
OP3 13
OP5 14
OP7 15
D1 16
28 OP2
27 OP4
26 OP6
25 D0
10 RDN
11 RxDB
12 NC
13 TxDB
14 OP1
15 OP3
16 OP5
17 OP7
18 D1
35 RxDA
36 X1/CLK
37 X2
38 RESET
39 CEN
40 IP2
D3 17
24 D2
D5 18
23 D4
19 D3
20 D5
41 IP6
42 IP5
D7 19
22 D6
21 D7
43 IP4
GND 20
21 INTRN
22 GND
44
V
CC
SD00098
Figure 1. Pin Configurations
NOTE:
Refer to SCN2681 for functional description.
3
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
BLOCK DIAGRAM
8
CHANNEL A
D0–D7
BUS BUFFER
TRANSMIT
TxDA
RxDA
HOLDING REG
TRANSMIT
SHIFT REGISTER
OPERATION CONTROL
RDN
RECEIVE
HOLDING REG (3)
WRN
CEN
ADDRESS
DECODE
4
RECEIVE
SHIFT REGISTER
A0–A3
RESET
R/W CONTROL
MRA1, 2
CRA
SRA
INTERRUPT CONTROL
TxDB
RxDB
INTRN
IMR
ISR
CHANNEL B
(AS ABOVE)
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
TIMING
7
IP0-IP6
BAUD RATE
GENERATOR
IPCR
ACR
CLOCK
SELECTORS
COUNTER/
TIMER
OUTPUT PORT
FUNCTION
SELECT LOGIC
8
OP0-OP7
X1/CLK
X2
XTAL OSC
OPCR
OPR
CSRA
CSRB
ACR
U
CTLR
CTLR
V
CC
GND
SD00099
Figure 2. Block Diagram
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1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
PIN DESCRIPTION
MNEMONIC TYPE
NAME AND FUNCTION
D0–D7
I/O
Data Bus: Bidirectional three-state data bus used to transfer commands, data and status between the DUART and
the CPU. D0 is the least significant bit.
CEN
I
Chip Enable: Active low input signal. When low, data transfers between the CPU and the DUART are enabled on
D0–D7 as controlled by the WRN, RDN, and A0–A3 inputs. When CEN is high, the DUART places the D0–D7 lines in
the three-state condition.
WRN
RDN
I
I
Write Strobe: When low and CEN is also low, the contents of the data bus is loaded into the addressed register. The
transfer occurs on the rising edge of the signal.
Read Strobe: When low and CEN is also low, causes the contents of the addressed register to be presented on the
data bus. The read cycle begins on the falling edge of RDN.
A0–A3
I
I
Address Inputs: Select the DUART internal registers and ports for read/write operations.
RESET
Reset: A high level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the high state,
stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark
(high) state. Clears Test modes, sets MR pointer to MR1.
INTRN
X1/CLK
X2
O
I
Interrupt Request: Active-low, open-drain output which signals the CPU that one or more of the eight maskable
interrupting conditions are true.
Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally
3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing.
I
Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not connected although it
is permissible to ground it.
RxDA
RxDB
TxDA
I
I
Channel A Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is high, ‘space’ is low.
Channel B Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is high, ‘space’ is low.
O
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’
condition when the transmitter is disabled, idle, or when operating in local loopback mode. ‘Mark’ is high, ‘space’ is low.
TxDB
O
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the
‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode. ‘Mark’ is high,
‘space’ is low.
OP0
OP1
O
O
Output 0: General purpose output, or channel A request to send (RTSAN, active-low). Can be deactivated
automatically on receive or transmit.
Output 1: General purpose output, or channel B request to send (RTSBN, active-low). Can be deactivated
automatically on receive or transmit.
OP2
OP3
O
O
Output 2: General purpose output, or channel A transmitter 1X or 16X clock output, or channel A receiver 1X clock output.
Output 3: General purpose output, or open-drain, active-low counter/timer output, or channel B transmitter 1X clock
output, or channel B receiver 1X clock output.
OP4
OP5
OP6
OP7
IP0
O
O
O
O
I
Output 4: General purpose output, or channel A open-drain, active-low, RxRDYA/FFULLA output.
Output 5: General purpose output, or channel B open-drain, active-low, RxRDYB/FFULLB output.
Output 6: General purpose output, or channel A open-drain, active-low, TxRDYA output.
Output 7: General purpose output, or channel B open-drain, active-low TxRDYB output.
Input 0: General purpose input, or channel A clear to send active-low input (CTSAN). Pin has an internal V pull-up
CC
device supplying 1 to 4 mA of current.
IP1
IP2
IP3
I
I
I
Input 1: General purpose input, or channel B clear to send active-low input (CTSBN). Pin has an internal V pull-up
device supplying 1 to 4 mA of current.
CC
Input 2: General purpose input, or counter/timer external clock input. Pin has an internal V pull-up device supplying
CC
1 to 4 mA of current.
Input 3: General purpose input, or channel A transmitter external clock input (TxCA). When the external clock is used
by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal V pull-up
CC
device supplying 1 to 4 mA of current.
IP4
IP5
IP6
I
I
I
Input 4: General purpose input, or channel A receiver external clock input (RxCA). When the external clock is used by
the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal V pull-up device
CC
supplying 1 to 4 mA of current.
Input 5: General purpose input, or channel B transmitter external clock input (TxCB). When the external clock is used
by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal V pull-up
CC
device supplying 1 to 4 mA of current.
Input 6: General purpose input, or channel B receiver external clock input (RxCB). When the external clock is used by
the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal V pull-up device
CC
supplying 1 to 4 mA of current.
Power Supply: +5V supply input.
Ground
V
I
I
CC
GND
5
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
0 to +70
UNIT
°C
2
T
A
Operating ambient temperature range
T
STG
Storage temperature range
-65 to +150
-0.5 to +6.0
°C
3
All voltages with respect to GND
V
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
1, 2, 3
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Typ
Max
V
V
V
Input low voltage
Input high voltage (except X1/CLK)
Input high voltage (X1/CLK)
0.8
IL
2.0
3.5
V
IH
IH
V
V
Output low voltage
Output high voltage (except o.c. outputs)
I
= 2.4mA
= -400µA
0.4
OL
OL
V
4
I
2.4
OH
OH
I
I
Input leakage current
Data bus 3-state leakage current
V
= 0 to V
CC
-10
-10
10
10
IL
IN
µA
V = 0.4 to V
O CC
LL
I
X1/CLK low input current
X1/CLK high input current
V
= 0, X2 grounded
-4
-3
-1
0
-2
-1.5
0.2
3.5
0
0
1
mA
mA
mA
mA
X1L
IN
V
= 0, X2 floated
IN
I
V
= V , X2 = grounded
X1H
IN
V
CC
= V , X2 floated
10
IN
CC
I
I
X2 low input current
X2 high input current
V
= 0, X1/CLK floated
-100
0
-30
+30
0
100
µA
µA
X2L
IN
V
IN
= V , X1/CLK floated
X2H
CC
I
I
Open-collector output leakage current
V
O
= 0.4 to V
CC
-10
10
µA
OC
5
Power supply current
150
mA
CC
NOTES:
1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and V
supply range.
CC
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a
transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages
of 0.8V and 2.0V and output voltages of 0.8V and 2.0V as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: C = 150pF, except interrupt outputs. Test conditions for interrupt outputs: C = 50pF, R = 2.7kΩ to V .
L
L
L
CC
5. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle.
1, 2, 3, 4
AC ELECTRICAL CHARACTERISTICS
RESET
t
RES
SD00028
Figure 3. Reset Timing
NOTES:
1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and V
supply range.
CC
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a
transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages
of 0.8V and 2.0V and output voltages of 0.8V and 2.0V as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: C = 150pF, except interrupt outputs. Test conditions for interrupt outputs: C = 50pF, R = 2.7kΩ to V .
L
L
L
CC
6
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Max
t
Reset pulse width
1.0
µs
RES
A0–A3
t
t
AVEL
ELAX
CEN
(READ)
t
EHEL
t
RLRH
RDN
t
RHDF
t
RLDV
t
RHDI
t
RLDA
D0–D7
(READ)
FLOAT
INVALID
VALID
FLOAT
CEN
(WRITE)
t
EHEL
t
WLWH
WRN
t
DVWH
t
WHDI
D0–D7
(WRITE)
VALID
SD00100
Figure 4. Bus Timing
LIMITS
1
SYMBOL
PARAMETER
UNIT
Min
Max
t
t
t
t
t
t
t
t
t
t
t
A0–A3 setup to RDN and CEN, or WRN and CEN low
RDN and CEN, or WRN and CEN low to A0–A3 invalid
RDN and CEN low to RDN or CEN high
CEN high to CEN low
CEN and RDN low to data outputs active
CEN and RDN low to data valid
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVEL
ELAX
RLRH
EHEL
RLDA
RLDV
RHDI
100
120
110
15
2, 3
100
65
CEN or RDN high to data invalid
10
CEN or RDN high to data outputs floating
WRN and CEN low to WRN or CEN high
Data input valid to WRN or CEN high
WRN or CEN high to data invalid
RHDF
WLWH
DVWH
WHDI
75
35
15
NOTES:
1. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle.
2. If CEN is used as the ‘strobing’ input, the parameter defines the minimum high times between one CEN and the next. The RDN signal must
be negated for t
to guarantee that any status register changes are valid. As a consequence, this minimum time must be met for the
EHEL
RDN input even if the CEN is used as the strobing signal for bus operations.
3. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
7
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
RDN
t
t
PH
PS
IP0–IP6
(a) INPUT PINS
WRN
t
PD
OP0–OP7
OLD DATA
NEW DATA
(b) OUTPUT PINS
SD00101
Figure 5. Port Timing
LIMITS
1
SYMBOL
PARAMETER
UNIT
Min
Max
t
t
t
Port input setup time before RDN low
Port input hold time after RDN high
Port output valid after WRN high
0
0
ns
ns
ns
PS
PH
PD
200
NOTE:
1. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle.
V
M
WRN
t
IR
1
INTERRUPT
V
+0.5V
OL
OUTPUT
V
OL
NOTES:
1. INTRN or OP3-OP7 when used as interrupt outputs.
2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching
signal, V , to a point 0.5V above V . This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and
M
OL
test environment are pronounced and can greatly affect the resultant measurement.
SD00102
Figure 6. Interrupt Timing
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Max
INTRN (or OP3–OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (delta break interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
200
200
200
200
200
200
ns
ns
ns
ns
ns
ns
t
IR
8
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
+5V
R1: 100K - 1Meg (See design note)
C1 = C2: 0-5pF + (STRAY < 5pF)
t
CLK
1K
t
CTC
DRIVING FROM
EXTERNAL SOURCE
CLOCK
t
Rx
Tx
TO OTHER
CHIPS
t
74LS04
X1/CLK
CTCLK
RxC
SCN2681
TxC
X1
TO THE REST
t
t
t
t
OF THE DUART
CIRCUITS
CLK
CTC
Rx
OPEN
X1
C1
C2
+5V
R2
Tx
R1
1KΩ
When using an external clock it is preferred to drive X2 and leave X1 open.
X2 is the input to the internal driver, while X1 is the output.
R1 is only required if U1 will not drive to X2 high level.
U1
X2
3.6864MHz
X2
Previous specifications indicated X2 should be grounded and X1
should be driven. This is still acceptable. It is electrically easier to drive
the amplifier input than to overdrive its output.
CRYSTAL SERIES RESISTANCE3 SHOULD BE LESS THAN 180Ω
R2 = 50kΩ to 150kΩ
SD00091
Figure 7. Clock Timing
LIMITS
Typ
SYMBOL
PARAMETER
UNIT
Min
Max
X1/CLK high or low time
X1/CLK frequency
90
2
55
0
55
0
0
ns
MHz
ns
MHz
ns
t
f
t
f
4
8
CLK
CTCLK (IP2) high or low time
CLK
CTC
CTC
1
CTCLK (IP2) frequency
RxC high or low time
1
t
f
RxC frequency (16X)
3.6864
8
1
MHz
MHz
RX
RX
1
(1X)
t
TX
f
TX
TxC high or low time
110
0
0
ns
MHz
MHz
1
TxC frequency (16X)
4
1
1
(1X)
NOTE:
1. Minimum frequencies are not tested but are guaranteed by design.
1 BIT TIME
(1 OR 16 CLOCKS)
TxC
(INPUT)
t
TXD
TxD
t
TCS
TxC
(1X OUTPUT)
SD00103
Figure 8. Transmit
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Max
t
t
TxD output delay from TxC external clock input on IP pin
Output delay from TxC low at OP pin to TxD data output
300
100
ns
ns
TXD
0
TCS
9
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
RxC
(1X INPUT)
t
t
RXH
RXS
RxD
SD00104
Figure 9. Receive
LIMITS
SYMBOL
PARAMETER
UNIT
Max
Min
t
t
RxD data setup time before RxC high at external clock input on IP pin
RxD data hold time after RxC high at external clock input on IP pin
200
25
ns
ns
RXS
RXH
TxD
D1
D2
D3
BREAK
D4
D6
TRANSMITTER
ENABLED
TxRDY
(SR2)
WRN
D1
D2
D3
START
BREAK
D4
STOP
BREAK
D5 WILL
NOT BE
D6
TRANSMITTED
1
CTSN
(IP0)
2
RTSN
(OP0)
OPR(0) = 1
OPR(0) = 1
NOTES:
1. Timing shown for MR2(4) = 1.
2. Timing shown for MR2(5) = 1.
SD00094
Figure 10. Transmitter Timing
10
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
D1
D2
D3
D4
D5
D6
D7
D8
RxD
D6, D7, D8 WILL BE LOST
RECEIVER
ENABLED
RxRDY
(SR0)
FFULL
(SR1)
RxRDY/
FFULL
2
(OP5)
RDN
S = STATUS
D = DATA
S
D
S D
S
D
S
D
D2
D1
D3
D4
OVERRUN
(SR4)
D5 WILL
BE LOST
RESET BY
COMMAND
1
RTS
(OP0)
OPR(0) = 1
NOTES:
1. Timing shown for MR1(7) = 1.
2. Shown for OPCR(4) = 1 and MR1(6) = 0.
SD00105
Figure 11. Receiver Timing
MASTER STATION
TxD
BIT 9
1
BIT 9
BIT 9
1
ADD#1
D0
0
ADD#2
TRANSMITTER
ENABLED
TxRDY
(SR2)
WRN
MR1(4–3) = 11
MR1(2) = 1
ADD#1 MR1(2) = 0D0
MR1(2) = 1
ADD#2
PERIPHERAL STATION
BIT 9
BIT 9
1
BIT 9
0
BIT 9
1
BIT 9
RxD
0
ADD#1
D0
ADD#2
0
RECEIVER
ENABLED
RxRDY
(SR0)
RDN/WRN
S = STATUS
D = DATA
S
D
S
D
MR1(4–3) = 11
ADD#1
D0
ADD#2
SD00106
Figure 12. Wake-Up Mode
11
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
12
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
13
1998 Sep 04
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 09-98
Document order number:
9397 750 04363
Philips
Semiconductors
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