SC16C750IA44 [NXP]
Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFO; 通用异步接收器/发送器( UART )具有64字节FIFO型号: | SC16C750IA44 |
厂家: | NXP |
描述: | Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFO |
文件: | 总45页 (文件大小:548K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SC16C750
Universal Asynchronous Receiver/Transmitter (UART)
with 64-byte FIFO
Rev. 04 — 20 June 2003
Product data
1. General description
The SC16C750 is a Universal Asynchronous Receiver and Transmitter (UART) used
for serial data communications. Its principal function is to convert parallel data into
serial data, and vice versa. The UART can handle serial data rates up to 3 Mbits/s.
The SC16C750 is pin compatible with the TL16C750 and it will power-up to be
functionally equivalent to the 16C450. Programming of control registers enables the
added features of the SC16C750. Some of these added features are the 64-byte
receive and transmit FIFOs, automatic hardware flow control. The selectable
auto-flow control feature significantly reduces software overload and increases
system efficiency while in FIFO mode by automatically controlling serial data flow
using RTS output and CTS input signals. The SC16C750 also provides DMA mode
data transfers through FIFO trigger levels and the TXRDY and RXRDY signals.
On-board status registers provide the user with error indications, operational status,
and modem interface control. System interrupts may be tailored to meet user
requirements. An internal loop-back capability allows on-board diagnostics.
The SC16C750 operates at 5 V, 3.3 V and 2.5 V, the industrial temperature range and
is available in plastic PLCC44 and LQFP64 packages.
2. Features
■ 5 V, 3.3 V and 2.5 V operation
■ Industrial temperature range
■ After reset, all registers are identical to the typical 16C450 register set
■ Capable of running with all existing generic 16C450 software
■ Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,
PC16C450/550
■ Up to 3 Mbits/s transmit/receive operation at 5 V, 2 Mbits/s at 3.3 V, and
1 Mbit/s at 2.5 V
■ 64 byte transmit FIFO
■ 64 byte receive FIFO with error flags
■ Programmable auto-RTS and auto-CTS
◆ In auto-CTS mode, CTS controls transmitter
◆ In auto-RTS mode, RxFIFO contents and threshold control RTS
■ Automatic hardware flow control
■ Software selectable Baud Rate Generator
■ Four selectable Receive interrupt trigger levels
■ Standard modem interface
■ Sleep mode
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
■ Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break)
■ Independent receiver clock input
■ Transmit, Receive, Line Status, and Data Set interrupts independently controlled
■ Fully programmable character formatting:
◆ 5-, 6-, 7-, or 8-bit characters
◆ Even-, Odd-, or No-Parity formats
◆ 1-, 11⁄2-, or 2-stop bit
◆ Baud generation (DC to 3 Mbits/s)
■ False start-bit detection
■ Complete status reporting capabilities
■ 3-State output TTL drive capabilities for bi-directional data bus and control bus
■ Line Break generation and detection
■ Internal diagnostic capabilities:
◆ Loop-back controls for communications link fault isolation
■ Prioritized interrupt system controls
■ Modem control functions (CTS, RTS, DSR, DTR, RI, DCD).
3. Ordering information
Table 1:
Ordering information
Industrial: VCC = 2.5 V, 3.3 V or 5 V ± 10%; Tamb = −40 °C to +85 °C.
Type number
Package
Name
Description
Version
SC16C750IA44
SC16C750IB64
PLCC44
LQFP64
plastic leaded chip carrier; 44 leads
plastic low profile quad flat package; 64 leads; 10 × 10 × 1.4 mm
SOT187-2
SOT314-2
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
2 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
4. Block diagram
SC16C750
TRANSMIT
FIFO
TRANSMIT
SHIFT
TX
REGISTERS
REGISTER
D0–D7
IOR, IOR
IOW, IOW
RESET
DATA BUS
AND
CONTROL LOGIC
FLOW
CONTROL
LOGIC
RECEIVE
FIFO
RECEIVE
SHIFT
RX
REGISTERS
REGISTER
FLOW
CONTROL
LOGIC
REGISTER
SELECT
LOGIC
A0–A2
CS0, CS1, CS2
AS
DDIS
DTR
RTS
OUT1, OUT2
MODEM
CONTROL
LOGIC
INT
TXRDY
RXRDY
CTS
RI
DCD
CLOCK AND
BAUD RATE
GENERATOR
INTERRUPT
CONTROL
LOGIC
DSR
002aaa335
XTAL1 XTAL2
RCLK BAUDOUT
Fig 1. Block diagram.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
3 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
5. Pinning information
5.1 Pinning
D5
D6
D7
7
8
9
39 RESET
38 OUT1
37 DTR
36 RTS
35 OUT2
34 NC
RCLK 10
RX 11
SC16C750IA44
NC 12
TX 13
33 INT
CS0 14
32 RXRDY
31 A0
CS1 15
CS2 16
30 A1
BAUDOUT 17
29 A2
002aaa336
Fig 2. PLCC44 pin configuration.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
4 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
1
2
48
47
46
45
44
43
42
41
40
39
38
XTAL1
XTAL2
NC
D4
NC
D3
D2
NC
D1
D0
NC
V
3
IOW
NC
4
5
6
IOW
NC
7
8
V
SS
SC16C750IB64
9
IOR
IOR
CC
10
11
12
NC
RI
NC
DDIS
37 NC
TXRDY 13
NC 14
36 DCD
35 DSR
34 NC
AS 15
NC 16
33 CTS
002aaa364
Fig 3. LQFP64 pin configuration.
5.2 Pin description
Table 2:
Symbol
Pin description
Pin
Type Description
PLCC44 LQFP64
A2-A0
AS
28, 27,
26
17, 18, 20
I
I
Register select. A0-A2 are used during read and write operations to select
the UART register to read from or write to. Refer to Table 3 for register
addresses and refer to AS description.
28
15
Address strobe. When AS is active (LOW), A0, A1, and A2 and CS0, CS1,
and CS2 drive the internal select logic directly; when AS is HIGH, the
register select and chip select signals are held at the logic levels they were
in when the LOW-to-HIGH transition of AS occurred.
BAUDOUT
17
64
O
Baud out. BAUDOUT is a 16× clock signal for the transmitter section of the
UART. The clock rate is established by the reference oscillator frequency
divided by a divisor specified in the baud generator divisor latches.
BAUDOUT may also be used for the receiver section by tying this output to
RCLK.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
5 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
Table 2:
Symbol
Pin description…continued
Pin
Type Description
PLCC44 LQFP64
CS0, CS1,
CS2
14, 15,
16
59, 61, 62
I
I
Chip select. When CS0 and CS1 are HIGH and CS2 is LOW, these three
inputs select the UART. When any of these inputs are inactive, the UART
remains inactive (refer to AS description).
CTS
40
33
Clear to send. CTS is a modem status signal. Its condition can be checked
by reading bit 4 (CTS) of the modem status register. Bit 0 (∆CTS) of the
modem status register indicates that CTS has changed states since the last
read from the modem status register. If the modem status interrupt is
enabled when CTS changes levels and the auto-CTS mode is not enabled,
an interrupt is generated. CTS is also used in the auto-CTS mode to control
the transmitter.
D7-D0
DCD
2-9
42
52, 51, 50, I/O
48, 46, 45,
43, 42
Data bus. Eight data lines with 3-State outputs provide a bi-directional path
for data, control and status information between the UART and the CPU.
36
I
Data carrier detect. DCD is a modem status signal. Its condition can be
checked by reading bit 7 (DCD) of the modem status register. Bit 3 (∆DCD)
of the modem status register indicates that DCD has changed states since
the last read from the modem status register. If the modem status interrupt
is enabled when DCD changes levels, an interrupt is generated.
DDIS
DSR
26
41
12
35
O
I
Driver disable. DDIS is active (LOW) when the CPU is not reading data.
When active, DDIS can disable an external transceiver.
Data set ready. DSR is a modem status signal. Its condition can be
checked by reading bit 5 (DSR) of the modem status register. Bit 1 (∆DSR)
of the modem status register indicates DSR has changed levels since the
last read from the modem status register. If the modem status interrupt is
enabled when DSR changes levels, an interrupt is generated.
DTR
INT
37
33
28
23
O
O
Data terminal ready. When active (LOW), DTR informs a modem or data
set that the UART is ready to establish communication. DTR is placed in the
active level by setting the DTR bit of the modem control register. DTR is
placed in the inactive level either as a result of a Master Reset, during loop
mode operation, or clearing the DTR bit.
Interrupt. When active (HIGH), INT informs the CPU that the UART has an
interrupt to be serviced. Four conditions that cause an interrupt to be issued
are: a receiver error, received data that is available or timed out (FIFO mode
only), an empty transmitter holding register or an enabled modem status
interrupt. INT is reset (deactivated) either when the interrupt is serviced or
as a result of a Master Reset.
MR
NC
39
34
32
I
Master Reset. When active (HIGH), MR clears most UART registers and
sets the levels of various output signals.
3, 5, 7, 11,
14, 16, 19,
22, 24, 27,
29, 31, 34,
37, 39, 41,
44, 47, 49,
53, 56, 57,
60, 63
Not connected.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
6 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
Table 2:
Symbol
Pin description…continued
Pin
Type Description
PLCC44 LQFP64
OUT1, OUT2 38, 35
30, 25
O
Outputs 1 and 2. These are user-designated output terminals that are set
to the active (low) level by setting respective modem control register (MCR)
bits (OUT1 and OUT2). OUT1 and OUT2 are set to inactive the (HIGH) level
as a result of Master Reset, during loop mode operations, or by clearing
bit 2 (OUT1) or bit 3 (OUT2) of the MCR.
RCLK
10
54
I
I
Receiver clock. RCLK is the 16× baud rate clock for the receiver section of
the UART.
IOR, IOR
24, 25
9, 10
Read inputs. When either IOR or IOR is active (LOW or HIGH,
respectively) while the UART is selected, the CPU is allowed to read status
information or data from a selected UART register. Only one of these inputs
is required for the transfer of data during a read operation; the other input
should be tied to its inactive level (i.e., IOR tied LOW or IOR tied HIGH).
RI
43
36
32
38
26
21
I
Ring indicator. RI is a modem status signal. Its condition can be checked
by reading bit 6 (RI) of the modem status register. Bit 2 (∆RI) of the modem
status register indicates that RI has transitioned from a LOW to a HIGH
level since the last read from the modem status register. If the modem
status interrupt is enabled when this transition occurs, an interrupt is
generated.
RTS
O
O
Request to send. When active, RTS informs the modem or data set that
the UART is ready to receive data. RTS is set to the active level by setting
the RTS modem control register bit and is set to the inactive (HIGH) level
either as a result of a Master Reset or during loop mode operations or by
clearing bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS is set to the
inactive level by the receiver threshold control logic.
RXRDY
Receiver ready. Receiver direct memory access (DMA) signaling is
available with RXRDY. When operating in the FIFO mode, one of two types
of DMA signaling can be selected using the FIFO control register bit 3
(FCR[3]). When operating in the 16C450 mode, only DMA mode 0 is
allowed. Mode 0 supports single-transfer DMA in which a transfer is made
between CPU bus cycles. Mode 1 supports multi-transfer DMA in which
multiple transfers are made continuously until the receiver FIFO has been
emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is
at least one character in the receiver FIFO or receiver holding register,
RXRDY is active (LOW). When RXRDY has been active but there are no
characters in the FIFO or holding register, RXRDY goes inactive (HIGH). In
DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level or the time-out
has been reached, RXRDY goes active (LOW); when it has been active but
there are no more characters in the FIFO or holding register, it goes inactive
(HIGH).
RX
TX
11
13
55
58
I
I
Serial data input. RX is serial data input from a connected communications
device.
Serial data output. TX is composite serial data output to a connected
communication device. TX is set to the marking (HIGH) level as a result of
Master Reset.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
7 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
Table 2:
Symbol
Pin description…continued
Pin
Type Description
PLCC44 LQFP64
TXRDY
27
13
O
Transmitter ready. Transmitter DMA signaling is available with TXRDY.
When operating in the FIFO mode, one of two types of DMA signaling can
be selected using FCR[3]. When operating in the 16C450 mode, only DMA
mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer
is made between CPU bus cycles. Mode 1 supports multi-transfer DMA in
which multiple transfers are made continuously until the transmit FIFO has
been filled.
VCC
44
40
8
Power 2.5 V, 3 V or 5 V supply voltage.
Power Ground voltage.
VSS
22
IOW, IOW
20, 21
4, 6
I
Write inputs. When either IOW or IOW is active (LOW or HIGH,
respectively) and while the UART is selected, the CPU is allowed to write
control words or data into a selected UART register. Only one of these
inputs is required to transfer data during a write operation; the other input
should be tied to its inactive level (i.e., IOW tied LOW or IOW tied HIGH).
XTAL1
XTAL2[1]
18
19
1
2
I
Crystal connection or External clock input.
O
Crystal connection or the inversion of XTAL1 if XTAL1 is driven.
[1] In sleep mode, XTAL2 is left floating.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
8 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
6. Functional description
The SC16C750 provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data
stream into parallel data that is required with digital data systems. Synchronization for
the serial data stream is accomplished by adding start and stop bits to the transmit
data to form a data character (character orientated protocol). Data integrity is insured
by attaching a parity bit to the data character. The parity bit is checked by the receiver
for any transmission bit errors. The SC16C750 is fabricated with an advanced CMOS
process to achieve low drain power and high speed requirements.
The SC16C750 is an upward solution that provides 64 bytes of transmit and receive
FIFO memory, instead of none in the 16C450, or 16 in the 16C550. The SC16C750 is
designed to work with high speed modems and shared network environments that
require fast data processing time. Increased performance is realized in the
SC16C750 by the larger transmit and receive FIFOs. This allows the external
processor to handle more networking tasks within a given time. In addition, the four
selectable levels of FIFO trigger interrupt and automatic hardware flow control is
uniquely provided for maximum data throughput performance, especially when
operating in a multi-channel environment. The combination of the above greatly
reduces the bandwidth requirement of the external controlling CPU, increases
performance, and reduces power consumption.
The SC16C750 is capable of operation up to 3 Mbits/s with a 48 MHz external clock
input (at 5 V).
The rich feature set of the SC16C750 is available through internal registers.
Automatic hardware flow control, selectable transmit and receive FIFO trigger level,
selectable TX and RX baud rates, modem interface controls, and a sleep mode are
some of these features.
6.1 Internal registers
The SC16C750 provides 15 internal registers for monitoring and control. These
registers are shown in Table 3. Twelve registers are similar to those already available
in the standard 16C550. These registers function as data holding registers
(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register
(FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),
and a user accessible scratchpad register (SPR). Beyond the general 16C550
features and capabilities, the SC16C750 offers an enhanced feature register that
provides on-board hardware flow control. Register functions are more fully described
in the following paragraphs.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
9 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
Table 3:
A2
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1]
Internal registers decoding
A1
A0 READ mode
WRITE mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Receive Holding Register
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
n/a
Interrupt Status Register
Line Status Register
Modem Status Register
Scratchpad Register
n/a
Scratchpad Register
Baud rate register set (DLL/DLM)[2]
0
0
0
LSB of Divisor Latch
LSB of Divisor Latch
MSB of Divisor Latch
0
0
1
MSB of Divisor Latch
Enhanced register set (EFR, Xon/off 1-2)[3]
0
1
1
1
1
1
0
0
1
1
0
0
1
0
1
Enhanced Feature Register
Xon1 word
Enhanced Feature Register
Xon1 word
Xon2 word
Xon2 word
Xoff1 word
Xoff1 word
Xoff2 word
Xoff2 word
[1] These registers are accessible only when LCR[7] is a logic 0.
[2] These registers are accessible only when LCR[7] is a logic 1.
[3] Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to
‘BF(HEX)’.
6.2 FIFO operation
The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control
Register bit-0 (FCR[0]). With 16C550 devices, the user can set the receive trigger
level, but not the transmit trigger level. The SC16C750 provides independent trigger
levels for both receiver and transmitter. To remain compatible with SC16C550, the
transmit interrupt trigger level is set to 16 following a reset. It should be noted that the
user can set the transmit trigger levels by writing to the FCR register, but activation
will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes
a time-out function to ensure data is delivered to the external CPU. An interrupt is
generated whenever the Receive Holding Register (RHR) has not been read
following the loading of a character or the receive trigger level has not been reached.
Table 4:
Flow control mechanism
Selected trigger level
(characters)
INT pin activation
Negate RTS
Assert RTS
16-byte FIFO
1
1
4
1
4
4
8
4
8
8
12
14
8
14
14
10
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
10 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
Table 4:
Flow control mechanism…continued
Selected trigger level
(characters)
INT pin activation
Negate RTS
Assert RTS
64-byte FIFO
1
1
16
32
56
60
1
16
32
56
16
32
56
8
16
32
6.3 Hardware flow control
When automatic hardware flow control is enabled, the SC16C750 monitors the CTS
pin for a remote buffer overflow indication and controls the RTS pin for local buffer
overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and
EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a
flow control request, the SC16C750 will suspend TX transmissions as soon as the
stop bit of the character in process is shifted out. Transmission is resumed after the
CTS input returns to a logic 0, indicating more data may be sent.
With the Auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level
below the programmed trigger level. However, under the above described conditions,
the SC16C750 will continue to accept data until the receive FIFO is full.
6.4 Time-out interrupts
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C750 FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
11 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
6.5 Programmable baud rate generator
The SC16C750 supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate.
A 128.0 kbit/s ISDN modem that supports data compression may need an input
data rate of 460.8 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is
capable of accepting an input clock up to 48 MHz, as required for supporting a
3 Mbits/s data rate. The SC16C750 can be configured for internal or external clock
operation. For internal clock oscillator operation, an industry standard microprocessor
crystal (parallel resonant/22-33 pF load) is connected externally between the XTAL1
and XTAL2 pins (see Figure 4). Alternatively, an external clock can be connected to
the XTAL1 pin to clock the internal baud rate generator for standard or custom rates
(see Table 5).
1.5 kΩ
X1
X1
1.8432 MHz
1.8432 MHz
C1
47 pF
C2
100 pF
C1
22 pF
C2
47 pF
002aaa169
Fig 4. Crystal oscillator connection.
The generator divides the input 16× clock by any divisor from 1 to 216 − 1. The
SC16C750 divides the basic crystal or external clock by 16. The frequency of the
BAUDOUT output pin is exactly 16× (16 times) of the selected baud rate
(BAUDOUT = 16 Baud Rate). Customized baud rates can be achieved by selecting
the proper divisor values for the MSB and LSB sections of baud rate generator.
Programming the Baud Rate Generator registers DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate. The example in
Table 5 shows selectable baud rates when using a 1.8432 MHz crystal.
For custom baud rates, the divisor value can be calculated using the following
equation:
XTAL1 clock frequency
serial data rate × 16
Divisor (in decimal) =
(1)
----------------------------------------------------------
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
12 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
Table 5:
Baud rates using 1.8432 MHz or 3.072 MHz crystal
Using 3.072 MHz crystal
Using 1.8432 MHz crystal
Desired
baud rate
Divisor for
16× clock
Baud rate
error
Desired
baud rate
Divisor for
16× clock
Baud rate
error
50
2304
1536
1047
857
768
384
192
96
50
3840
2560
1745
1428
1280
640
320
160
107
96
75
75
110
0.026
0.058
110
0.026
0.034
134.5
150
134.5
150
300
300
600
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
64
0.312
58
0.69
48
80
32
53
0.628
1.23
24
40
16
27
12
20
6
10
3
5
2
2.86
6.6 DMA operation
The SC16C750 FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in
the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY
output pins. Tables 6 and 7 show this.
Table 6:
Effect of DMA mode on state of RXRDY pin
Non-DMA mode
DMA mode
1 = FIFO empty
0-to-1 transition when FIFO empties
0 = at least 1 byte in FIFO
1-to-0 transition when FIFO reaches trigger level,
or time-out occurs
Table 7:
Effect of DMA mode on state of TXRDY pin
Non-DMA mode
1 = at least 1 byte in FIFO
0 = FIFO empty
DMA mode
0-to-1 transition when FIFO becomes full
1-to-0 transition when FIFO goes below trigger level
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
13 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
6.7 Sleep mode
The SC16C750 is designed to operate with low power consumption. A special sleep
mode is included to further reduce power consumption when the chip is not being
used. With IER[4] enabled (set to a logic 1), the SC16C750 enters the sleep mode,
but resumes normal operation when a start bit is detected, a change of state on any
of the modem input pins RX, RI, CTS, DSR, DCD, or a transmit data is provided by
the user. If the sleep mode is enabled and the SC16C750 is awakened by one of the
conditions described above, it will return to the sleep mode automatically after the last
character is transmitted or read by the user. In any case, the sleep mode will not be
entered while an interrupt(s) is pending. The SC16C750 will stay in the sleep mode of
operation until it is disabled by setting IER[4] to a logic 0.
6.8 Loop-back mode
The internal loop-back capability allows on-board diagnostics. In the loop-back mode,
the normal modem interface pins are disconnected and reconfigured for loop-back
internally. MCR[0-3] register bits are used for controlling loop-back diagnostic testing.
In the loop-back mode, OUT1 and OUT2 in the MCR register (bits 2-3) control the
modem RI and DCD inputs, respectively. MCR signals DTR and RTS (bits 0-1) are
used to control the modem CTS and DSR inputs, respectively. The transmitter output
(TX) and the receiver input (RX) are disconnected from their associated interface
pins, and instead are connected together internally (see Figure 5). The CTS, DSR,
DCD, and RI are disconnected from their normal modem control input pins, and
instead are connected internally to DTR, RTS, OUT1 and OUT2. Loop-back test data
is entered into the transmit holding register via the user data bus interface, D0-D7.
The transmit UART serializes the data and passes the serial data to the receive
UART via the internal loop-back connection. The receive UART converts the serial
data back into parallel data that is then made available at the user data interface
D0-D7. The user optionally compares the received data to the initial transmitted data
for verifying error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read
using lower four bits of the Modem Status Register (MSR[0-3]) instead of the four
Modem Status Register bits 4-7. The interrupts are still controlled by the IER.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
14 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
SC16C750
TRANSMIT
FIFO
TRANSMIT
SHIFT
TX
REGISTERS
REGISTER
D0–D7
IOR, IOR
IOW, IOW
RESET
DATA BUS
AND
CONTROL LOGIC
FLOW
CONTROL
LOGIC
RECEIVE
SHIFT
REGISTER
RECEIVE
FIFO
REGISTERS
RX
A0–A2
CS0, CS1
FLOW
CONTROL
LOGIC
REGISTER
SELECT
LOGIC
CS2
AS
RTS
DDIS
DSR
DTR
MODEM
CONTROL
LOGIC
CTS
OUT1
RI
INT
TXRDY
RXRDY
CLOCK AND
BAUD RATE
GENERATOR
INTERRUPT
CONTROL
LOGIC
OUT2
DCD
002aaa337
XTAL1
RCLK
XTAL2
BAUDOUT
Fig 5. Internal loop-back mode diagram.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
15 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
7. Register descriptions
Table 8 details the assigned bit functions for the fifteen SC16C750 internal registers.
The assigned bit functions are more fully defined in Section 7.1 through Section 7.11.
Table 8:
SC16C750 internal registers
A2 A1 A0 Register Default[1] Bit 7
General Register Set[2]
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
1
RHR
THR
IER
XX
XX
00
bit 7
bit 7
0
bit 6
bit 6
0
bit 5
bit 5
bit 4
bit 4
bit 3
bit 3
bit 2
bit 2
bit 1
bit 1
bit 0
bit 0
low
power
mode
Sleep
mode
modem receive
status line
interrupt status
interrupt
XMIT
transmit receive
holding holding
register register
0
0
0
1
1
1
1
1
0
0
0
0
1
0
1
FCR
ISR
00
01
00
00
60
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
64-byte reserved DMA
FIFO
enable
RCVR
FIFO
reset
FIFO
enable
mode
select
FIFO
reset
FIFOs
FIFOs
64-byte
0
INT
priority
bit 2
INT
priority
bit 1
INT
priority
bit 0
INT
status
enabled enabled FIFO
enable
LCR
MCR
LSR
divisor
latch
enable
set break set parity even
parity
parity
enable
stop bits word
length
word
length
bit 0
bit 1
0
0
reserved loop back OUT2,
OUT1
RTS
DTR
INT
enable
FIFO
data
error
trans.
empty
trans.
holding
empty
break
interrupt error
framing parity
overrun receive
error
error
data
ready
1
1
1
1
0
1
MSR
SPR
X0
FF
DCD
bit 7
RI
DSR
bit 5
CTS
bit 4
∆DCD
∆RI
∆DSR
∆CTS
bit 6
bit 3
bit 2
bit 1
bit 0
Special Register Set[3]
0
0
0
DLL
XX
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 9
bit 0
bit 8
0
0
1
DLM
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
Enhanced Register Set[4]
0
1
0
EFR 00
Auto
CTS
Auto RTS 0
0
0
0
0
0
[1] The value shown represents the register’s initialized HEX value; X = n/a.
[2] These registers are accessible only when LCR[7] = 0.
[3] The Special Register set is accessible only when LCR[7] is set to a logic 1.
[4] Enhanced Feature Register is accessible only when LCR is set to ‘BFHex’.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
16 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR
register will be set to a logic 1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can be performed when the THR
empty flag is set (logic 0 = FIFO full; logic 1 = at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C750 and receive FIFO by reading the RHR
register. The receive section provides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal receiver counter starts counting
clocks at the 16× clock rate. After 7-1⁄2 clocks, the start bit time should be shifted to
the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0
it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INT output pin.
Table 9:
Interrupt Enable Register bits description
Description
Bit
Symbol
7-6
IER[7],
Not used.
IER[6]
IER[5]
5
4
3
Low power mode.
Logic 0 = Disable low power mode (normal default condition).
Logic 1 = Enable low power mode.
IER[4]
IER[3]
Sleep mode.
Logic 0 = Disable sleep mode (normal default condition).
Logic 1 = Enable sleep mode. See Section 6.7 “Sleep mode” for details.
Modem Status Interrupt.
Logic 0 = Disable the modem status register interrupt (normal default
condition).
Logic 1 = Enable the modem status register interrupt.
2
IER[2]
Receive Line Status interrupt. This interrupt will be issued whenever a fully
assembled receive character is transferred from RSR to the RHR/FIFO,
i.e., data ready, LSR[0].
Logic 0 = Disable the receiver line status interrupt (normal default
condition).
Logic 1 = Enable the receiver line status interrupt.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
17 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
Table 9:
Interrupt Enable Register bits description…continued
Bit
Symbol Description
1
IER[1]
Transmit Holding Register interrupt. This interrupt will be issued whenever
the THR is empty, and is associated with LSR[1].
Logic 0 = Disable the transmitter empty interrupt (normal default
condition).
Logic 1 = Enable the transmitter empty interrupt.
0
IER[0]
Receive Holding Register interrupt. This interrupt will be issued when the
FIFO has reached the programmed trigger level, or is cleared when the
FIFO drops below the trigger level in the FIFO mode of operation.
Logic 0 = Disable the receiver ready interrupt (normal default condition).
Logic 1 = Enable the receiver ready interrupt.
7.2.1 IER versus Receive FIFO interrupt mode operation
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)
are enabled, the receive interrupts and register status will reflect the following:
• The receive data available interrupts are issued to the external CPU when the
FIFO has reached the programmed trigger level. It will be cleared when the FIFO
drops below the programmed trigger level.
• FIFO status will also be reflected in the user accessible ISR register when the
FIFO trigger level is reached. Both the ISR register status bit and the interrupt will
be cleared when the FIFO drops below the trigger level.
• The data ready bit (LSR[0]) is set as soon as a character is transferred from the
shift register to the receive FIFO. It is reset when the FIFO is empty.
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C750 in the FIFO polled
mode of operation. Since the receiver and transmitter have separate bits in the LSR,
either or both can be used in the polled mode by selecting respective transmit or
receive control bit(s).
• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
• LSR[1-4] will provide the type of errors encountered, if any.
• LSR[5] will indicate when the transmit FIFO is empty.
• LSR[6] will indicate when both the transmit FIFO and transmit shift register are
empty.
• LSR[7] will indicate any FIFO data errors.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
18 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO
trigger levels, and select the DMA mode.
7.3.1 DMA mode
Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or
receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) will
go to a logic 0 whenever an empty transmit space is available in the Transmit Holding
Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.
Mode 1 (FCR bit 3 = 1): Set and enable the interrupt in a block mode operation. The
transmit interrupt is set when the transmit FIFO is below the programmed trigger
level. The receive interrupt is set when the receive FIFO fills to the programmed
trigger level. However, the FIFO continues to fill regardless of the programmed level
until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill level is above
the programmed trigger level.
7.3.2 FIFO mode
Table 10: FIFO Control Register bits description
Bit
Symbol
Description
7-6
FCR[7]
(MSB),
FCR[6]
(LSB)
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to Table 11.
5
FCR[5]
Logic 0 = 16-byte mode (normal default condition).
Logic 1 = 64-byte mode.
4
3
FCR[4]
FCR[3]
Reserved.
DMA mode select.
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C750 is in the 16C450
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO or transmit holding register, the TXRDY
pin will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after
the first character is loaded into the transmit holding register.
Receive operation in mode ‘0’: When the SC16C750 is in 16C450
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and
there is at least one character in the receive FIFO, the RXRDY pin will
be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
19 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
Table 10: FIFO Control Register bits description…continued
Bit
Symbol
Description
Transmit operation in mode ‘1’: When the SC16C750 is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1
when the transmit FIFO is completely full. It will be a logic 0 when the
trigger level has been reached.
Receive operation in mode ‘1’: When the SC16C750 is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-Out has occurred, the RXRDY pin will go to
a logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO.
2
1
0
FCR[2]
FCR[1]
FCR[0]
XMIT FIFO reset.
Logic 0 = No FIFO transmit reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets the
FIFO counter logic (the transmit shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
RCVR FIFO reset.
Logic 0 = No FIFO receive reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
FIFO enable.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO. This bit must be a
‘1’ when other FCR bits are written to, or they will not be
programmed.
Table 11: RCVR trigger levels
FCR[7]
FCR[6]
RX FIFO trigger level (bytes)
16-byte operation
64-byte operation
0
0
1
1
0
1
0
1
1
1
4
16
32
56
8
14
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
20 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
7.4 Interrupt Status Register (ISR)
The SC16C750 provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the interrupt status register is read,
the interrupt status is cleared. However, it should be noted that only the current
pending interrupt is cleared by the read. A lower level interrupt may be seen after
re-reading the interrupt status bits. Table 12 “Interrupt source” shows the data values
(bits 0-5) for the six prioritized interrupt levels and the interrupt sources associated
with each of these interrupt levels.
Table 12: Interrupt source
Priority
level
ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt
1
2
2
3
0
0
1
0
1
1
1
0
1
0
0
1
0
0
0
0
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time-out)
TXRDY (Transmitter Holding Register
Empty)
4
0
0
0
0
MSR (Modem Status Register)
Table 13: Interrupt Status Register bits description
Bit
Symbol
Description
7-6
ISR[7-6]
FIFOs enabled. These bits are set to a logic 0 when the FIFO is
not being used. They are set to a logic 1 when the FIFOs are
enabled.
Logic 0 or cleared = default condition.
64-byte FIFO enable.
5
ISR[5]
Logic 0 = 16-byte operation.
Logic 1 = 64-byte operation.
Not used.
4
ISR[4]
3-1
ISR[3-1]
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 12).
Logic 0 or cleared = default condition.
INT status.
0
ISR[0]
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
21 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 14: Line Control Register bits description
Bit
Symbol
Description
7
LCR[7] [1]
Divisor latch enable. The internal baud rate counter latch and Enhance
Feature mode enable.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch and enhanced feature register enabled.
6
5
LCR[6]
LCR[5]
Set break. When enabled, the Break control bit causes a break condition
to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic 0.
Logic 0 = no TX break condition (normal default condition).
Logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition.
Set parity. If the parity bit is enabled, LCR[5] selects the forced parity
format. Programs the parity conditions (see Table 15).
Logic 0 = parity is not forced (normal default condition).
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1
for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0
for the transmit and receive data.
4
LCR[4]
Even parity. If the parity bit is enabled with LCR[3] set to a logic 1,
LCR[4] selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd number of
logic 1s in the transmitted data. The receiver must be programmed to
check the same format (normal default condition).
Logic 1 = EVEN Parity is generated by forcing an even number of
logic 1s in the transmitted data. The receiver must be programmed to
check the same format.
3
LCR[3]
Parity enable. Parity or no parity can be selected via this bit.
Logic 0 = no parity (normal default condition).
Logic 1 = a parity bit is generated during the transmission, receiver
checks the data and parity for transmission errors.
2
LCR[2]
Stop bits. The length of stop bit is specified by this bit in conjunction with
the programmed word length (see Table 16).
Logic 0 or cleared = default condition.
1-0
LCR[1-0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Table 17).
Logic 0 or cleared = default condition.
[1] When LCR[7] = 1, the general register set cannot be accessed until LCR[7] = 0.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
22 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
Table 15: LCR[5] parity selection
LCR[5]
LCR[4]
LCR[3]
Parity selection
no parity
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
ODD parity
EVEN parity
force parity ‘1’
forced parity ‘0’
Table 16: LCR[2] stop bit length
LCR[2]
Word length
5, 6, 7, 8
5
Stop bit length (bit times)
0
1
1
1
1-1⁄2
6, 7, 8
2
Table 17: LCR[1-0] word length
LCR[1]
LCR[0]
Word length
0
0
1
1
0
1
0
1
5
6
7
8
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
23 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 18: Modem Control Register bits description
Bit
7
Symbol
MCR[7]
MCR[6]
MCR[5]
MCR[4]
Description
Reserved. Set to 0.
Reserved. Set to 0.
Reserved. Set to 0.
6
5
4
Loop-back. Enable the local loop-back mode (diagnostics). In this
mode the transmitter output (TX) and the receiver input (RX), CTS,
DSR, DCD, and RI are disconnected from the SC16C750 I/O pins.
Internally the modem data and control pins are connected into a
loop-back data configuration (see Figure 5). In this mode, the receiver
and transmitter interrupts remain fully operational. The Modem
Control Interrupts are also operational, but the interrupts’ sources are
switched to the lower four bits of the Modem Control. Interrupts
continue to be controlled by the IER register.
Logic 0 = Disable loop-back mode (normal default condition).
Logic 1 = Enable local loop-back mode (diagnostics).
3
MCR[3]
OUT2, INTx enable. Used to control the modem DCD signal in the
loop-back mode.
Logic 0 = Forces INT output to the 3-State mode. In the loop-back
mode, sets OUT2 (DCD) internally to a logic 1.
Logic 1 = Forces the INT output to the active mode. In the
loop-back mode, sets OUT2 (DCD) internally to a logic 0.
2
1
MCR[2]
MCR[1]
OUT1. This bit is used in the Loop-back mode only. In the loop-back
mode, this bit is used to write the state of the modem RI interface
signal via OUT1.
RTS
Logic 0 = Force RTS output to a logic 1 (normal default condition).
Logic 1 = Force RTS output to a logic 0.
DTR
0
MCR[0]
Logic 0 = Force DTR output to a logic 1 (normal default condition).
Logic 1 = Force DTR output to a logic 0.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
24 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C750 and
the CPU.
Table 19: Line Status Register bits description
Bit
Symbol
Description
7
LSR[7]
FIFO data error.
Logic 0 = No error (normal default condition).
Logic 1 = At least one parity error, framing error or break indication is in
the current FIFO data. This bit is cleared when LSR register is read.
6
5
LSR[6]
LSR[5]
THR and TSR empty. This bit is the Transmit Empty indicator. This bit is
set to a logic 1 whenever the transmit holding register and the transmit
shift register are both empty. It is reset to logic 0 whenever either the THR
or TSR contains a data character. In the FIFO mode, this bit is set to ‘1’
whenever the transmit FIFO and transmit shift register are both empty.
THR empty. This bit is the Transmit Holding Register Empty indicator.
This bit indicates that the UART is ready to accept a new character for
transmission. In addition, this bit causes the UART to issue an interrupt to
CPU when the THR interrupt enable is set. The THR bit is set to a logic 1
when a character is transferred from the transmit holding register into the
transmitter shift register. The bit is reset to a logic 0 concurrently with the
loading of the transmitter holding register by the CPU. In the FIFO mode,
this bit is set when the transmit FIFO is empty; it is cleared when at least
1 byte is written to the transmit FIFO.
4
3
2
1
LSR[4]
LSR[3]
LSR[2]
LSR[1]
Break interrupt.
Logic 0 = No break condition (normal default condition).
Logic 1 = The receiver received a break signal (RX was a logic 0 for
one character frame time). In the FIFO mode, only one break character
is loaded into the FIFO.
Framing error.
Logic 0 = No framing error (normal default condition).
Logic 1 = Framing error. The receive character did not have a valid stop
bit(s). In the FIFO mode, this error is associated with the character at
the top of the FIFO.
Parity error.
Logic 0 = No parity error (normal default condition).
Logic 1 = Parity error. The receive character does not have correct
parity information and is suspect. In the FIFO mode, this error is
associated with the character at the top of the FIFO.
Overrun error.
Logic 0 = No overrun error (normal default condition).
Logic 1 = Overrun error. A data overrun error occurred in the receive
shift register. This happens when additional data arrives while the FIFO
is full. In this case, the previous data in the shift register is overwritten.
Note that under this condition, the data byte in the receive shift register
is not transferred into the FIFO, therefore the data in the FIFO is not
corrupted by the error.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
25 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
Table 19: Line Status Register bits description…continued
Bit
Symbol
Description
0
LSR[0]
Receive data ready.
Logic 0 = No data in receive holding register or FIFO (normal default
condition).
Logic 1 = Data has been received and is saved in the receive holding
register or FIFO.
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the
modem, or other peripheral device to which the SC16C750 is connected. Four bits of
this register are used to indicate the changed information. These bits are set to a
logic 1 whenever a control input from the modem changes state. These bits are set to
a logic 0 whenever the CPU reads this register.
Table 20: Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
Data Carrier Detect. DCD (Active-HIGH, logical 1). Normally this bit is
the complement of the DCD input. In the loop-back mode this bit is
equivalent to the OUT2 bit in the MCR register.
6
5
4
MSR[6]
MSR[5]
MSR[4]
Ring Indicator. RI (Active-HIGH, logical 1). Normally this bit is the
complement of the RI input. In the loop-back mode this bit is equivalent
to the OUT1 bit in the MCR register.
Data Set Ready. DSR (Active-HIGH, logical 1). Normally this bit is the
complement of the DSR input. In loop-back mode this bit is equivalent to
the DTR bit in the MCR register.
Clear To Send. CTS. CTS functions as hardware flow control signal input
if it is enabled via EFR[7]. Flow control (when enabled) allows starting
and stopping the transmissions based on the external modem CTS
signal. A logic 1 at the CTS pin will stop SC16C750 transmissions as
soon as current character has finished transmission. Normally MSR[4] is
the complement of the CTS input. However, in the loop-back mode, this
bit is equivalent to the RTS bit in the MCR register.
3
2
MSR[3]
MSR[2]
∆DCD [1]
Logic 0 = No DCD change (normal default condition).
Logic 1 = The DCD input to the SC16C750 has changed state since
the last time it was read. A modem Status Interrupt will be generated.
∆RI [1]
Logic 0 = No RI change (normal default condition).
Logic 1 = The RI input to the SC16C750 has changed from a logic 0 to
a logic 1. A modem Status Interrupt will be generated.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
26 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
Table 20: Modem Status Register bits description…continued
Bit
Symbol
Description
1
MSR[1]
∆DSR [1]
Logic 0 = No DSR change (normal default condition).
Logic 1 = The DSR input to the SC16C750 has changed state since
the last time it was read. A modem Status Interrupt will be generated.
0
MSR[0]
∆CTS [1]
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C750 has changed state since
the last time it was read. A modem Status Interrupt will be generated.
[1] Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
7.9 Scratchpad Register (SPR)
The SC16C750 provides a temporary data register to store 8 bits of user information.
7.10 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Table 21: Enhanced Feature Register bits description
Bit
Symbol Description
7
EFR[7]
Automatic CTS flow control.
Logic 0 = Automatic CTS flow control is disabled (normal default
condition).
Logic 1 = Enable Automatic CTS flow control. Transmission will stop
when CTS goes to a logical 1. Transmission will resume when the CTS
pin returns to a logical 0.
6
EFR[6]
Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will
be generated when the receive FIFO is filled to the programmed trigger
level and RTS will go to a logic 1 at the next trigger level. RTS will return to
a logic 0 when data is unloaded below the next lower trigger level
(programmed trigger level 1). The state of this register bit changes with the
status of the hardware flow control. RTS functions normally when
hardware flow control is disabled.
0 = Automatic RTS flow control is disabled (normal default condition).
1 = Enable Automatic RTS flow control.
5-0
EFR[5-0] Reserved; set to 0.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
27 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
7.11 SC16C750 external reset conditions
Table 22: Reset state for registers
Register
IER
Reset state
IER[7-0] = 0
ISR
ISR[7-1] = 0; ISR[0] = 1
LCR[7-0] = 0
LCR
MCR
LSR
MCR[7-0] = 0
LSR[7] = 0; LSR[6-5] = 1; LSR[4-0] = 0
MSR[7-4] = input signals; MSR[3-0] = 0
FCR[7-0] = 0
MSR
FCR
EFR
EFR[7-0] = 0
Table 23: Reset state for outputs
Output
TX
Reset state
HIGH
RTS
HIGH
DTR
HIGH
RXRDY
TXRDY
INT
HIGH (STD mode)
LOW (STD mode)
LOW (STD mode)
8. Limiting values
Table 24: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCC
Parameter
Conditions
Min
Max
Unit
V
supply voltage
-
7
Vn
voltage at any pin
operating temperature
storage temperature
GND − 0.3 VCC + 0.3
V
Tamb
−40
−65
-
+85
°C
°C
mW
Tstg
+150
500
Ptot(pack)
total power dissipation per
package
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
28 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
9. Static characteristics
Table 25: DC electrical characteristics
Tamb = −40 °C to +85 °C; VCC = 2.5V, 3.3 V or 5.0 V ±10%, unless otherwise specified.
Symbol Parameter
Conditions
2.5 V
Max
3.3 V
Max
5.0 V
Max
Unit
Min
−0.3
1.8
−0.3
1.6
-
Min
−0.3
2.4
−0.3
2.0
-
Min
−0.5
3.0
−0.5
2.2
-
VIL(CK)
VIH(CK)
VIL
LOW-level clock input voltage
0.45
VCC
0.65
-
0.6
VCC
0.8
-
0.6
V
V
V
V
V
HIGH-level clock input voltage
LOW-level input voltage
HIGH-level input voltage
VCC
0.8
VIH
VCC
0.4
VOL
LOW-level output voltage on all IOL = 5 mA
outputs[1]
-
-
(databus)
OL = 4 mA
(other outputs)
OL = 2 mA
(databus)
OL = 1.6 mA
I
-
-
-
0.4
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
I
-
0.4
-
-
-
-
-
-
-
-
I
-
0.4
-
-
(other outputs)
VOH
HIGH-level output voltage
IOH = −5 mA
(databus)
-
-
-
-
-
-
2.4
I
OH = −1 mA
(other outputs)
OH = −800 µA
(databus)
OH = −400 µA
(other outputs)
-
2.0
-
-
-
I
1.85
1.85
-
-
I
ILIL
LOW-level input leakage current
clock leakage
-
±10
±30
3.5
5
-
±10
±30
4.5
5
-
±10
±30
4.5
5
µA
µA
mA
pF
kΩ
ICL
-
-
-
ICC
average power supply current
-
-
-
Ci
input capacitance
internal pull-up resistance[2]
-
-
-
Rpu(int)
500
-
500
-
500
-
[1] Except for x2, VOL = 1 V typically.
[2] Refer to Table 2 “Pin description” on page 5 for a listing of pins having internal pull-up resistors.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
29 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
10. Dynamic characteristics
Table 26: AC electrical characteristics
Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5 V ±10%, unless otherwise specified.
Symbol
Parameter
Conditions
2.5 V
3.3 V
5.0 V
Unit
Min Max
Min Max
Min Max
t1w, t2w
t3w
clock pulse duration
oscillator/clock frequency
address strobe width
address set-up time
address hold time
15
-
-
13
-
-
10
-
-
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[1]
16
32
-
48
-
t4w
45
5
-
35
5
25
1
t5s
-
-
-
t5h
5
-
5
-
5
-
t6s
chip select set-up time to AS
address hold time
10
0
-
5
-
0
-
t6h
-
0
-
0
-
[2]
t6s'
address set-up time
chip select hold time
IOR delay from chip select
IOR strobe width
10
0
-
10
0
-
5
-
t6h
-
-
0
-
t7d
10
77
0
-
10
26
0
-
10
23
0
-
t7w
25 pF load
-
-
-
t7h
chip select hold time from IOR
address hold time
-
-
-
[2]
t7h'
5
-
5
-
5
-
t8d
IOR delay from address
read cycle delay
10
20
-
-
10
20
-
-
10
20
-
-
t9d
25 pF load
25 pF load
25 pF load
25 pF load
-
-
-
t11d
t12d
t12h
t13d
t13w
t13h
t14d
t15d
t16s
t16h
t17d
t18d
IOR to DDIS delay
100
35
26
15
-
30
23
15
-
delay from IOR to data
data disable time
-
77
-
-
-
15
-
-
IOW delay from chip select
IOW strobe width
10
20
0
-
10
20
0
10
15
0
[3]
[4]
-
-
-
chip select hold time from IOW
IOW delay from address
write cycle delay
-
-
-
10
25
20
15
-
-
10
25
20
5
-
10
20
15
5
-
-
-
-
data set-up time
-
-
-
data hold time
-
-
-
delay from IOW to output
25 pF load
25 pF load
100
100
-
33
24
-
29
23
delay to set interrupt from Modem
input
-
-
-
t19d
t20d
t21d
t22d
t23d
t24d
t25d
t26d
t27d
delay to reset interrupt from IOR
delay from stop to set interrupt
delay from IOR to reset interrupt
delay from start to set interrupt
delay from IOW to transmit start
delay from IOW to reset interrupt
delay from stop to set RXRDY
delay from IOR to reset RXRDY
delay from IOW to set TXRDY
25 pF load
25 pF load
-
-
-
-
8
-
-
-
-
100
1
-
-
-
-
8
-
-
-
-
24
1
-
-
-
-
8
-
-
-
-
23
1
ns
Rclk
ns
100
100
24
29
45
24
45
1
28
40
24
40
1
ns
Rclk
ns
100
1
Rclk
ns
100
100
45
45
40
40
ns
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
30 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
Table 26: AC electrical characteristics…continued
Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5 V ±10%, unless otherwise specified.
Symbol
Parameter
Conditions
2.5 V
3.3 V
5.0 V
Unit
Min Max
Min Max
Min Max
t28d
tRESET
N
delay from start to reset TXRDY
Reset pulse width
-
8
-
8
-
8
Rclk
ns
100
1
-
40
1
-
40
1
-
baud rate divisor
216 − 1
216 − 1
216 − 1 Rclk
[1] Applies to external clock, crystal oscillator max 24 MHz.
[2] Applicable only when AS is tied LOW.
1
[3] IOWstrobemax
=
--------------------------------------
2(Baudratemax
)
= 333 ns (for Baudratemax = 1.5 Mbits/s)
= 1 µs (for Baudratemax = 460.8 kbits/s)
= 4 µs (for Baudratemax = 115.2 kbits/s)
[4] When in both DMA mode 0 and FIFO enable mode, the write cycle delay should be larger than one x1 clock cycle.
10.1 Timing diagrams
t
4w
AS
t
5s
t
5h
VALID
ADDRESS
A0–A2
t
6s
t
6h
CS2
CS1–CS0
VALID
t
7d
t
7h
t
7w
t
8d
t
9d
IOR, IOR
ACTIVE
t
11d
t
11d
DDIS
ACTIVE
t
t
12h
12d
D0–D7
DATA
002aaa331
Fig 6. General read timing when using AS signal.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
31 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
t
4w
AS
t
5s
t
5h
VALID
ADDRESS
A0–A2
t
6s
t
6h
CS2
CS1–CS0
VALID
t
t
13h
13d
t
13w
t
t
15d
14d
IOW, IOW
ACTIVE
t
t
16h
16s
D0–D7
DATA
002aaa332
Fig 7. General write timing when using AS signal.
VALID
ADDRESS
VALID
ADDRESS
A0–A2
t
′
7h
t
′
6s
t
′
7h
t
′
6s
t
7w
ACTIVE
ACTIVE
CS
t
7w
t
9d
IOR
ACTIVE
t
12h
t
t
t
12h
12d
12d
D0–D7
DATA
002aaa333
Fig 8. General read timing when AS is tied to GND.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
32 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
VALID
ADDRESS
VALID
ADDRESS
A0–A2
t
′
7h
t
′
6s
t
′
7h
t
′
6s
ACTIVE
ACTIVE
CS
t
t
t
13w
13w
15d
IOW
ACTIVE
t
16h
t
t
t
16h
16s
16s
D0–D7
DATA
002aaa334
Fig 9. General write timing when AS is tied to GND.
IOW
ACTIVE
t
17d
RTS
DTR
CHANGE OF STATE
CHANGE OF STATE
DCD
CTS
DSR
CHANGE OF STATE
CHANGE OF STATE
t
t
18d
18d
INT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
t
19d
IOR
ACTIVE
t
18d
RI
CHANGE OF STATE
002aaa111
Fig 10. Modem input/output timing.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
33 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
t
t
1w
2w
EXTERNAL
CLOCK
002aaa112
t
3w
Fig 11. External clock timing.
NEXT
DATA
START
BIT
PARITY STOP START
BIT
BIT
BIT
DATA BITS (5-8)
RX
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS
7 DATA BITS
t
20d
ACTIVE
INT
t
21d
ACTIVE
IOR
16 BAUD RATE CLOCK
002aaa113
Fig 12. Receive timing.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
34 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
NEXT
DATA
START
BIT
PARITY STOP START
BIT
BIT
BIT
DATA BITS (5–8)
RX
D0
D1
D2
D3
D4
D5
D6
D7
t
25d
ACTIVE
DATA
READY
RXRDY
t
26d
ACTIVE
IOR
002aaa114
Fig 13. Receive ready timing in non-FIFO mode.
START
BIT
PARITY STOP
BIT BIT
DATA BITS (5–8)
RX
D0
D1
D2
D3
D4
D5
D6
D7
FIRST BYTE THAT
REACHES THE
TRIGGER LEVEL
t
25d
ACTIVE
DATA
READY
RXRDY
t
26d
ACTIVE
IOR
002aaa115
Fig 14. Receive ready timing in FIFO mode.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
35 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
NEXT
DATA
START
BIT
PARITY STOP START
BIT
BIT
BIT
DATA BITS (5–8)
TX
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS
7 DATA BITS
ACTIVE TX READY
INT
t
22d
t
24d
t
23d
ACTIVE
ACTIVE
IOW
16 BAUD RATE CLOCK
002aaa116
Fig 15. Transmit timing.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
36 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
NEXT
DATA
START
BIT
PARITY STOP START
BIT
BIT
BIT
DATA BITS (5–8)
TX
D0
D1
D2
D3
D4
D5
D6
D7
ACTIVE
IOW
D0–D7
TXRDY
TRANSMITTER READY
BYTE #1
t
28d
t
27d
ACTIVE
TRANSMITTER
NOT READY
002aaa129
Fig 16. Transmit ready timing in non-FIFO mode.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
37 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
START
BIT
PARITY STOP
BIT BIT
DATA BITS (5-8)
TX
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS
7 DATA BITS
ACTIVE
IOW
D0–D7
TXRDY
t
28d
BYTE #16
t
27d
FIFO FULL
002aaa118
Fig 17. Transmit ready timing in FIFO mode (DMA mode ‘1’).
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
38 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
11. Package outline
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
e
e
E
D
y
X
A
39
29
b
p
Z
E
28
40
b
1
w
M
44
1
H
E
E
pin 1 index
A
A
1
A
4
e
(A )
3
6
18
β
L
p
k
detail X
7
17
v
M
A
e
Z
D
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm dimensions are derived from the original inch dimensions)
(1)
(1)
A
A
Z
Z
E
4
1
(1)
(1)
D
UNIT
mm
A
A
b
D
E
e
e
e
H
H
k
L
p
v
w
y
β
b
3
1
D
E
D
E
p
max.
min.
max. max.
4.57
4.19
0.81 16.66 16.66
0.66 16.51 16.51
16.00 16.00 17.65 17.65 1.22 1.44
14.99 14.99 17.40 17.40 1.07 1.02
0.53
0.33
0.51 0.25 3.05
0.02 0.01 0.12
1.27
0.05
0.18 0.18
0.1
2.16 2.16
o
45
0.180
0.165
0.032 0.656 0.656
0.026 0.650 0.650
0.63 0.63 0.695 0.695 0.048 0.057
0.59 0.59 0.685 0.685 0.042 0.040
0.021
0.013
inches
0.007 0.007 0.004 0.085 0.085
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
01-11-14
SOT187-2
112E10
MS-018
EDR-7319
Fig 18. PLCC44 (SOT187-2).
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
39 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
y
X
A
48
33
Z
49
32
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
pin 1 index
L
64
17
detail X
1
16
Z
v
M
A
D
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
D
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 10.1 10.1
0.17 0.12 9.9 9.9
12.15 12.15
11.85 11.85
0.75
0.45
1.45 1.45
1.05 1.05
1.6
mm
0.25
0.5
1
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
03-02-25
SOT314-2
136E10
MS-026
Fig 19. LQFP64 (SOT314-2).
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
40 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
12. Soldering
12.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all IC packages. Wave soldering can still
be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In
these situations reflow soldering is recommended. In these situations reflow
soldering is recommended.
12.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder
paste material. The top-surface temperature of the packages should preferably be
kept:
• below 220 °C (SnPb process) or below 245 °C (Pb-free process)
– for all BGA and SSOP-T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 235 °C (SnPb process) or below 260 °C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.
12.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11623
Product data
Rev. 04 — 20 June 2003
41 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.
12.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
12.5 Package related soldering information
Table 27: Suitability of surface mount IC packages for wave and reflow soldering
methods
Package[1]
Soldering method
Wave
Reflow[2]
BGA, LBGA, LFBGA, SQFP, SSOP-T[3],
TFBGA, VFBGA
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP,
HSOP, HTQFP, HTSSOP, HVQFN, HVSON,
SMS
not suitable[4]
suitable
PLCC[5], SO, SOJ
suitable
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended[5][6]
not recommended[7]
SSOP, TSSOP, VSO, VSSOP
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
42 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
[3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow
oven. The package body peak temperature must be kept as low as possible.
[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.
[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
13. Revision history
Table 28: Revision history
Rev Date
CPCN
-
Description
04 20030620
Product data (9397 750 11623); ECN 853-2367 30035 of 16 June 2003.
Modifications:
• Figure 4 “Crystal oscillator connection.” on page 12: changed capacitors’ values and
added connection with resistor.
03 20030314
02 20021211
01 20020904
-
-
-
Product data (9397 750 11203); ECN 853-2367 29619 of 07 March 2003.
Product data (9397 750 10797); ECN 853-2367 29261 of 06 December 2002.
Product data (9397 750 10149); ECN 853-2367 28865 of 04 September 2002.
9397 750 11623
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 20 June 2003
43 of 45
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
14. Data sheet status
Level Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
15. Definitions
16. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
44 of 45
9397 750 11623
Product data
Rev. 04 — 20 June 2003
SC16C750
UART with 64-byte FIFO
Philips Semiconductors
Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 28
Static characteristics . . . . . . . . . . . . . . . . . . . 29
Dynamic characteristics. . . . . . . . . . . . . . . . . 30
Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 31
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 39
9
10
10.1
11
12
12.1
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Introduction to soldering surface mount
packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 41
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 41
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 42
Package related soldering information. . . . . . 42
6
Functional description . . . . . . . . . . . . . . . . . . . 9
Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 9
FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 10
Hardware flow control. . . . . . . . . . . . . . . . . . . 11
Time-out interrupts . . . . . . . . . . . . . . . . . . . . . 11
Programmable baud rate generator . . . . . . . . 12
DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 13
Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Loop-back mode. . . . . . . . . . . . . . . . . . . . . . . 14
12.2
12.3
12.4
12.5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
13
14
15
16
Revision history . . . . . . . . . . . . . . . . . . . . . . . 43
Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 44
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7
7.1
Register descriptions . . . . . . . . . . . . . . . . . . . 16
Transmit (THR) and Receive (RHR)
Holding Registers . . . . . . . . . . . . . . . . . . . . . 17
Interrupt Enable Register (IER) . . . . . . . . . . . 17
IER versus Receive FIFO interrupt
7.2
7.2.1
mode operation . . . . . . . . . . . . . . . . . . . . . . . 18
IER versus Receive/Transmit FIFO polled
7.2.2
mode operation . . . . . . . . . . . . . . . . . . . . . . . 18
FIFO Control Register (FCR) . . . . . . . . . . . . . 19
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Interrupt Status Register (ISR) . . . . . . . . . . . . 21
Line Control Register (LCR) . . . . . . . . . . . . . . 22
Modem Control Register (MCR) . . . . . . . . . . . 24
Line Status Register (LSR). . . . . . . . . . . . . . . 25
Modem Status Register (MSR). . . . . . . . . . . . 26
Scratchpad Register (SPR) . . . . . . . . . . . . . . 27
Enhanced Feature Register (EFR) . . . . . . . . . 27
SC16C750 external reset conditions . . . . . . . 28
7.3
7.3.1
7.3.2
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
© Koninklijke Philips Electronics N.V. 2003.
Printed in the U.S.A
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 20 June 2003
Document order number: 9397 750 11623
相关型号:
©2020 ICPDF网 联系我们和版权申明