SAA2013H [NXP]
Adaptive allocation and scaling for PASC coding in DCC systems; 自适应分配和缩放PASC编码的DCC系统
| 型号： | SAA2013H |
| 厂家： | 
NXP |
| 描述： | Adaptive allocation and scaling for PASC coding in DCC systems |
| 文件： | 总32页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA2013
Adaptive allocation and scaling for
PASC coding in DCC systems
May 1994
Preliminary specification
File under Integrated Circuits, IC01
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
FEATURES
• Wide operating voltage range: 2.7 to 5.5 V
• Low power consumption: 13 mW; 3.0 V
• Low power decode mode: 1 mW; 5.0 V
• Sleep mode for low power and low Electromagnetic
Interference (EMI)
GENERAL DESCRIPTION
The SAA2013 performs the adaptive allocation and
scaling function in the Precision Adaptive Sub-band
Coding (PASC) system. It is not required in playback only
applications, and is only used during recording. To
complete the PASC processor, a SAA2003 stereo filter
and codec is required.
• Sophisticated allocation algorithm
• Optimum sound quality
• Three-wire L3 bus microcontroller interface
• Stereo or 2-channel mono recording
• Small surface mounted package (QFP; SOT307).
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
PINS
PIN POSITION
QFP(1)
MATERIAL
CODE
SAA2013H
44
plastic
SOT307-2
Note
1. When using reflow soldering it is recommended that the Dry Packing instructions in the “Quality Reference
Pocketbook” are followed. The pocketbook can be ordered using the code 9398 510 34011.
May 1994
2
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
BLOCK DIAGRAM
FRESET
FDAI
V
V
V
DD1
14
DD2
24
DD3
40
FDIR FSYNC
FS256
39
37 36 35 34
3
4
5
L3MODEM
L3CLKM
32
31
30
26
MICROCONTROLLER
BUS
FDCL
FDWS
COMPENSATION
DELAY
L3DATAM
CONTROL
AND
SYNC
SLEEP
CLK24
RESET
SAA2013
23
33
FDAO
9
L3MODEC
L3CLKC
10
11
SFC
BUS
ALLOCATION AND SCALE FACTOR
COMPUTATION
L3DATAC
6
25
44
20
21
22
MGB355
NODONE RESOL0 RESOL1
V
V
V
SS3
SS1
SS2
Fig.1 Block diagram.
May 1994
3
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
PINNING
SYMBOL
TEST10
PIN
DESCRIPTION
TYPE
1
test input; connect to VSS
test input; connect to VSS
I
I
TEST11
L3MODEM
L3CLKM
L3DATAM
VSS1
2
3
microcontroller interface mode input
microcontroller interface clock input
microcontroller interface data 3-state input/output
supply ground
I
4
I
5
I/O
−
O
O
O
O
I/O
O
O
−
I
6
TEST12
TEST13
L3MODEC
L3CLKC
L3DATAC
TEST1
TEST2
VDD1
7
test output; do not connect
test output; do not connect
codec interface mode output
codec interface clock output
codec interface data 3-state input/output
test output; do not connect
test output; do not connect
supply voltage
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TEST3
TEST4
TEST5
TEST6
TEST7
NODONE
RESOL0
RESOL1
RESET
VDD2
test mode input; connect to VDD
test mode input; connect to VDD
test input; connect to VSS
test input; connect to VSS
test input; connect to VSS
nodone state selection input; connect to VDD
resolution selection 0 input
resolution selection 1 input
reset input; active HIGH
I
I
I
I
I
I
I
I
supply voltage
−
−
I
VSS2
supply ground
CLK24
LOWPWR
POR
24.576 MHz clock input
low power decode select input
power on reset input
I
I
TEST8
SLEEP
FDWS
test input; connect to VSS
sleep mode select input
I
I
filtered data word select
I
FDCL
filtered data clock
I
FDAO
filtered data output
O
I
FDAI
filtered data input
FSYNC
FRESET
FDIR
sub-band synchronization on filtered I2S bus
reset signal input from SAA2003
filtered data direction input
test input; connect to VSS
system clock input; 256 × sample frequency (fs)
supply voltage
I
I
I
TEST9
FS256
I
I
VDD3
−
May 1994
4
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
SYMBOL
n.c.
PIN
DESCRIPTION
TYPE
41
42
43
44
not connected
not connected
not connected
supply ground
−
−
−
−
n.c.
n.c.
VSS3
TEST10
1
FDAO
FDCL
33
32
TEST11
2
L3MODEM
31 FDWS
SLEEP
3
4
L3CLKM
30
29 TEST8
L3DATAM
5
V
POR
28
27
26
25
24
23
6
SS1
SAA2013
LOWPWR
CLK24
TEST12
TEST13
7
8
L3MODEC
V
9
SS2
V
L3CLKC
10
11
DD2
RESET
L3DATAC
MGB356
Fig.2 Pin configuration.
May 1994
5
RAM
41464
BUFFER
64K x 4
speed control
CAPSTAN
DRIVE
L
DAC
analog
output
TDA1305
sub-band
R
2
I S
SFC3
SAA2003
WRAMP
TDA1381
WRITE AMP.
baseband
STEREO
FILTER CODEC
2
I S
DRP
SAA2023
OR
L
FIXED
HEAD
TAPE
analog
input
ADC
SAA7366
SAA3323
DRIVE
PROCESSOR
2
R
filtered I S
RDAMP
TDA1380
READ AMP.
ADAS3
SAA2013
ADAPTIVE
ALLOCATION
DIGITAL
AUDIO I/O
TDA1315
MECHANICS
DRIVERS
IEC958
search data
analog CC
L output
detect
switch
analog CC
R output
AUDIO IN/OUT
PASC PROCESSOR
TAPE DRIVE PROCESSING
SYSTEM
MICROCONTROLLER
SYSTEM CONTROL
MBD620
Fig.3 DCC system block diagram.
ahdnbok,uflapegwidt
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
to determine the operation mode. When FDIR is HIGH,
SAA2013 is in decode mode. When FDIR is LOW the
SAA2013 is in encode mode. See Fig.4.
PASC processor
The PASC processor is a dedicated Digital Signal
Processor (DSP) engine which efficiently codes digital
audio data at a bit rate of 384 kbits/s without affecting the
sound quality. This is achieved using an efficient adaptive
data notation and by only encoding the audio information
which can be heard by the human ear.
Reset
When used with low-power mode disabled
(LOWPWR = VSS), and with the SLEEP input LOW,
SAA2013 is reset if the RESET pin is held HIGH for at least
5 periods of the CLK24 clock, see Fig.5. SAA2013 defaults
to decode mode. When in low-power mode, the RESET
pin is disabled.
The audio data is split into 32 equal sub-bands during
encoding. For each of the sub-bands a masking threshold
is calculated. The samples from each of the sub-bands are
included in the PASC data with an accuracy that is
determined by the available bit-pool and by the difference
between the signal power and the masking threshold for
that sub-band. In decode, the sub-band signals are
reconstructed into the full bandwidth audio signal.
Sleep mode
Sleep mode is entered by taking the SLEEP input HIGH
with the LOWPWR pin connected to VSS; CLK24 and
FS256 are stopped internally to the SAA2013, the 3-state
buffers will have a high impedance, and outputs will freeze
in the same state as just before the sleep mode became
active (clocks stopped). To come out of sleep mode, the
SLEEP input must be taken LOW again. To clear data
present from before sleep was entered, this should be
followed by a reset, see Fig.5.
The stereo filter codec performs the splitting (encoding)
and reconstruction (decoding), including the necessary
formatting functions. During encoding, the adaptive
allocation and scaling circuit calculates the required
accuracy (bit allocation) and scale factors of the
sub-band samples.
Decode/encode control
Selection of decode or encode is controlled using FRESET
and FDIR. FRESET causes a general reset. The FDIR
signal is sampled at the falling edge of the FRESET signal
t
H
FRESET
t
t
su
h
FDIR
MGB357
Fig.4 FDIR and FRESET timing.
May 1994
7
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
SLEEP
t
h
RESET
t
d
CLK24
MGB358
Fig.5 SLEEP and RESET timing.
Low-power decode mode
V
Low-power decode mode is made available by connecting
DD
handbook, halfpage
the LOWPWR pin to VDD. With LOWPWR = VDD
,
1 µF
low-power decode mode is entered 9 cycles of CLK24
after the SLEEP input is taken HIGH. In low-power decode
mode, the L3 bus connections are connected straight
trough the SAA2013, which is effectively bypassed. The
compensation delay connection between pins FDAI and
FDAO is no longer needed by the SAA2003, and CLK24
and FS256 are stopped internally to the SAA2013.
V
V
DD
POR
SS
150
kΩ
V
SS
MGB359
To get out of low-power decode mode, it is necessary to
take SLEEP LOW, FDIR LOW, and FRESET HIGH (in a
normal application taking FDIR LOW and FRESET HIGH
can be achieved by setting SAA2003 into encode mode),
SAA2013 then performs an internal reset, and defaults to
normal decode mode. The RESET pin does not reset the
circuit from low-power decode mode.
Fig.6 POR circuit.
Encode mode
In encode mode the SAA2013 receives sub-band filtered
samples from SAA2003 on the FDAI pin. The SAA2013
has to collect a complete frame of sub-band data before
the allocation and scale factor information can be
calculated. So that the allocation and scale factor
information is available in the same time frame as the
audio samples at the output, the sub-band filtered samples
are delayed by 480 FDWS periods.
Power-On Reset (POR)
When low-power decode mode is enabled
(LOWPWR = VDD), a power-on reset circuit is required to
ensure that the internal clocks are connected correctly at
power-on. A suitable circuit is shown in Fig.6. This circuit
will correctly reset the internal clock connection provided
that the nominal value of the VDD supply is reached within
40 ms at power-on.
1
fs
One FDWS period is equal to
where fs is the audio
---
sample rate of 32, 44.1 or 48 kHz. The delayed samples
are passed to the codec part of SAA2003 on the
FDAO pin.
May 1994
8
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
For each sub-band frame, SAA2013 calculates the
allocation and scale factor index information required by
the SAA2003. In order to synchronize the codec part of
SAA2003, SAA2013 frequently requests status
information from the codec. It monitors sample frequency,
emphasis information and stereo mode, and uses the
ready-to-receive bit of the codec to determine when to
transfer information.
Audio sample resolution section
The SAA2013 is designed for operation with audio input
sources of 14, 15, 16 or 18-bit resolution.
For optimum audio performance the bit allocation
algorithm of the SAA2013 can be varied to suit the bit
resolution of the audio source. This is done with the pins
RESOL0 and RESOL1 as shown in Table 1.
Table 1 Resolution set by pins RESOL0 and RESOL1.
Decode mode
In decode the SAA2003 will transfer samples from FDAI to
FDAO with a delay of 480 FDWS periods. Settings and
status information can be sent to SAA2003 via SAA2013,
but the SAA2013 does not itself act on this information.
Transfer of this information is automatically synchronized
to the ready-to-receive bit of SAA2003 by SAA2013.
RESOLUTION
RESOL0
RESOL1
16 bits
18 bits
14 bits
15 bits
0
0
1
1
0
1
0
1
Filtered data interface
The filtered data interface signals are given in Table 2.
Table 2 Filtered data interface signals.
PIN
INPUT/OUTPUT
FUNCTION
FREQUENCY
FDWS
FDCL
FDAI
input
input
input
filtered data interface word select
filtered data interface bit clock
filtered data input
fs
64fs
−
FDAO
output
input
filtered data output
−
FSYNC
filtered data sub-band synchronization
−
The filtered data interface transfers sub-band filtered
samples between the stereo filter codec SAA2003 and
SAA2013. The interface is similar to a normal I2S interface,
consisting of clock (FDCL), data (FDAI/FDAO) and word
select lines (FDWS), except that the samples sent
represent signals divided into 32 sub-bands. One frame of
data consists of 12 samples from 32 sub-bands for both
left and right channels, i.e.: 768 audio samples. Each
audio sub-band sample is represented by a 24-bit two’s
complement number.
Table 3 Order of samples.
SUB-BAND
0
0
1
1
2
2
... 31 31
Channel
Sample
L
0
1
2
.
R
0
1
2
.
L
0
1
2
.
R
0
1
2
.
L
0
1
2
.
R
0
1
2
.
...
...
...
...
...
...
L
0
1
2
.
R
0
1
2
.
.
.
.
.
.
.
.
.
The order in which the samples are sent is shown in
Table 3.
11 11 11 11 11 11 ... 11 11
For two channel mono, the order is the same, but with
Channel 1 samples in the place of left and Channel 2
samples in place of right.
The signal FSYNC is used between each PASC frame to
indicate the sending of samples for sub-band 0 (Fig.7).
May 1994
9
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
channel
32 bits
h
left
20
FDWS
FDCL
right
1
0
23
22
21
7 bit
1 bit
FSYNC
timing
L
L
L
L
L
FDWS
R
R
R
R
R
FSYNC
sub-band
31
0
1
31
0
T
c
t
t
cL
cH
FDCL
t
d4
t
d3
FDAO
t
t
su1
h1
FDAI
FDWS
MGB360
Fig.7 Filtered interface format.
Status information from the codec is interpreted to ensure
that SAA2013 quickly acts upon the status of SAA2003.
Control interfaces
Two 3-wire control interfaces are provided (referred to as
‘L3’ interfaces). One is connected to the system
microcontroller (L3MODEM, L3CLKM, L3DATAM where
‘M’ represents microcontroller), the other to SAA2003
(L3MODEC, L3CLKC, L3DATAC where ‘C’ represents
codec). In general, control data is passed between
SAA2003 and the microcontroller via SAA2013. This
ensures that the microcontroller is buffered from the
time-critical SAA2013 to SAA2003 interface during
encode.
The L3 bus operation is shown in Fig.8. There are three
modes:
1. Address.
2. Data.
3. Halt.
Each interface operates as either a master or a slave,
where the master provides L3CLK and L3MODE. For the
microcontroller to SAA2013 interface, the microcontroller
is the master. For the SAA2013 to SAA2003 interface,
SAA2013 is the master.
The SAA2013 does not interpret the data from the
microcontroller interface.
May 1994
10
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
L3MODE
L3CLK
L3DATA
0
1
2
3
4
5
6
7
MGB361
Fig.8 L3 bus operation; address mode.
L3MODE
L3CLK
L3DATA
0
1
2
3
4
5
6
7
MGB362
Fig.9 L3 single byte transfer.
L3MODE
L3CLK
L3DATA
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
MGB363
Fig.10 L3 bus two byte transfer.
11
May 1994
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
ADDRESS MODE
HALT MODE
Address mode is entered by the master pulling L3MODE
LOW. This causes the L3DATA line to act as an input on
the slave, and 8 bits of address data are clocked into the
slave. If the slave recognizes the address, it will set-up its
internal state based on the 2 Least Significant Bits (LSBs)
of the address. The slave than expects to send status data
or receive control data.
Halt mode consists of pulling L3MODE LOW after sending
data. It is used for marking the end of a data transfer mode
which does not have an internal bit counter.
SAA2013 interface modes
The SAA2013 may be used to read and write from or to
SAA2003. Information is transferred via a set of transit
registers within SAA2013.
The addresses for SAA2013 are shown in Table 4.
Table 4 SAA2013 addresses.
DECODE OPERATION
During decode, the SAA2013 does not perform allocation.
Therefore no allocation and scale factor indices are sent to
SAA2003. Settings and extended settings may still be sent
to SAA2003, and SAA2013 monitors the status of the
codec by reading status from it after every occurrence of
FSYNC. Peak level data can also be transferred from
SAA2003.
L3 OPERATION
MSB LSB
FUNCTION
MODE
0010 0000 WDAT
0010 0001 RDAT
0010 0010 WCMD
0010 0011 RSTAT
extended settings
allocation information
settings
status/peak read
ENCODE OPERATION
The interface may be reset by sending an address of all
zeros (‘00000000’). This may be used to allow
inter-operation with other devices sharing the L3CLK and
L3DATA lines (e.g. SAA7345 CD decoder).
In encode, the same information may be sent as for
decode, and in addition, allocation/scale factor indices are
sent to the codec by SAA2013.
The interface modes are shown in Table 5.
DATA MODE
In data mode, bytes of data are clocked into (e.g. control)
or out of (e.g. status) the slave. A single byte transfer is
shown in Fig.9. A two byte transfer is shown in Fig.10,
between bytes there must be a pause during which the
clock remains HIGH.
May 1994
12
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
Table 5 Interface modes.
ADDRESS
MODE
INTERFACE MODE
LENGTH (BITS)
DIRECTION
BIT 1
BIT 0
Decode
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
extended settings
−
8
microcontroller to SAA2003
−
−
settings
16
microcontroller to SAA2003
SAA2003 to microcontroller
microcontroller to SAA2003
SAA2013 to SAA2003
microcontroller to SAA2003
SAA2003 to microcontroller
status/peak
extended settings
allocation/scale
settings
16 or 48
8
Encode
48 × 16
16
status/peak
16 or 48
the transit registers, and sent next time that allocation is
being sent. In decode, settings are sent as soon as
possible subject to the RTRC flag from SAA2003.
PRIORITY
Each type of transfer has a priority. The priorities are:
1. Allocation/scale/settings (highest priority).
2. Status read.
Before sending settings the microcontroller should read
the status of SAA2013 to examine the Ready-To-Receive
bit Settings (RTRS). After the settings have been received
by SAA2013, RTRS will be made logic 0, until the settings
have been sent to SAA2003. Only after RTRS is logic 1
again may the microcontroller send new settings.
3. Peak read.
4. Extended settings (lowest priority).
ALLOCATION AND SCALE FACTOR TRANSFER
The allocation and scale factor information sent from
SAA2013 to SAA2003 during encode has the highest
priority. The other types of transfer interleaved with the
allocation/scale information.
STATUS READ
Status and peak information may be read from SAA2003
by the microcontroller. The status bits are defined in
Table 6.
SETTINGS TRANSFER
This is a 16-bit transfer. The microcontroller sends settings
to SAA2003. SAA2013 only transfers these without taking
notice of the contents. In encode, the settings are held in
Table 6 Status bits.
BIT
B15 to B12
B11 and B10
B9
NAME
bit rate index
FUNCTION
bit rate indication
VALID IN
encode/decode
sample frequency indication
RTRS (settings)
44.1, 48, 32 kHz indication
1 = ready; 0 = not ready
1 = ready; 0 = not ready
encode/decode
encode/decode
encode/decode
encode/decode
B8
RTRE (external settings)
MODE
B7 and B6
sub-band signal mode
identification
B5
SYNC
synchronization indication
1 = OK; 0 = not OK
transparent bits
encode/decode
encode/decode
encode/decode
encode/decode
B4
CLKOK
B3 and B2
B1 and B0
Tr0 and Tr1
EMPHASIS
emphasis indication
May 1994
13
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
Since the two bytes of status information are sampled
separately, the bytes may result from different sub-band
frames.
is possible that peak data may contain an additional delay
of 1 column (667 µs minimum at 48 kHz, 1 ms maximum
at 32 kHz). If the microcontroller attempts to read peak
level data with a delay of less than 1 column, the peak level
data from the previous reading will be repeated. Normally
the microcontroller should allow at least 1 ms between
reads. There is also a delay required between peak data
words (Fig.13).
The only valid bit rate code for the SAA2013 is 1100.
The sample frequency indication is shown in Table 7.
Table 7 Sample frequency indication.
If the SAA2013 does not have peak data available (for
instance the microcontroller attempts two reads in very
quick succession), it will return all peak data bits set to
logic 0. The microcontroller can detect if valid peak data
has been returned by inspecting bits T16 and T32. If both
bits are set to logic 0 the data is not valid.
BIT 11
BIT 10
SAMPLE FREQUENCY
0
0
1
1
0
1
0
1
44.1 kHz; default
48.0 kHz
32.0 kHz
do not use
Ready-to-receive S or E indicates whether the SAA2013 is
ready-to-receive new settings or extended settings from
the microcontroller. This should be checked before
sending new information.
MSB
LSB
handbook, halfpage
0 0 1 0 0 0 1 1
For details of the MODE, SYNC, CLKOK and transparent
bits, refer to the “SAA2003 data sheet”.
STATUS MSB
PEAK BYTE 1
PEAK BYTE 3
STATUS LSB
PEAK BYTE 0
PEAK BYTE 2
The emphasis indication can be used to apply the correct
de-emphasis. In encode SAA2013 will correct the
calculated allocation if 50
⁄15 µs emphasis is applied. When
“CCITT J.17” emphasis is applied, the bit allocation
remains the same as when no emphasis is applied.
MGB364
The 2 bytes of the status are ‘sampled’ at different
moments. So the information may not result from the same
sub-band frame.
Fig.11 Peak level read format; SAA2013 to
microcontroller.
When making repeated status reads (for instance reading
the RTRS/RTRE flags before sending settings or extended
settings), the microcontroller must send an address
before each status read, to ensure that the byte counter in
the interface is reset to logic 0. If this is not done, then the
peak data will be read. Conversely, it is important not to
send a new address after a status read if the peak data is
required.
handbook, halfpage
16
32
15-bit peak
15-bit peak
PEAK READ
channel
indicator
channel
indicator
Peak information is read by clocking a further 4 bytes of
data after a status read. The data format is shown in
Figs 11 and 12. Bits B17 to B31 contain a 15-bit unsigned
peak, LSB first, channel indicated by bit B16. Bits B33 to
B47 contain a 15-bit unsigned peak, channel indicated by
bit B32.
bits 17 to 31
bits 33 to 47
MGB365
Fig.12 Peak level format.
The peak data is delayed by 1 read period. If for example
the microcontroller reads peak level data every 50 ms, the
peak data sourced by SAA2013 will be 50 ms old. Also it
May 1994
14
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
15.625 µs
HALT
L3MODEC
STATUS
BYTES
PEAK 1
PEAK 2
MGB366
Fig.13 Peak data timing.
EXTENDED SETTINGS
This is a single byte transfer, valid during decode and encode. The sequence of operations is:
1. Microcontroller reads status from SAA2013, waiting for the flag RTRE to be set.
2. When RTRE is logic 1, the microcontroller writes address bit 0 is logic 0, bit 1 is logic 0.
3. One byte of extended settings is clocked into the transit register (SAA2013).
4. When it is possible (i.e. subject to RTRC being HIGH, and assuming that allocation or status is not waiting), the byte
is transferred from the transit register to the SAA2003.
L3MODEC
t
t
t
h2
t
cH
cL
d1
L3CLKC
t
t
t
d5
d3
d4
t
t
h1
d2
L3DATAC
(ADAS-SFC)
MGB367
Fig.14 L3 interface timing; SAA2013 to SAA2003 (address mode).
May 1994
15
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
h
L3MODEC
t
t
t
t
h2
d1
cH
cL
L3CLKC
t
t
h1
su1
L3DATAC
SFC-ADAS)
t
t
d3
d4
h3
t
d5
t
t
d2
L3DATAC
(ADAS-SFC)
MGB368
Fig.15 L3 interface timing; SAA2013 to SAA2003 (data mode).
L3MODEM
L3CLKM
t
t
t
cL
t
d1
cH
h2
t
t
h1
su1
L3DATAM
(microcontroller-
ADAS)
MGB369
Fig.16 L3 interface timing; microcontroller to SAA2013 (address mode).
16
May 1994
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
L3MODEM
t
t
t
t
h2
d1
cH
cL
L3CLKCM
t
t
t
su1
h1
L3DATAM
(microcontroller-
ADAS)
t
t
d3
d4
t
d5
t
d2
h3
L3DATAM
(ADAS-
microcontroller)
MGB370
Fig.17 L3 interface timing; microcontroller to SAA2013 (data mode).
t
L
L3MODEM/
L3MODEC
t
t
d1
h2
L3CLKM/
L3CLKC
t
t
d2
d5
L3DATA/
L3DATAC
(OUTPUT)
MGB371
Fig.18 L3 interface timing; microcontroller to SAA2013 and SAA2013 to SAA2003 (halt mode).
17
May 1994
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
T
c24
t
t
cH
cL
CLK24
MGB372
t
t
f
r
Fig.19 Input timing CLK24.
CLK24
t
t
h
su
DATA
MGB373
t , t
r
f
Fig.20 Input signal timing for FSYNC, FRESET, FDIR, FDWS, L3MODEM, L3CLKM, L3DATAM and L3DATAC.
May 1994
18
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
FS256
t
d
t
h
FDAO
MGB374
Fig.21 Output signal timing FDAO.
T
c
t
t
cH
cL
FDCL
t
d4
t
d3
FDAO
(FDAI)
t
t
h1
su1
FDAI,
FDWS
MGB375
Fig.22 Filtered data interface timing.
19
May 1994
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
Current consumption
The typical current consumption is shown in Fig.23.
MBD697
10
handbook, halfpage
I
DD
(mA)
8
6
4
2
0
2
3
4
5
6
V
(V)
DD
Tamb = 25 °C.
Fig.23 Typical current consumption.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS
supply voltage
MIN.
−0.5
MAX.
+6.5
UNIT
VDD
VI
V
V
input voltage
−0.5
−
VDD + 0.5
20
II
input current
mA
V
VO
IO
output voltage
−0.5
−
+6.5
20
output current
mA
°C
°C
Tstg
storage temperature
operating ambient temperature
electrostatic handling
Human Body Model (HBM)
Machine Model (MM)
−65
−40
+150
+85
Tamb
Ves
note 1
note 2
−2000
−200
+2000
+200
V
V
Notes
1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
2. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.
May 1994
20
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
CHARACTERISTICS
V
DD = 2.7 to 5.5 V; VSS = 0 V;Tamb = −40 to 85 °C; unless otherwise specified; IOL and IOH derated by 75% for
DD < 4.5 V.
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
2.7
4
5.0
5
5.5
6
V
IDD
supply current
VDD = 3.0 V
VDD = 5.0 V
VDD = 5.0 V
mA
mA
µA
7
10
−
12
400
Istb
standby current
−
Inputs
VIL
VIH
ILI
LOW level input voltage
HIGH level input voltage
input leakage current
input capacitance
0
−
−
−
−
0.3VDD
VDD
+10
V
0.7VDD
−10
−
V
VI = 0 to VDD
µA
pF
CI
10
Outputs
VOL
LOW level output voltage
HIGH level output voltage
load capacitance
IOL = 4 mA
0
−
−
−
0.4
VDD
30
V
VOH
IOH = −4 mA
V
DD − 0.4
V
CL
−
pF
Inputs/outputs
VIL
VIH
ILI
LOW level input voltage
0
−
−
−
−
−
−
−
0.3VDD
VDD
+10
10
V
HIGH level input voltage
3-state leakage current
input capacitance
0.7VDD
V
VI = 0 to VDD
−10
−
µA
pF
V
CI
VOL
VOH
CL
LOW level output voltage
HIGH level output voltage
load capacitance
IOL = 4 mA
0
0.4
IOH = −4 mA
V
DD − 0.4
VDD
30
V
−
pF
Clock input CLK24
fi
input frequency
see Fig.19
−
−
−
24.576
−
7
7
−
−
MHz
ns
tr
rise time
fall time
−
−
−
−
tf
ns
tcH
tcL
HIGH time
LOW time
10
10
ns
ns
Clock input FS256
fi
input frequency
fs = 48 kHz
fs = 44.1 kHz
fs = 32 kHz
−
12.288
−
−
−
7
7
−
−
MHz
MHz
MHz
ns
−
11.2896
−
8.192
tr
rise time
fall time
−
−
−
−
−
tf
−
ns
tcH
tcL
HIGH time
LOW time
35
35
ns
ns
May 1994
21
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Inputs FSYNC, FRESET, FDIR, FDWS, L3MODEM, L3CLKM, L3DATAM and L3DATAC;
referenced to CLK24 rising edge; see Fig.20; SLEEP = RESET = POR = logic 0
tsu
th
tr
set-up time
hold time
rise time
fall time
15
20
−
−
−
−
−
−
ns
−
ns
ns
ns
200
200
tf
−
Inputs FDAI, FDCL, FDWS, FRESET and FDIR; referenced to FS256 rising edge;
SLEEP = RESET = POR = logic 0
tsu
th
tr
set-up time
hold time
rise time
fall time
15
20
−
−
−
−
−
−
ns
ns
ns
ns
−
200
200
tf
−
Output FDAO; referenced to FS256 rising edge; see Fig.21; SLEEP = RESET = POR = logic 0
th
hold time
CL = 7.5 pF
CL = 30 pF
see Fig.22
0
−
−
−
−
ns
ns
ns
td
delay time
−
30
−
td3
output delay time after FDCL
HIGH
2Tc256 − 10(1)
td4
output delay time after FDCL
HIGH
see Fig.22
−
−
3Tc256 + 60(1) ns
Input FDCL; see Fig.22
(1)
Tc
tcH
tcL
FDCL period
280
4Tc256
−
−
−
ns
ns
ns
FDCL HIGH time
FDCL LOW time
Tc256 + 35(1)
Tc256 + 35(1)
−
−
Inputs FDAI and FDWS; see Fig.22
tsu1
th1
set-up time before FDCL HIGH
hold time after FDCL HIGH
3Tc256 + 60(1)
Tc256 + 20(1)
−
−
−
−
ns
ns
Input FRESET; see Fig.4
tH
FRESET HIGH time
1280
0
−
−
−
ns
ns
tsu
FDIR set-up time before
FRESET LOW
210
(2)
th
FDIR hold time after FRESET
LOW
9Tc24
370
−
ns
SLEEP and RESET timing; see Fig.5; LOWPWR = logic 1
(2)
th
RESET hold time after SLEEP
LOW
5Tc24
210
370
−
−
ns
ns
(2)
td
CLK24 disable after SLEEP
HIGH
9Tc24
May 1994
22
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
L3 interface timing; microcontroller to SAA2013
ADDRESS MODE; SEE FIG.16
td1
L3MODEM LOW to L3CLKM
LOW
190
−
−
ns
tcH
tcL
L3CLKM HIGH time
L3CLKM LOW time
250
250
190
−
−
−
−
−
−
ns
ns
ns
tsu1
L3DATAM input set-up time
before L3CLKM HIGH
th1
th2
L3DATAM input hold time
after L3CLKM HIGH
30
−
−
−
−
ns
ns
L3CLKM HIGH before
L3MODEM HIGH
190
DATA MODE; SEE FIG.17
td1
L3MODEM HIGH to L3CLKM
190
−
−
ns
LOW delay time
tcH
tcL
L3CLKM HIGH time
L3CLKM LOW time
250
250
190
−
−
−
−
−
−
ns
ns
ns
tsu1
L3DATAM input set-up time
before L3CLKM HIGH
th1
th2
td3
th3
td4
L3DATAM input hold time
after L3CLKM HIGH
30
−
−
−
−
−
ns
ns
ns
ns
L3CLKM HIGH before
L3MODEM LOW
190
−
−
L3MODEM HIGH to L3DATAM
output valid
380
−
L3DATAM output hold time
after L3CLKM HIGH
120
L3CLKM HIGH to L3DATAM
output valid delay time
−
−
−
−
360
530
ns
ns
between bits 7
and 8; no halt
mode used
td2
td5
L3MODEM HIGH to L3DATAM
output enabled delay time
0
0
−
−
50
50
ns
ns
L3MODEM LOW to L3DATAM
output disabled delay time
May 1994
23
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
HALT MODE; SEE FIG.18
tL
L3MODEM LOW time
190
190
−
−
−
−
ns
td1
L3MODEM HIGH to L3CLKM
HIGH delay time
ns
ns
ns
ns
th2
td2
td5
L3CLKM HIGH before
L3MODEM LOW
190
0
−
−
−
−
L3MODEM HIGH to L3DATAM
output enabled delay time
50
50
L3MODEM LOW to L3DATAM
output disabled delay time
0
L3 interface timing; SAA2013 to SAA2003
ADDRESS MODE; SEE FIG.14
td1
L3MODEC LOW to L3CLKC
LOW delay time
190
−
−
ns
tcH
tcL
th2
L3CLKC HIGH time
L3CLKC LOW time
210
210
190
−
−
−
−
−
−
ns
ns
ns
L3CLKC HIGH time before
L3MODEC HIGH
td3
th1
td4
td2
td5
L3MODEC LOW to L3DATAC
output valid delay time
−
−
−
−
−
−
380
−
ns
ns
ns
ns
ns
L3DATAC output hold time
after L3CLKC HIGH
120
−
L3CLKC HIGH to L3DATAC
output valid delay time
360
50
L3MODEC LOW to L3DATAC
output enabled delay time
0
L3MODEC HIGH to L3DATAC
output disabled delay time
0
50
May 1994
24
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DATA MODE; SEE FIG.15
td1
L3MODEC HIGH to L3CLKC
190
−
−
ns
LOW
tcH
tcL
L3CLKC HIGH time
L3CLKC LOW time
210
210
100
−
−
−
−
−
−
ns
ns
ns
tsu1
L3DATAC input set-up time
before L3CLKC HIGH
th1
th2
td3
th3
td4
L3DATAC input hold time after
L3CLKC HIGH
30
−
−
−
−
−
ns
ns
ns
ns
L3CLKC HIGH time before
L3MODEC LOW
190
−
−
L3MODEC HIGH to L3DATAC
output valid
380
−
L3DATAC output hold time
after L3CLKC HIGH
120
L3CLKC HIGH to L3DATAC
output valid
−
−
−
−
360
530
ns
ns
between bits 7
and 8; no halt
mode used
HALT MODE; SEE FIG.18
tL
L3MODEC LOW time
190
190
−
−
−
−
ns
ns
td1
L3MODEC HIGH to L3CLKC
HIGH delay time
th2
L3CLKC HIGH time before
L3MODEC LOW
190
−
−
ns
L3 interface delays in bypassed mode; LOWPWR = logic 1
tpd1
propagation delay from
L3MODEM to L3MODEC;
L3DATAM to L3DATAC;
L3CLKM to L3CLKC
−
−
35
ns
tpd2
propagation delay from
L3DATAM to L3DATAC;
L3CLKM to L3CLKC
−20
−20
−
−
+4
+4
ns
ns
tpd3
propagation delay from
L3DATAM to L3DATAC;
L3MODEM to L3MODEC
Notes
1. Tc256 is a clock period of FS256.
2. Tc24 is a clock period of CLK24.
May 1994
25
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
PACKAGE OUTLINE
seating
plane
S
0.1 S
12.9
12.3
1.2
0.8
(4x)
44
34
B
33
1
pin 1 index
0.8
10.1 12.9
9.9
12.3
0.40
0.20
11
23
12
22
1.2
0.8
(4x)
0.40
0.20
0.15 M
A
X
0.8
10.1
9.9
A
0.85
0.75
1.85
1.65
2.10
1.70
0.25
0.14
0.25
0.05
o
0 to 10
0.95
0.55
detail X
MBB944 - 2
Dimensions in mm.
Fig.24 Plastic quad flat-pack, 44-pin (short) (QFP44SL).
26
May 1994
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
SOLDERING
Plastic quad flat-packs
BY WAVE
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
May 1994
27
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N.V.
May 1994
28
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
NOTES
May 1994
29
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
NOTES
May 1994
30
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
NOTES
May 1994
31
Philips Semiconductors – a worldwide company
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United States:INTEGRATED CIRCUITS:
811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. (800)234-7381, Fax. (708)296-8556
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,
P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,
Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300
Uruguay: Coronel Mora 433, MONTEVIDEO,
Tel. (021)5201 122, Fax. (021)5205 189
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BAF-1,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825
Tel. (01)640 000, Fax. (01)640 200
Italy: PHILIPS COMPONENTS S.r.l.,
Viale F. Testi, 327, 20162 MILANO,
Tel. (02)6752.3302, Fax. (02)6752 3300.
Japan: Philips Bldg 13-37, Kohnan2-chome, Minato-ku, TOKYO 108,
SCD31
© Philips Electronics N.V. 1994
Tel. (03)3740 5028, Fax. (03)3740 0580
Korea: (Republic of) Philips House, 260-199 Itaewon-dong,
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,
SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880
Mexico: Philips Components, 5900 Gateway East, Suite 200,
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556
Printed in The Netherlands
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB
Tel. (040)783749, Fax. (040)788399
513061/1500/01/pp32
Date of release: May 1994
9397 731 90011
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. (09)849-4160, Fax. (09)849-7811
Document order number:
Philips Semiconductors
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