SAA2022 [NXP]

Tape formatting and error correction for the DCC system; 磁带格式和纠错的DCC系统
SAA2022
型号: SAA2022
厂家: NXP    NXP
描述:

Tape formatting and error correction for the DCC system
磁带格式和纠错的DCC系统

文件: 总52页 (文件大小:205K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
INTEGRATED CIRCUITS  
DATA SHEET  
SAA2022  
Tape formatting and error  
correction for the DCC system  
February 1994  
Product specification  
Supersedes data of February 1993  
File under Integrated Circuits, Miscellaneous  
Philips Semiconductors  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
FEATURES  
Integrated error correction encoder/decoder function  
with Digital Compact Cassette (DCC) optimized  
algorithms  
Control of capstan servo during recording and after  
recording by microcontroller  
GENERAL DESCRIPTION  
Frequency and phase regulation of capstan servo  
during playback  
Performing the tape formatting and error correction  
functions for DCC applications, the SAA2022 can be used  
in conjunction with the PASC (SAA2002/SAA2012), tape  
equalization (SAA2032), read amplifier (TDA1317 or  
TDA1318) and write amplifier (TDA1316 or TDA1319)  
circuits to implement a full signal processing system.  
Choice of two Dynamic Random Access Memory  
(DRAM) types operating in page mode  
Scratch pad RAM area available to microcontroller in  
system DRAM  
Low power standby mode  
I2S interface  
Microcontroller interface for high-speed transfer burst  
rates up to 170 kbytes per second  
SYSINFO and AUXILIARY data flags on microcontroller  
interface  
Protection against invalid AUXILIARY data  
+4 V operating voltage capability.  
ORDERING INFORMATION  
PACKAGE  
EXTENDED TYPE  
NUMBER  
PINS  
PIN POSITION  
QFP(1)  
MATERIAL  
CODE  
SAA2022GP  
64  
plastic  
SOT208A  
Note  
1. When using reflow soldering it is recommended that the Dry Packing instructions in the “Quality Reference  
Pocketbook” are followed. The pocketbook can be ordered using the code 9398 510 34011.  
February 1994  
2
V
V
V
V
DD1  
DD2  
DD3  
DD4  
5
43  
8
27  
59  
LTCLK  
LTEN  
6
3
LTCNT1  
LTCNT0  
PINI  
4
49  
57  
62  
61  
60  
56  
SBEF  
SBDA  
SBCL  
SBWS  
SBMCLK  
2
29  
28  
LTDATA  
WDATA  
WCLOCK  
33–41  
TCH0 - 7,  
TAUX  
32  
50  
51  
PINO1  
2
SB – I  
S
TAPE INPUT  
BUFFER  
TAPE OUTPUT  
BUFFER  
MICROCONTROLLER  
INTERFACE  
PINO2  
PINO3  
INTERFACE  
ERROR  
CORRECTION  
CODER  
9
SAA2022  
RASN  
CASN  
15  
17–25  
11–14  
A0–8  
D0–3  
CLOCK  
GENERATOR  
DRAM  
INTERFACE  
CONTROL  
10  
16  
WEN  
OEN  
48  
47  
44  
1
64  
63  
30  
31  
52  
55  
RESET  
LTREF  
URDA  
SBDIR  
SPEED  
SPDF  
AZCHK  
MCLK  
PWRDWN  
CLK24  
42  
7
26  
58  
V
V
V
V
SS4  
SS1  
SS2  
SS3  
MEA711 - 2  
Fig.1 Block diagram.  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
PINNING  
SYMBOL  
LTREF  
PIN  
1
DESCRIPTION  
timing reference for microcontroller interface  
LTDATA  
LTCNT1  
LTCNT0  
LTCLK  
LTEN  
VSS2  
2
data for microcontroller interface (3-state; CMOS levels)  
control for microcontroller interface  
control for microcontroller interface  
bit clock for microcontroller interface  
enable for microcontroller interface  
supply ground (0 V)  
3
4
5
6
7
VDD2  
8
supply voltage (+5 V)  
RASN  
WEN  
D3  
9
DRAM row address strobe  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
DRAM write enable  
DRAM data (MSB); 3-state output; TTL compatible input  
DRAM data; 3-state output; TTL compatible input  
DRAM data; 3-state output; TTL compatible input  
DRAM data (LSB); 3-state output; TTL compatible input  
DRAM column address strobe  
DRAM output enable  
D2  
D1  
D0  
CASN  
OEN  
A8  
DRAM address (MSB)  
A7  
DRAM address  
A6  
DRAM address  
A5  
DRAM address  
A4  
DRAM address  
A3  
DRAM address  
A2  
DRAM address  
A1  
DRAM address  
A0  
DRAM address (LSB)  
VSS3  
supply ground (0 V)  
VDD3  
supply voltage (+5 V)  
WCLOCK  
WDATA  
SPEED  
SPDF  
PINO1  
TAUX  
TCH7  
TCH6  
TCH5  
TCH4  
TCH3  
TCH2  
clock for write amplifier transfers  
write amplifier serial data  
capstan phase information  
capstan frequency information  
Port expander output 1  
AUX channel input from SAA2032  
main data channel 7, input from SAA2032  
main data channel 6, input from SAA2032  
main data channel 5, input from SAA2032  
main data channel 4, input from SAA2032  
main data channel 3, input from SAA2032  
main data channel 2, input from SAA2032  
February 1994  
4
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
SYMBOL  
TCH1  
PIN  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
DESCRIPTION  
main data channel 1, input from SAA2032  
TCH0  
VSS1  
main data channel 0, input from SAA2032  
supply ground (0 V)  
VDD1  
supply voltage (+5 V)  
CLK24  
TEST0  
TEST1  
PWRDWN  
RESET  
PINI  
24.576 MHz clock from SAA2002  
test select LSB; do not connect  
test select MSB; do not connect  
sleep mode selection  
reset input with hysteresis and pull-down resistor  
Port expander input  
PINO2  
PINO3  
AZCHK  
TEST2  
TEST3  
MCLK  
SBMCLK  
SBEF  
VSS4  
Port expander output 2  
Port expander output 3  
azimuth check (channels 0 and 7)  
symbol error rate measurement output  
do not connect  
master clock output (6.144 MHz)  
master clock for SB-I2S-interface  
byte error SB-I2S-interface  
supply ground (0 V)  
VDD4  
supply voltage (+5 V)  
SBWS  
SBCL  
SBDA  
SBDIR  
URDA  
word select SB-I2S-interface; 3-state output; CMOS levels  
bit clock SB-I2S-interface; 3-state output; CMOS levels  
data line SB-I2S-interface; 3-state output; CMOS levels  
direction SB-I2S-interface  
unusable data SB-I2S-interface  
February 1994  
5
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
LTREF  
LTDATA  
LTCNT1  
LTCNT0  
LTCLK  
1
2
51 PINO3  
50  
PINO2  
49 PINI  
3
4
48 RESET  
PWRDWN  
5
47  
LTEN  
6
46 TEST1  
45 TEST0  
V
7
SS2  
V
CLK24  
8
44  
43  
42  
DD2  
V
RASN  
WEN  
9
DD1  
V
SAA2022  
10  
11  
12  
13  
SS1  
41 TCH0  
40 TCH1  
39 TCH2  
38 TCH3  
37 TCH4  
36 TCH5  
35 TCH6  
34 TCH7  
33 TAUX  
D3  
D2  
D1  
D0 14  
CASN 15  
OEN 16  
17  
A8  
A7 18  
A6 19  
MEA693 - 2  
Fig.2 Pin configuration (SOT208A).  
February 1994  
6
RECORDING + PLAY BACK  
analog  
input  
ADC  
SAA7360  
stereo filter  
codec  
speed control  
capstan  
drive  
2
TDA1316 or  
TDA1319  
I S  
analog  
output  
DAC  
SAA7323  
SAA2002  
2
write  
read  
I S  
(sub-band)  
heads  
and  
tape  
digital input  
DAIO  
SAA2012  
SAA2022  
SAA2032  
TDA1315  
digital output  
adaptive  
allocation and  
scale factors  
digital  
equalizer  
TDA1317 or  
TDA1318  
RAM  
256 kbits  
AUDIO INPUT/OUTPUT  
PASC PROCESSING  
TAPE DRIVE PROCESSING  
MEA695 - 2  
MICROCONTROLLER  
Fig.3 DCC data flow diagram.  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
The SAA2022 provides the following functions:  
PWRDWN  
This pin is an active HIGH signal which places the  
SAA2022 in a “SLEEP” mode. When the SAA2022 is in  
“SLEEP” mode and the CLK24 is either held HIGH or held  
LOW, there is no activity in the device, thus resulting in  
no EMI and a low power dissipation (typically <10% of  
operational dissipation). This pin should be connected to  
the DCC power-down signal, which can be driven by the  
system microcontroller.  
In Playback Modes  
Tape channel data and clock recovery  
10 to 8 demodulation  
Data placement in DRAM  
C1 and C2 error correction decoding  
I2S-interfacing to SB-I2S-bus  
To enter the “SLEEP” mode the SAA2022 should reset  
and hold reset. After a delay of at least 15 µs the  
PWRDWN pin should be brought HIGH after which the  
state of the reset pin is “don’t care”. The power dissipation  
is reduced further when the CLK24 input signal stops.  
Interfacing to microcontroller for SYSINFO and  
AUX data  
Capstan control for tape deck.  
In Record Modes  
When recovering from “SLEEP” mode the PWRDWN pin  
should be driven LOW and the chip reset with a pulse of at  
least 15 µs duration.  
I2S-interfacing to SB-I2S-bus  
C1 and C2 error correction encoding  
Formatting for tape transfer  
8 to 10 modulation  
CLK24  
This is the 24.576 MHz clock input and should be  
connected directly to the SAA2002 CLK24 pin.  
Interfacing to microcontroller for SYSINFO and  
AUX data  
Connections to SAA2032  
Capstan control for tape deck, programmable by  
microcontroller.  
TCH0 TO TCH7 AND TAUX  
These lines are the equalized and clipped (to VDD) tape  
channel inputs and should be connected to the SAA2032  
pins TCH0 to TCH7 and TAUX.  
Operational Modes  
The 3 basic modes of operation are:  
DPAP - Main data (audio) and SYSINFO play, AUX play  
Sub-band I2S-bus Connections  
The timing for the SB-I2S-interface is given in Figs 4 to 9.  
DRAR - Main data (audio) and SYSINFO record,  
AUX record  
DPAR - Main data (audio) and SYSINFO play,  
AUX record.  
Hardware Interfacing  
RESET  
This is an active HIGH input signal which resets the  
SAA2022 and brings it into its default mode, DPAP. This  
should be connected to the system reset, which can be  
driven by the microcontroller. The duration of the reset  
pulse should be at least 15 µs. This pin has an internal  
pull-down resistor of between 20 kand 125 k.  
February 1994  
8
lines show rising edge of SBMCLK  
SBMCLK  
SBCL  
SBWS  
SBDA  
bit number  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
byte number  
0
1
SBEF  
byte number  
0
1
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
2
3
MEA697 - 1  
2
3
Fig.4 SB-I2S-interface in playback master mode (1).  
t
H-1  
SBMCLK  
(INPUT)  
t
t
L-1  
dSR  
SBCL  
(OUTPUT)  
t
dSR  
SBWS  
(OUTPUT)  
SBEF  
(OUTPUT)  
t
t
suMR  
suMR  
MCLK  
(OUTPUT)  
t
dMR  
SBDA  
(OUTPUT)  
SBEF  
(OUTPUT)  
MEA696  
Fig.5 SB-I2S-interface in playback master mode (2).  
SBCL  
SBWS  
SBDA  
bit number  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
byte number  
0
1
SBEF  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
2
3
MEA699 - 1  
Fig.6 SB-I2S-interface in playback slave mode (1).  
MCLK  
t
t
hMR  
hMR  
t
t
suMR  
suMR  
SBCL  
(INPUT)  
SBWS  
(INPUT)  
SBEF  
(OUTPUT)  
t
dMR  
SBDA  
(OUTPUT)  
MEA698  
Fig.7 SB-I2S-interface in playback slave mode (2).  
SBCL  
SBWS  
SBDA  
bit number  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
byte number  
0
1
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
MSA536  
2
3
Fig.8 SB-I2S-interface in record mode (1).  
MCLK  
(OUTPUT)  
t
suMR  
SBCL  
(INPUT)  
t
hMR  
SBWS  
(INPUT)  
SBDA  
(INPUT)  
MEA700  
Fig.9 SB-I2S-interface in record mode (2).  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
SBMCLK  
SBDA  
This is the sub-band master clock input for the  
SB-I2S-interface. The frequency of this signal is nominally  
6.144 MHz. This pin should be connected to the SBMCLK  
pin of the SAA2002.  
This input/output pin is the serial data line for the  
SB-I2S-interface to the SAA2002.  
SBEF  
This active HIGH output pin is the error per byte line for the  
SB-I2S-interface to the SAA2002.  
SBDIR  
This output pin is the sub-band I2S-bus direction signal, it  
indicates the direction of transfer on the SB-I2S-bus.  
A logic 1 indicates a SAA2022 to SAA2002 transfer  
(audio play) whilst a logic 0 is output for a SAA2002 to  
SAA2022 transfer (audio record). This pin connects  
directly to the SBDIR pin on the SAA2002.  
URDA  
This active HIGH output pin indicates that the main data  
(audio), the SYSINFO and the AUXILIARY data are not  
usable, regardless of the state of the corresponding  
reliability flags. The state of this pin is reflected in the  
URDA bit of STATUS byte 0, which can be read by the  
microcontroller. This pin should be connected directly to  
the URDA pin of the SAA2002. URDA is activated as a  
result of a reset, a mode change from DRAR to DPAP, or  
if the SAA2022 has had to resynchronize with the incoming  
data from tape.  
SBCL  
This input/output pin is the bit clock line for the  
SB-I2S-interface to the SAA2002. Is has a nominal  
frequency of 768 kHz.  
SBWS  
The position of the first SB-I2S-bytes in a tape frame is  
shown in Fig.10.  
This input/output pin is the word select line for the  
SB-I2S-interface to the SAA2002. It has a nominal  
frequency of 12 kHz.  
February 1994  
15  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
MODE DPAP OR DPAR  
1
0
SNUM  
LTREF  
SBWS  
SBDA  
BYTE number 2  
BYTE number 1  
BYTE number  
8191  
BYTE number 0  
OF PREVIOUS  
TAPE FRAME  
MODE DRAR  
0
SNUM  
3
LTREF  
SBWS  
SBDA  
BYTE number 2  
MEA701 - 2  
BYTE number 8191  
BYTE number 1  
BYTE number 0  
OF PREVIOUS  
TAPE FRAME  
Fig.10 Position of first SB-I2S-bytes in tape frame.  
February 1994  
16  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
MCLK  
RASN  
CASN  
D0...D3  
#0  
#1  
#2  
A0...A7 (A8)  
ROW  
COLUMN #0  
COLUMN #1  
COLUMN #2  
OEN  
WEN  
1 read cycle = 651 ns  
MEA702  
Fig.11 DRAM timing read cycle.  
OEN  
DRAM Interface  
The SAA2022 has been designed to operate with  
64 k × 4-bit or 256 k × 4-bit DRAMs operating in page  
mode, with an access time of 80 to 100 ns. The timing for  
read, write and refresh cycles is shown in Figs 11 to 13.  
This pin provides the output enable (active LOW) for the  
DRAM, it connects directly to the output enable pin of the  
DRAM.  
WEN  
CASN  
This output pin provides the write enable (active LOW) for  
the DRAM, it connects directly to the write enable pin of the  
DRAM.  
This output pin is the column address strobe (active LOW)  
for the DRAM, it connects directly to the column address  
strobe pin of the DRAM.  
A0 TO A8  
RASN  
These output pins are the multiplexed column and row  
address lines for the DRAM. When the 64 k × 4-bit DRAM  
is used, pins A0 to A7 should be connected to the DRAM  
address input pins, and pin A8 should be left unconnected.  
When using the 256 k × 4-bit DRAM then address pins  
A0 to A8 should be connected to the address input pins of  
the DRAM.  
This output pin is the row address strobe (active LOW) for  
the DRAM, it connects directly to the row address strobe  
pin of the DRAM.  
February 1994  
17  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
MCLK  
RASN  
CASN  
D0...D3  
#0  
#1  
#2  
A0...A7 (A8)  
ROW  
COLUMN #0  
COLUMN #1  
COLUMN #2  
OEN  
WEN  
MEA703  
1 write cycle = 651 ns  
Fig.12 DRAM write cycle.  
WDATA  
D0 TO D3  
These input/output pins are the data lines for the DRAM,  
they should be connected directly to the DRAM data I/O  
pins.  
This output pin is the multiplexed data and control line for  
the WRITE AMPLIFIER (timing information is shown in  
Fig.14). The WDATA pin should be connected directly to  
the WDATA pin of the WRITE AMPLIFIER.  
Write amplifier interface  
The SAA2022 may be used with either the TDA1316 or  
TDA1319 write amplifiers.  
WCLOCK  
This output pin provides the 3.072 MHz clock output for the  
WRITE AMPLIFIER, it should be connected directly to the  
WCLOCK pin of the WRITE AMPLIFIER.  
February 1994  
18  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
MCLK  
RASN  
CASN  
D0...D3  
A0...A7 (A8)  
ROW  
OEN  
WEN  
1 refresh cycle = 651 ns  
MEA704 - 1  
Fig.13 DRAM refresh cycle.  
SPDF signal is 5.2 µs. The duty cycle of SPDF can vary  
from 0% at +6.5% deviation to 100% at 6.5% deviation. If  
the deviation = 0% then the duty cycle of SPDF is 50%.  
Tape deck capstan control interface  
SPEED  
This signal is a pulse width modulated output that may be  
used to control the tape deck capstan. The period of the  
SPEED signal is 41.66 µs and the nominal duty cycle is  
50%.  
Microcontroller Interface  
LTREF  
The SAA2022 divides time into segments of 42.67 ms  
nominal duration which are counted in modulo 4. The  
LTREF active LOW output pin can be connected directly to  
the interrupt input of the microcontroller and indicates the  
start of a time segment. It goes LOW for 5.2 µs once every  
42.66 ms and can be used for generating interrupts. Note  
if a resync occurs then the time between the occurrences  
of LTREF can vary. The function and programming of the  
other interface lines LTCNT0, LTCNT1, LTEN, LTCLK and  
LTDATA are described in the pinning and programming  
sections.  
There are 4 modes of operation for the SPEED signal  
which can be selected by the programmed settings of  
µCSPD (microcontroller capstan speed), ENFREG  
(enable frequency regulation) and ENEFREG (enable  
extended frequency regulation) flags.  
SPDF  
If µCSPD = logic 0 this pin outputs a pulse width  
modulated measurement of the main data channel bit  
rates and may be used in combination with the SPEED  
signal to control the tape deck capstan. The period of the  
February 1994  
19  
WCLOCK  
WDATA  
SYNC  
SYNC  
TDATPLB TAUXPLB TERAUX  
TCH0  
TCH1  
TCH2  
TCH3  
TCH4  
TCH5  
TCH6  
TCHAUX  
TCH7  
TDATPLB  
MLA643  
Fig.14 WDATA and WCLOCK timing.  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
Duration of the one tape block  
5.3 ms  
h
AZCHK  
(8 periods MCLK)  
1.3 µs  
MEA705  
This is a measure of the azimuth error.  
Fig.15 AZCHK timing.  
PINO2  
Test Pins  
This output pin is connected directly to the PINO2 bit of the  
SETTINGS byte 1 register and can be set or reset by the  
microcontroller.  
TEST0, TEST1, TEST2 AND TEST 3  
These input pins are for test use only and for normal  
operation should not be connected.  
PINO3  
AZCHK  
This output pin is connected directly to the PINO3 bit of the  
SETTINGS byte 1 register and can be set or reset by the  
microcontroller.  
This output pin indicates the occurrence of a tape channel  
sync symbol on tape channels TCH0 and TCH7. The  
separation between the pulses for the TCH0 and TCH7  
channels gives a measure of the azimuth error between  
the tape and head alignment (see Fig.15).  
Power Supply Pins  
VDD1 TO VDD4  
Port Expansion Pins  
These are the +5 V power supply pins which must all be  
connected. Decoupling of VSS1 to VSS4 is recommended.  
PINI  
VSS1 TO VSS4  
This input pin is connected directly to the PINI bit in the  
STATUS byte 1, it can be read by the microcontroller, and  
may be used for any CMOS level compatible input signals.  
These are the +5 V power supply ground pins, all of which  
must be connected.  
PINO1  
This output pin is connected directly to the PINO1 bit of the  
SETTINGS byte 1 register and can be set or reset by the  
microcontroller.  
February 1994  
21  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
Programming the SAA2022 via the Microcontroller Interface  
Table 1 SAA2022 interface connections to the microcontroller.  
PIN  
INPUT/OUTPUT  
DESCRIPTION  
LTEN  
I
I
enable active HIGH  
clock signal  
LTCLK  
LTCNT0  
LTCNT1  
LTDATA  
LTREF  
I
control LSB  
I
control MSB  
I/O  
O
bi-directional data  
timing reference 5 µs at start of every segment active LOW  
All transfers are in units of 8-bits, registers with less than 8-bits are LSB justified, unless otherwise specified. The four  
basic types of transfer are shown in Table 2.  
Table 2 Types of transfer.  
LTCNT1  
LTCNT0  
TRANSFER  
WDAT  
EXPLANATION  
write DATA to SAA2022  
0
0
1
1
0
1
0
1
RDAT  
read DATA from SAA2022  
write Command to SAA2022  
read Status from SAA2022  
WCMD  
RSTAT  
Microcontroller Interface Registers  
The SAA2022 microcontroller interface has 7 write and 4 read registers, as shown in Table 3.  
Table 3 SAA2022 Microcontroller Interface Registers.  
REGISTER  
SET0  
READ/WRITE  
WRITE  
WRITE  
WRITE  
WRITE  
WRITE  
WRITE  
WRITE  
READ  
NO. OF BITS  
COMMENTS  
7
8
6
8
7
8
4
8
7
8
8
primary settings  
SET1  
secondary settings  
CMD  
microcontroller command  
byte counter  
BYTCNT  
RACCNT  
SPDDTY  
AFLEV  
random access counter  
duty cycle for SPEED  
AUXILIARY flag level  
primary status  
STATUS0  
STATUS1  
STATUS2  
STATUS3  
READ  
secondary status  
READ  
SYSINFO/AUX flags  
channel status flags  
READ  
February 1994  
22  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
Direct Access  
Indirect Access  
Only one write (CMD) and four read  
To write to or read from the indirect access registers, a  
command must first be sent to the command register. The  
transfer of bytes can then occur using WDAT and RDAT  
type transfers. It is the responsibility of the microcontroller  
to ensure that the transfer type and the last command are  
compatible. The same type of transfer can continue until a  
new command is sent.  
(STATUS0 to STATUS3) registers can be directly  
accessed using the LTCNT lines, all other registers must  
be accessed by first programming the command register.  
The four Status registers can be read by performing  
4 RSTAT transfers within the same LTEN = HIGH period.  
Typical transfers on the microcontroller interface are  
shown in Figs 16 to 19.  
transfer of byte from microcontroller (a)  
t
LE  
LTEN  
t
t
t
h2  
su1  
h1  
LTCNT0,1  
LTCLK  
t
t
t
Lc  
su4  
su2  
t
t
t
Hc  
su3  
h3  
0
1
2
3
4
5
6
7
LTDATA  
transfer of byte to microcontroller (b)  
t
LE  
LTEN  
t
t
t
t
h2  
su1  
t
h1  
LTCNT0,1  
LTCLK  
t
t
su4  
su2  
Lc  
t
t
t
t
h6  
d1  
d2  
h5  
Hc  
1
2
3
4
5
6
7
LTDATA  
0
MEA715 - 1  
Fig.16 LT interface timing (1).  
February 1994  
23  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
Notes to Fig.16a.  
DESCRIPTION  
TIMING  
For the timing figures it is assumed that cycle time Tcy of MCLK is within the limits 160 ns < Tcy < 165 ns  
The set-up time tsu of LTEN, LTCNT, LTCLK and LTDATA to MCLK HIGH  
The hold time th of LTEN, LTCNT, LTCLK and LTDATA to MCLK HIGH  
LTEN LOW time before start data transfer  
LTCLK LOW time  
tsu < 40 ns  
th = 0 ns  
tLE > 535 ns; note 1  
tLc > 205 ns  
tHc > 205 ns  
LTCLK HIGH time  
LTCNT0/1 set-up time to LTEN HIGH  
LTCNT0/1 hold time to LTEN HIGH  
LTEN set-up time to LTCLK LOW  
tsu1 > 205 ns  
th1 > 205 ns  
tsu2 > 0 ns  
LTEN hold time to LTCLK HIGH  
th2 > 205 ns  
tsu3 > 205 ns  
th3 > 40 ns  
tsu4 > 535 ns  
LTDATA set-up time to LTCLK HIGH  
LTDATA hold time to LTCLK HIGH  
LTCLK set-up time to LTEN HIGH  
Note  
1. See interface timing (Fig.16b) for the transfer of a byte to the microcontroller.  
February 1994  
24  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
Notes to Fig.16b.  
DESCRIPTION  
TIMING  
For the timing figures it is assumed that cycle time Tcy of MCLK is within the limits 160 ns < Tcy < 165 ns  
The set-up time tsu of LTEN, LTCNT, LTCLK and LTDATA to MCLK HIGH  
The hold time th of LTEN, LTCNT, LTCLK and LTDATA to MCLK HIGH  
The delay time td of LTDATA from MCLK HIGH is within the limits  
The delay time td of LTEN to the 3-state control of LTDATA  
LTEN LOW time before start data transfer  
LTCLK LOW time  
tsu < 40 ns  
th = 0 ns  
0 ns < td < 30 ns  
0 ns < td < 50 ns  
tLE > 535 ns; note 1  
t
Lc > 205 ns  
LTCLK HIGH time  
tHc > 205 ns  
tsu1 > 205 ns  
th1 > 205 ns  
tsu2 > 0 ns  
LTCNT0/1 set-up time to LTEN HIGH  
LTCNT0/1 hold time from LTEN HIGH  
LTEN set-up time to LTCLK LOW  
LTEN hold time from LTCLK HIGH  
th2 > 205 ns  
tsu4 > 535 ns  
th5 > 160 ns  
LTCLK set-up time to LTEN HIGH  
LTCLK hold time from LTEN LOW  
LTDATA hold time from LTEN LOW  
th6 > 0 ns  
LTDATA delay time from LTEN HIGH  
td1 < 235 ns  
td2 < 400 ns  
td4 < 50 ns  
LTDATA delay time from LTCLK HIGH  
LTDATA delay time from LTEN (3-state control)  
Note  
1. tLE is determined by the longest path from LTEN LOW to LTDATA. This path is via the reset of the internal bit counter.  
This reset is only necessary when after the last LTEN = LOW, an exact multiple of 8-bits has not been transferred.  
Otherwise tLE can be Tcy = 165 ns less.  
February 1994  
25  
transfer of 3 status bytes to microcontroller  
LTEN  
3HEX  
LTCNT0,1  
LTCLK  
t
t
d3  
d3  
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
LTDATA  
status byte 0  
status byte 1  
status byte 2  
transfer of 2 SYSINFO bytes to microcontroller (in fast transfer period)  
LTEN  
2HEX  
1HEX  
LTCNT0,1  
LTCLK  
t
t
ds2  
ds1  
0
1
1
0
2
0
3
1
4
0
5
0
6
0
7
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
LTDATA  
command RDSYS  
first SYSINFO byte  
second SYSINFO byte  
transfer of 2 SYSINFO bytes from microcontroller (in fast transfer period)  
LTEN  
LTCNT0,1  
2HEX  
0HEX  
LTCLK  
t
t
dr1  
dr2  
3
0
1
1
1
2
0
3
1
4
0
5
0
6
0
7
0
7
0
7
LTDATA  
0
1
2
3
4
5
6
1
2
4
5
6
MEA712 - 1  
command WRSYS  
first SYSINFO byte  
second SYSINFO byte  
Fig.17 LT interface timing (2).  
transfer of two SYSINFO bytes starting at byte # 8 to microcontroller (in fast transfer period)  
LTEN  
2HEX  
0HEX  
2HEX  
LTCNT0,1  
LTCLK  
1HEX  
1HEX  
LTDATA  
Idbyte  
08hex  
rdsys  
sysinfo (8)  
sysinfo (9)  
transfer of two SYSINFO bytes starting at byte # 8 from microcontroller to SAA2022 (in fast transfer period)  
LTEN  
LTCNT0,1  
LTCLK  
2HEX  
2HEX  
0HEX  
0HEX  
0HEX  
LTDATA  
MEA714  
Idbyte  
08hex  
wrsys  
sysinfo (8)  
sysinfo (9)  
Fig.18 LT interface timing (3).  
transfer of two scratch pad RAM bytes (SPR) starting at SPR page 3, column 5, row 23 to microcomputer  
(in fast transfer period)  
LTEN  
LTCNT0,1  
LTCLK  
2HEX  
0HEX  
2HEX  
0HEX  
2HEX  
1HEX  
1HEX  
LTDATA  
L
Idbyte  
97hex  
38hex  
rddrac  
spr (3,5,23)  
spr (3,5,24)  
draccnt  
transfer of two scratch pad RAM bytes (SPR) starting at SPR page 3, column 5, row 23 from microcontroller to SAA2022  
(in fast transfer period)  
LTEN  
LTCNT0,1  
LTCLK  
2HEX  
0HEX  
2HEX  
0HEX  
2HEX  
0HEX  
0HEX  
LTDATA  
MEA713  
L
Idbyte  
97hex  
draccnt  
38hex  
wrdrac  
spr (3,5,23)  
spr (3,5,24)  
Fig.19 LT interface timing (4).  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
MEA717  
100 %  
91 %  
duty  
factor  
speed  
50 %  
9 %  
0
0
+ 2 blocks  
+ 10.6 ms  
+ 1.65 blocks  
+ 8.8 ms  
– 1.65 blocks  
– 8.8 ms  
– 2 blocks  
– 10.6 ms  
Fig.20 SPEED pulse width as a function of phase error.  
SNUM  
0
1
1
2
3
3
0
0
1
1
2
2
3
3
0
0
1
1
2
2
3
3
0
0
1
1
2
2
3
3
0
0
1
1
2
2
3
3
0
0
1
1
2
2
3
3
0
AUXBLK  
2
AUX CHN  
RECLAB  
SYSBLK  
0
1
2
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
2
0
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
DATA CHN  
MEA706  
Fig.21 Recording a label.  
29  
February 1994  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
Table 4 Microcontroller Interface Commands.  
CMD  
REGISTER  
76543210  
COMMAND  
EXPLANATION  
XXXX1000  
XXXX1001  
XXXX1010  
XXXX1011  
XXXX0000  
XXXX0001  
XXXX0010  
XXXX0011  
XXXX0101  
XXXX0110  
XXYZ1100  
XXYZ1101  
XXYZ1110  
XXYZ1111  
RDAUX  
RDSYS  
read AUXILIARY INFO  
read SYSINFO  
WRAUX  
write AUXILIARY INFO  
write SYSINFO  
WRSYS  
LDSET0  
load new settings register 0  
load new settings register 1  
load AUX flag threshold level  
load record speed duty cycle  
load byte counter  
LDSET1  
LDAFLEV  
LDSPDDTY  
LDBYTCNT  
LDRACCNT  
RDDRAC  
RDFDRAC  
WRDRAC  
WRFDRAC  
load random access counter  
read data in random access mode from RAM quarter YZ  
read flag and data in random access mode from RAM quarter YZ  
write data in random access mode to RAM quarter YZ  
write flag and data in random access mode to RAM quarter YZ  
Explanation of settings  
SET0 REGISTER (TABLE 6)  
µCSPD  
ENEFREG  
Enable Extended Frequency Regulation active HIGH,  
allows extended frequency information from the data  
channels to be used with the “normal” frequency  
information and the phase information to generate the  
capstan SPEED signal, if ENFREG is active.  
An active HIGH, selects microprocessor control for the  
SPEED pulse width modulated servo control signal.  
SET1 REGISTER (TABLE 7)  
TEST1  
DISRSY  
Disable Resyncs active HIGH, is used in after recording.  
RECLAB  
This setting is for test only. For use in applications this bit  
should be always programmed to logic 0.  
Record labels active HIGH when in DRAR or DPAR  
modes; a label being defined as the bodies of all four AUX  
tape blocks in a tape frame which is being written.  
This setting has immediate effect and should only be  
modified in time segment 1.  
PINO1  
Pin Output 1, Port expander output for the microcontroller.  
TFEMAS  
This allows the SAA2022 to become master of the  
SB-I2S-bus in modes DPAP and DPAR. In mode DRAR  
the device always operates as a slave irrespective of the  
settings bit.  
ENFREG  
In modes DPAP and DPAR Enable Frequency Regulation  
active HIGH, allows frequency information from the data  
channels to be used with the phase information to  
generate the capstan SPEED signal.  
February 1994  
30  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
PORTAB  
EXTENDED TAPE FREQUENCY MODE  
Portable application active HIGH, allows for the data  
channels clock extraction to track fast variations in tape bit  
rate. For home use set to inactive.  
ENFREG = logic 1, ENEFREG = logic 1 and  
µCSPD = logic 0  
In this mode there are 3 regions. This provides a more  
gentle transition from frequency plus phase control to  
phase only control. Firstly from 0% to ±4.5% deviation,  
where the operation is as for the tape phase mode.  
Secondly from ±4.5% to ±6% deviation where the  
contribution of the frequency information to the servo  
information is half of that in the region beyond ±6%  
deviation. Thirdly when the deviation is greater than ±6%,  
which is the same as for the tape frequency mode.  
NOCOS  
No Corrected Output Symbol active HIGH, disables the  
writing of the error corrected output to the DRAM. It is only  
used for debugging.  
TEST2  
This setting is for test only. For use in applications this bit  
should always be programmed to logic 0.  
MICROCONTROLLER MODE  
PINO2  
µCSPD = logic 1  
Pin output 2, Port expander output for the microcontroller.  
In this mode the pulse width is determined by the  
microcontroller programming of the SPDDTY interface  
register.  
PINO3  
Pin output 3, Port expander output for the microcontroller.  
TAPE PHASE MODE  
NMODE0, NMODE1  
These two bits control the mode change operation in the  
SAA2022.  
ENFREG = logic 0, ENEFREG = logic 0 and  
µCSPD = logic 0  
Table 5 NMODE1, NMODE0.  
In this mode the SAA2022 performs a new calculation to  
determine the pulse width for the SPEED signal  
NMODE1  
NMODE0  
OPERATING MODE  
DPAP  
approximately once every 21.33 ms, giving a sampling  
rate of approximately 46.9 Hz. This calculation is basically  
a phase comparison between the incoming main data tape  
frame and an internally generated reference. The pulse  
duty cycle increases linearly from approximately 9% when  
the incoming main data tape frame is 1.65 tape blocks  
(8.8 ms) too early up to 91% when the incoming main data  
tape frame is 1.65 tape blocks (8.8 ms) too late, in 256  
steps (see Fig.20). Outside ±2 tape blocks range the pulse  
width characteristic overflows and repeats itself forming a  
saw-tooth pattern. The SAA2022 has an internal buffer of  
±8.8 ms inside which the phase information is valid.  
0
1
1
0
0
0
1
1
DPAR  
DRAR  
invalid state  
TAPE FREQUENCY MODE  
ENFREG = logic 1, ENEFREG = logic 0 and  
µCSPD = logic 0  
The above description is overridden with frequency  
information. That is if the incoming main data bit rate  
deviates by more than approximately ±6% from the  
nominal bit rate of 96000 bits per second, frequency  
information is mixed with the phase information. In  
between the limits ±6% the pulse width is determined as  
above.  
February 1994  
31  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
SETTINGS REGISTERS  
Table 8 SPEED Source.  
Table 6 SET0.  
MODE  
DPAP  
µCSPD  
SPEED  
tape(1)  
µC(2)  
SETTING  
ENEFREG  
BIT  
6
DEFAULT  
0
1
0
1
0
1
0
0
0
0
0
0
0
DPAP  
ENFREG  
RECLAB  
DISRSY  
µCSPD  
5
DPAR  
tape(1)  
µC(2)  
4
DPAR  
3
DRAR  
50%(3)  
µC(2)  
2
DRAR  
NMODE1  
NMODE0  
1
Notes  
0
1. “Tape” means that the duty cycle has been calculated  
from the playback tape signal.  
Table 7 SET1.  
2. “µC” means that the microcontroller programs the  
duty cycle via the SPDDTY register in the  
microcontroller interface.  
SETTING  
PINO3  
BIT  
7
DEFAULT  
0
0
0
0
1
1
0
0
3. “50%” defines that the duty cycle is fixed at 50%.  
PINO2  
6
TEST2  
5
NOCOS  
PORTAB  
TFEMAS  
PINO1  
4
3
2
1
TEST1  
0
Table 9 Typical Settings.  
SETTING BYTE  
0
1
WHEN  
7
X
X
X
X
X
X
6
1
5
1
4
0
0
0
1
0
1
3
0
0
X
X
1
1
2
0
0
0
0
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
0
7
0
0
0
0
0
0
6
0
0
0
0
0
0
5
0
0
0
0
0
0
4
0
0
0
0
0
0
3
0
1
0
0
0
0
2
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
play home machine  
play portable machine  
record NO LABEL  
record LABEL  
1
1
X
X
X
X
X
X
X
X
after record NO LABEL  
after record LABEL  
February 1994  
32  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
STATUS REGISTERS  
The SAA2022 has 4 status registers all of which are read only. A circular pointer is used to select which of the status  
registers is addressed. This pointer is reset to point to STATUS0 as result of the rising edge of LTEN while the LTCNT0/  
1 = RSTAT. Any number of the registers may be read, always starting at STATUS0.  
Table 10 STATUS0.  
STATUS BIT  
Table 12 STATUS2.  
STATUS BIT  
BIT  
7
BIT  
7
RFBT  
NFLG3  
NFLG2  
NFLG1  
NFLG0  
FLG3  
SYSFLC  
AUXFLC  
AUXFLO  
FLAGI  
6
6
5
5
4
4
3
3
URDA  
2
FLG2  
2
SNUM1  
SNUM0  
1
FLG1  
1
0
FLG0  
0
Table 11 STATUS1.  
Table 13 STATUS3.  
STATUS BIT  
BIT  
7
STATUS BIT  
BIT  
7
SLOWTFR  
TEST4  
CHANS7  
CHANS6  
CHANS5  
CHANS4  
CHANS3  
CHANS2  
CHANS1  
CHANS0  
6
6
5
5
PINI  
4
4
PAG2  
PAG1  
MODE1  
MODE0  
3
3
2
2
1
1
0
0
February 1994  
33  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
SNUM0, SNUM1  
Time segment number.  
URDA  
PINI  
Pin input, Port expander input for the microcontroller.  
TEST4  
Unreliable Data active HIGH, means that regardless of the  
other flag information you cannot use the Data,  
SYSINFO or AUX, because they are unreliable, this can  
occur as result of a RESYNC, a mode change from mode  
DRAR to mode DPAP, or a reset of the SAA2022. When a  
resync occurs it resynchronizes with the incoming main  
data tape channel information, with a result that for a  
period of time, the time that URDA is HIGH all output data  
is unusable.  
This is for test purposes only.  
SLOWTFR  
Indicates that LT data transfers of SYSINFO, AUX or  
Scratch Pad RAM can only occur at low speed rate. This  
occurs only during the second half of time segment 0,  
therefore the status bit RFBT must be polled to see if a  
transfer is possible. This bit will be HIGH only during the  
second half of time segment 0.  
FLAGI  
FLG 0 to 3  
Instantaneous flag active HIGH, indicates that the  
AUXILIARY byte that is about to be transferred to the  
microcontroller has a flag that is AFLEV, or that the  
SYSINFO byte that is about to be transferred is in error.  
Error flag from the next AUXILIARY/SYSINFO byte which  
is to be transferred to the microcontroller.  
The flags for SYSINFO bytes have only 2 values, logic 0  
which implies that the error corrector finds the bytes are  
good and logic 1 which implies that the bytes are in error.  
AUXFLO  
The flags for AUXINFO bytes can have any one of 16  
values, 0 to 15, depending on the type of correction. All of  
the AUX bytes in the same AUX code word will have the  
same flag value. The less reliable the data, the higher the  
flag value. It is recommended that any byte with a flag  
value of 10 or higher is deemed unreliable.  
Old Aux Flag active HIGH, indicates that AUXILIARY data  
due to be transferred to the microcontroller in the current  
segment should not be used.  
AUXFLC  
AUX Flag active HIGH, indicates that at least one of the  
AUXILIARY data bytes due to be transferred to the  
microcontroller in the current segment is in error. This  
information is provided before the transfer occurs.  
NFLG 0 to 3  
Error flag from the byte after the next AUXILIARY/  
SYSINFO byte which will be transferred to the  
microcontroller.  
SYSFLC  
SYSINFO flag active HIGH, indicates that at least one of  
the SYSINFO bytes in the current segment is in error. This  
information is provided before the transfer occurs.  
CHANS 0 to 7  
Error Correction Channel status, which indicates if the  
even C1 code words in the 5th block of the segment for  
each data tape channel were non correctable. Therefore 1  
in every 16 C1 code words from each channel is monitored  
to see if the C1 error correcting decoding was successful.  
RFBT  
Ready for byte transfer of SYSINFO, AUX or Scratch pad  
RAM to or from the microcontroller active HIGH.  
MODE0, MODE1  
Current mode of operation of the SAA2022.  
PAG1, PAG2  
Two most significant bits of the modulo 6 internal page  
counter, the least significant bit is equal to SNUM0.  
February 1994  
34  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
Loadable registers  
Table 14 AFLev.  
3
2
1
0
BIT  
1
0
1
0
default value  
AUX Flag threshold level. FLAGI goes HIGH for the AUX bytes whose flags are AFLev. AUXFLC will go HIGH if the  
flags from either code word in the current segment are AFLev. The default value is 10.  
Table 15 SPDDTY.  
7
6
5
4
3
2
1
0
BIT  
1
0
0
0
0
0
0
0
default value  
SPEED duty cycle register. If µCSPD is active, this register determines the duty cycle of the speed signal.  
The duty cycle is given by:  
SPDDTY × 100  
Duty cycle = ------------------------------------------ %  
256  
0 for 0% duty cycle  
128 for 50% duty cycle  
255 for 99.6% duty cycle.  
The default value is 128.  
Table 16 BYTCNT.  
7
6
5
4
3
2
1
0
BIT  
0
0
0
0
0
0
0
0
default value  
Byte counter for SYSINFO, AUX and Scratch Pad RAM  
transfers. For SYSINFO:  
values 0 to 31 access SYSINFO from the current segment.  
values 32 to 63 access SYSINFO from the current +1 segment.  
values 64 to 95 access SYSINFO from the current +2 segments.  
values 96 to 127 access SYSINFO from the current +3 segments.  
In Random access mode the SYSTEM ADDRESS is mapped on to BYTCNT as follows:  
Table 17 SYSTEM ADDRES in Random access mode.  
7
6
5
4
3
2
1
0
BYTCNT  
7
6
5
4
3
2
1
0
ROW  
Table 18 RAACNT.  
6
5
4
3
2
1
0
BIT  
0
0
0
0
0
0
0
default value  
February 1994  
35  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
Random Access counter is used for generating addresses in the Random access mode, the SYSTEM ADDRESS is  
mapped on to RACCNT as shown in Table 19.  
Table 19 SYSTEM address.  
6
2
5
1
4
0
3
2
2
1
1
0
0
8
RACCNT  
ROW  
COL  
PAG  
In mode DRAR SYSINFO must be transferred to the  
SAA2022 as 4 blocks of 32 bytes, one block in each  
segment.  
SYSINFO AND AUX DATA OFFSETS  
AUX data consists of 4 blocks of 36 bytes, one block being  
transferred in each time segment.  
Figures 26 to 29 show the offsets between the SYSINFO  
and AUX and the time segment counter, for the various  
modes of operation of the SAA2022.  
Each tape frame contains 128 bytes of SYSINFO, the  
SYSINFO bytes can for convenience, be considered as  
being grouped into 4 SYSINFO blocks, with:  
SYSBlk0 ==> SI0 to SI31,  
SYSBlk1 ==> SI32 to SI63, etc.  
In modes DPAP and DPAR SYSINFO transfers may occur  
in two ways:  
1. 4 blocks of 32 bytes, one block being transferred from  
the SAA2022 in each time segment.  
2. 1 block of 128 bytes being transferred in time  
segment 1.  
February 1994  
36  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
quarters, each of 6 pages where each page consists of  
8 columns × 448 rows. The pages are numbered 0 to 5,  
columns 0 to 7 and rows 0 to 431. This gives then a total  
of (2688 + (3 × 6 × 8 × 448)) = 67200 locations. The RAM  
quarter is chosen by the YZ bits of the microcontroller  
interface commands.  
BLOCK OFFSETS WITH RESPECT TO TIME SEGMENT  
Mode DPAP  
SYSBlk = (SNUM + 3) MOD 4;  
or read all 4 SYSINFO blocks when SNUM = 1.  
If AUX and MAIN were recorded simultaneously then  
AUXBlk = (SNUM + 1) MOD 4; else read and interpret  
1 AUX block in each time segment.  
Use of the scratch pad RAM outside the above ranges will  
upset the operation of the device.  
As with SYSINFO, AUX transfers can occur at high-speed  
at all times except the second half of time segment 0, that  
is when the status bit SLOWTFR is HIGH. During this  
period the microcontroller must poll the status bit RFBT to  
determine when a transfer can occur.  
Mode DRAR  
SYSBlk = SNUM;  
AUXBlk = (SNUM + 1) MOD 4.  
Mode DPAR  
There are two possible methods for addressing the scratch  
pad RAM. For random access of the scratch pad the  
address of each location is sent by the microcontroller to  
the SAA2022 before each location transfer. Alternatively,  
the address of the first location can be sent by the  
microcontroller before the first location transfer. This will  
automatically increment the row for all subsequent  
transfers until the end of the column. The RACCNT and  
BYTCNT registers are used for addressing the scratch  
pad. For the 64 k × 4-bit DRAM, and first quarter of  
256 k × 4 DRAM the mapping of the scratch pad RAM  
address onto the RACCNT and BYTCNT registers is  
shown in Tables 20 and 21. For the other three-quarters of  
the 256 k × 4 DRAM the mapping of the scratch pad RAM  
address onto the RACCNT and BYTCNT registers is  
shown in Tables 22 and 23.  
SYSBlk = (SNUM + 3) MOD 4;  
or read all 4 SYSINFO blocks when SNUM = 1;  
AUXBlk = (SNUM + 1) MOD 4.  
THE SCRATCH PAD RAM  
The SAA2022 provides the microcontroller with a scratch  
pad RAM, which it can use for any purpose. The size of the  
scratch pad depends upon the size of the DRAM used and  
the locations may be written and read in 8-bit or 12-bit  
units.  
For a 64 k × 4-bit DRAM, the scratch pad is arranged as  
6 pages, where each page consists of  
7 columns × 64 rows. The pages are numbered 0 to 5,  
columns 1 to 7 and rows 0 to 63. This gives a total of  
(6 × 7 × 64) = 2688 locations.  
For a 256 k × 4-bit DRAM, the scratch pad is the same as  
for the 64 k × 4 bit DRAM, plus an additional 3 RAM  
Table 22 RACCNT bit.  
Table 20 RACCNT bit.  
RACCNT BIT  
RACCNT BIT  
6
5
4
3
2
1
0
6
5
4
3
2
1
0
P2  
P1  
P0  
C2  
C1  
C0  
R8  
P2  
P1  
P0  
C2  
C1  
C0  
1
Table 23 BYTCNT bit.  
BYTCNT BIT  
Table 21 BYTCNT bit.  
BYTCNT BIT  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
R7  
R6  
R5  
R4  
R3  
R2  
R1  
R0  
1
0
R5  
R4  
R3  
R2  
R1  
R0  
February 1994  
37  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
Mode changes  
Table 24 Possible mode changes for the SAA2022.  
NEW MODE  
CURRENT MODE  
DPAP  
DRAR  
DPAR  
YES  
DPAP  
DRAR  
DPAR  
YES  
YES  
YES  
TIMING FOR MODE CHANGES  
Mode change DRAR to DPAP  
This mode change occurs at the first end of time  
Mode change DPAP to DRAR  
segment 0 after the SAA2022 receives the new setting.  
Writing of MAIN and AUX data stops immediately after the  
mode change. The time segment jumps back to 0, URDA  
goes HIGH and stays HIGH for 5 time segments  
This mode change occurs at the end of the time segment  
in which the SAA2022 receives the new settings. Writing  
of the first MAIN and AUX data commences at the start of  
the time segment 1 which follows two subsequent end of  
time segment 3 intervals. The delay to writing to tape is  
approximately 222 ms, as shown in Fig.22. If “seamless  
appending” is required the new settings should be sent to  
the SAA2022 during time segment 2.  
(213.3 ms) after which it goes LOW, as shown in Fig.24.  
Mode change DPAR to DPAP  
This mode change occurs at the first end of time  
segment 0 after the SAA2022 receives the new setting.  
The writing of AUX data to tape stops immediately after the  
mode change. The first AUX read from tape can be  
expected during the following time segment 0 or 1 (i.e.  
128 to 170.67 ms after the mode change), as shown in  
Fig.25.  
Mode change DPAP to DPAR  
This mode change occurs at the first end of time segment  
2 after the SAA2022 receives the new settings. Output of  
AUX to tape begins at the start of the following time  
segment 1, (i.e. 85.3 ms after the mode change), as  
shown in Fig.23.  
February 1994  
38  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
handbook, halfpage  
SNUM  
0
1
2 3 0  
1
2
3
0
1
2
handbook, halfpage  
SNUM  
1
2
3
0
1
2
3
0
1
2
DPAP  
DRAR  
DRAR  
MODE  
MODE  
DPAP  
DPAR  
85.3 ms  
DPAR  
NEW MODE  
NEW MODE  
222 ms  
AUXILIARY, MAIN  
TAPE OUT  
MEA707 - 2  
AUXILIARY  
TAPE OUT  
MEA708 - 2  
Fig.22 Mode change DPAP to DRAR (AUX  
and MAIN simultaneously recording).  
Fig.23 Mode change DPAP to DPAR  
(AUX after recording).  
handbook, halfpage  
SNUM  
MODE  
1
2
3
0
1
2
3
0
1
2
handbook, halfpage  
SNUM  
1
2
3
0
0
1
2
3
0
1
DPAR  
DPAP  
DPAP  
MODE  
DRAR  
DPAP  
DPAP  
NEW MODE  
NEW MODE  
AUXILIARY  
TAPE OUT  
128 ms  
URDA  
AUXILIARY  
TO  
213.3 ms  
MEA709 - 1  
MICROCONTROLLER  
170.66 ms  
MEA710 - 2  
Fig.24 Mode change DRAR to DPAP.  
Fig.25 Mode change DPAR to DPAP.  
February 1994  
39  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
SNUM  
0 1  
2
3
1
3
0
2
0
1
3
1
2
0
2
3
1
3
0
2
0
1
3
1
2
0
2
3
1
3
0
2
0
1
3
1
2
0
2
3
AUX BLK  
SYS BLK  
SYS BLK  
1
2
0
3
1
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
*
AUX, MAIN  
DATA INPUT  
FROM TAPE  
0 1  
2
3
0
1
2
3
0
1
2
3
0
1
2
MLB413  
Fig.26 SYSINFO and AUX block delays in DPAP (Audio and AUX simultaneously recorded).  
SNUM  
0 1  
2
3
0
1
2
3
0
1
2
3
0
1
0
2
DEPENDS ON PHASE OF AUX WRT MAIN DATA CHANNELS  
AUX BLK  
SYS BLK  
SYS BLK  
3
0
1
2
3
0
1
2
3
0
1
2
3
1
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
*
AUX, MAIN  
DATA INPUT  
FROM TAPE  
0 1  
2
3
0
1
2
3
0
1
2
3
0
1
2
MLB414  
Fig.27 SYSINFO and AUX block delays in mode DPAP (Audio and AUX recorded separately).  
February 1994  
40  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
SNUM  
0 1  
2
3
2
3
0
3
0
1
0
1
2
1
2
3
2
3
0
3
0
1
0
1
2
1
2
3
2
3
0
3
0
1
0
1
2
1
2
3
2
AUX BLK  
SYS BLK  
1
2
0 1  
AUX, MAIN  
DATA OUTPUT  
FROM TAPE  
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
MLB415  
Fig.28 SYSINFO and AUX block delays in mode DRAR.  
SNUM  
0 1  
2
3
1
3
0
2
0
1
3
1
2
0
2
3
1
3
0
2
0
1
3
1
2
0
2
3
1
3
0
2
0
1
3
1
2
0
2
3
AUX BLK  
SYS BLK  
SYS BLK  
1
2
0
3
1
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
*
MAIN DATA  
INPUT  
FROM TAPE  
0 1  
2
1
3
2
0
3
1
0
2
1
3
2
0
3
1
0
2
1
3
2
0
3
1
0
2
AUX OUTPUT  
TO TAPE  
0
1
1
MLB416  
Fig.29 SYSINFO and AUX block delays in mode DPAR.  
41  
February 1994  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 134).  
SYMBOL  
PARAMETER  
supply voltage  
CONDITIONS  
MIN.  
0.5  
MAX.  
+6.5  
VDD + 0.5 V  
UNIT  
VDD  
VI  
V
input voltage  
note 1  
0.5  
ISS  
supply current in VSS  
supply current in VDD  
input current  
100  
100  
mA  
mA  
IDD  
II  
10  
20  
+10  
mA  
mA  
mW  
°C  
°C  
V
IO  
output current  
+20  
Ptot  
Tstg  
Tamb  
Ves1  
Ves2  
total power dissipation  
storage temperature  
operating ambient temperature  
electrostatic handling  
electrostatic handling  
500  
55  
40  
1500  
70  
+150  
+85  
note 2  
note 3  
+1500  
+70  
V
Notes  
1. Input voltage should not exceed 6.5 V unless otherwise specified.  
2. Equivalent to discharging a 100 pF capacitor through a 1.5 kseries resistor.  
3. Equivalent to discharging a 200 pF capacitor through a 0 series resistor.  
DC CHARACTERISTICS  
VDD = 3.8 to 5.5 V; Tamb = 40 to +85 °C; unless otherwise specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Supply  
VDD  
supply voltage  
supply current  
note 1  
3.8  
5.0  
21  
16  
5.5  
30  
25  
V
IDD  
VDD = 5 V  
mA  
mA  
VDD = 3.8 V  
Inputs CLK24, TCH0 to TCH7, TAUX, PWRDWN, LTCLK, LTCNT0, LTCNT1, LTEN, PINI and SBMCLK  
VIL  
VIH  
II  
LOW level input voltage  
HIGH level input voltage  
input current  
0.3VDD  
V
0.7VDD  
V
VI = 0 V; Tamb = 25 °C  
VI = 5.5 V; Tamb = 25 °C  
10  
10  
µA  
µA  
February 1994  
42  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Input RESET  
VtLH  
threshold voltage  
LOW-HIGH  
0.8VDD  
V
V
V
VtHL  
threshold voltage  
HIGH-LOW  
0.2VDD  
Vhys  
II  
hysteresis  
V
tLH VtHL  
1.5  
input current  
VI = VDD  
25  
400  
µA  
Outputs RASN, CASN, WCLOCK and WDATA  
VOL  
VOH  
LOW level output voltage  
HIGH level output voltage  
IO = 3 mA  
0.4  
V
V
IO = 3 mA  
V
DD 0.5  
Outputs LTREF, WEN, OEN, A0 to A8, SPEED, SPDF, PINO1, PINO3, AZCHK, TEST2, TEST3, MCLK, SBEF,  
SBDIR and URDA  
VOL  
VOH  
LOW level output voltage  
HIGH level output voltage  
IO = 2 mA  
0.4  
V
V
IO = 2 mA  
V
DD 0.5  
Inputs/outputs D0 to D3; with outputs in 3-state  
VIL  
VIH  
II  
LOW level input voltage  
HIGH level input voltage  
input leakage current  
TTL-level  
2
0.8  
V
TTL-level  
V
VI = 0 V; Tamb = 25 °C  
VI = 5.5 V; Tamb = 25 °C  
10  
10  
µA  
µA  
Inputs/outputs D0 to D3  
VOL  
VOH  
LOW level output voltage  
HIGH level output voltage  
IO = 3 mA  
0.4  
V
V
IO = 3 mA  
V
DD 0.5  
Inputs/outputs LTDATA, SBCL, SBDA and SBWS; with outputs in 3-state  
VIL  
VIH  
II  
LOW level input voltage  
HIGH level input voltage  
input leakage current  
TTL-level  
0.3VDD  
V
TTL-level  
0.7VDD  
V
VI = 0 V; Tamb = 25 °C  
VI = 5.5 V; Tamb = 25 °C  
10  
10  
µA  
µA  
Inputs/outputs LTDATA, SBCL, SBDA and SBWS  
VOL  
VOH  
LOW level output voltage  
HIGH level output voltage  
IO = 3mA  
0.4  
V
V
IO = 3 mA  
V
DD 0.5  
Note  
1. For applications requiring minimum power dissipation the device may be operated from a nominal +4 V supply.  
February 1994  
43  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
AC CHARACTERISTICS  
VDD = 3.8 to 5.5 V; Tamb = 40 to +85 °C; unless otherwise specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Clock inputs  
Ci  
input capacitance  
10  
pF  
CLK24  
f
pulse frequency  
pulse width LOW  
pulse width HIGH  
23  
10  
10  
24.576  
26  
MHz  
ns  
tL-i  
tH-i  
ns  
SBMCLK  
f
pulse frequency  
pulse width LOW  
pulse width HIGH  
6.144  
12.5  
MHz  
ns  
tL-i  
30  
30  
tH-i  
ns  
Clock outputs  
CL  
load capacitance  
50  
pF  
MCLK  
f
pulse frequency  
6.144  
MHz  
ns  
tL-i  
pulse width LOW  
50  
50  
tH-i  
pulse width HIGH  
ns  
tdMFR  
delay time from CLK24  
delay time from PWRDWN  
note 1  
45  
ns  
td  
15  
ns  
Clock inputs  
Ci  
input capacitance  
10  
pF  
Inputs LTCLK, LTCNT0, LTCNT1, LTEN, RESET, TCH0 to TCH7 and TAUX  
tsuMR  
set-up time to MCLK  
hold time from MCLK  
note 2  
note 2  
40  
0
ns  
ns  
thMR  
Input PINI  
tsuMR  
set-up time to MCLK  
hold time from MCLK  
note 1  
note 1  
70  
0
ns  
ns  
thMR  
Outputs  
CL  
load capacitance  
50  
pF  
February 1994  
44  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Outputs A0 to A8, AZCHK, TEST2, LTREF, SBDIR, SBEF, SPDF, SPEED, PINO1 to PINO3, URDA, WCLOCK,  
WDATA, OEN and WEN  
tdMR  
delay time from MCLK  
note 2  
30  
ns  
Outputs OEN and WEN  
td  
delay time from PWRDWN  
15  
ns  
Output RASN  
tdFR  
delay time from CLK24  
note 1  
note 1  
30  
ns  
ns  
td  
delay time from PWRDWN  
15  
Output CASN  
tdFR  
td  
Inputs/outputs  
delay time from CLK24  
30  
ns  
ns  
delay time from PWRDWN  
15  
Ci  
input capacitance  
load capacitance  
10  
50  
pF  
pF  
CL  
Inputs/outputs D0 to D3  
tsuCR  
thCR  
tdMR  
td  
set-up time to CASN  
note 3  
note 3  
note 2  
10  
0
ns  
ns  
ns  
ns  
hold time from CASN  
delay time from MCLK  
delay time from PWRDWN  
25  
15  
Input/output LTDATA  
tsuMR  
thMR  
tdMR  
td  
set-up time to MCLK  
note 2  
note 2  
note 2  
40  
0
ns  
ns  
ns  
ns  
ns  
hold time from MCLK  
delay time from MCLK  
delay time from PWRDWN  
delay time from LTEN  
30  
15  
15  
td  
Inputs/outputs SBCL and SBWS  
tsuMR  
thMR  
tdSR  
tdMR  
td  
set-up time to MCLK  
note 2  
40  
0
ns  
ns  
ns  
ns  
ns  
hold time from MCLK  
delay time from SBMCLK  
delay time from MCLK  
delay time from PWRDWN  
note 2  
note 3  
40  
30  
notes 2 and 5  
15  
February 1994  
45  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Input/output SBDA  
tsuMR  
thMR  
tdMR  
td  
set-up time to MCLK  
note 2  
40  
ns  
hold time from MCLK  
delay time from MCLK  
delay time from PWRDWN  
note 2  
note 2  
0
ns  
ns  
ns  
30  
15  
Notes  
1. LOW-to-HIGH transition of CLK24.  
2. LOW-to-HIGH transition of MCLK.  
3. LOW-to-HIGH transition of CASN.  
4. LOW-to-HIGH transition of SBMCLK.  
5. 3-state control.  
t
L–i  
CLK24  
OUT1  
t
t
H–i  
dFR  
t
t
dMFR  
dMFR  
MCLK  
IN1  
t
H–O  
t
t
t
suMR  
hMR  
t
L–O  
dMR  
OUT2  
t
t
dFR  
dFR  
CASN  
t
t
hCR  
suCR  
IN2  
t
L– i  
SBMCLK  
OUT3  
t
H– i  
MEA716 - 1  
t
dSR  
Fig.30 Timing for AC characteristics.  
46  
February 1994  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
PACKAGE OUTLINE  
seating plane  
S
S
0.15  
19.2  
18.2  
B
64  
52  
51  
1
1.2  
0.8  
pin 1 index  
(4x)  
1.0  
20.1  
19.9  
25.2  
24.2  
0.50  
0.35  
33  
19  
20  
32  
0.50  
0.35  
1.2  
0.8  
0.15 M  
A
(4x)  
X
1.0  
14.1  
13.9  
A
1.45  
1.15  
2.85  
2.65  
3.2  
2.7  
0.30  
0.05  
0.25  
0.14  
1.55  
0.85  
o
0 to 7  
detail X  
MBC658 - 1  
Dimensions in mm.  
Fig.31 64-lead quad flat-pack; plastic (SOT208).  
47  
February 1994  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
Several techniques exist for reflowing; for example,  
SOLDERING  
Quad flat-packs  
BY WAVE  
thermal conduction by heated belt, infrared, and  
vapour-phase reflow. Dwell times vary between 50 and  
300 s according to method. Typical reflow temperatures  
range from 215 to 250 °C.  
During placement and before soldering, the component  
must be fixed with a droplet of adhesive. After curing the  
adhesive, the component can be soldered. The adhesive  
can be applied by screen printing, pin transfer or syringe  
dispensing.  
Preheating is necessary to dry the paste and evaporate  
the binding agent. Preheating duration: 45 min at 45 °C.  
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING  
IRON OR PULSE-HEATED SOLDER TOOL)  
Maximum permissible solder temperature is 260 °C, and  
maximum duration of package immersion in solder bath is  
10 s, if allowed to cool to less than 150 °C within 6 s.  
Typical dwell time is 4 s at 250 °C.  
Fix the component by first soldering two, diagonally  
opposite, end pins. Apply the heating tool to the flat part of  
the pin only. Contact time must be limited to 10 s at up to  
300 °C. When using proper tools, all other pins can be  
soldered in one operation within 2 to 5 s at between 270  
and 320 °C. (Pulse-heated soldering is not recommended  
for SO packages.)  
A modified wave soldering technique is recommended  
using two waves (dual-wave), in which, in a turbulent wave  
with high upward pressure is followed by a smooth laminar  
wave. Using a mildly-activated flux eliminates the need for  
removal of corrosive residues in most applications.  
For pulse-heated solder tool (resistance) soldering of VSO  
packages, solder is applied to the substrate by dipping or  
by an extra thick tin/lead plating before package  
placement.  
BY SOLDER PASTE REFLOW  
Reflow soldering requires the solder paste (a suspension  
of fine solder particles, flux and binding agent) to be  
applied to the substrate by screen printing, stencilling or  
pressure-syringe dispensing before device placement.  
February 1994  
48  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
DEFINITIONS  
Data sheet status  
Objective specification  
Preliminary specification  
Product specification  
Limiting values  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or  
more of the limiting values may cause permanent damage to the device. These are stress rating only and operation of  
the device at these or at any other conditions above those given in the Characteristics sections of the specification is  
not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N.V.  
February 1994  
49  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
NOTES  
February 1994  
50  
Philips Semiconductors  
Product specification  
Tape formatting and error  
correction for the DCC system  
SAA2022  
NOTES  
February 1994  
51  
Philips Semiconductors – a worldwide company  
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)  
Pakistan: Philips Markaz, M.A. Jinnah Rd., KARACHI 3,  
BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367  
Tel. (021)577 039, Fax. (021)569 1832  
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,  
Tel. (02)805 4455, Fax. (02)805 4466  
Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,  
Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,  
106 Valero St. Salcedo Village, P.O. Box 911, MAKATI,  
Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474  
Tel. (01)60 101-1236, Fax. (01)60 101-1211  
Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,  
Portugal: Av. Eng. Duarte Pacheco 6, 1009 LISBOA Codex,  
Tel. (01)683 121, Fax. (01)658 013  
Tel. (31)40 783 749, Fax. (31)40 788 399  
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,  
Brazil: Rua do Rocio 220 - 5th floor, Suite 51,  
CEP: 04552-903-SÃO PAULO-SP, Brazil.  
P.O. Box 7383 (01064-970).  
Tel. (65)350 2000, Fax. (65)251 6500  
South Africa: 195-215 Main Road, Martindale,  
P.O. Box 7430,JOHANNESBURG 2000,  
Tel. (011)470-5433, Fax. (011)470-5494  
Tel. (011)829-1166, Fax. (011)829-1849  
Spain: Balmes 22, 08007 BARCELONA,  
Tel. (03)301 6312, Fax. (03)301 42 43  
Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,  
Tel. (0)8-632 2000, Fax. (0)8-632 2745  
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,  
Tel. (01)488 2211, Fax. (01)481 7730  
Taiwan: 69, Min Sheng East Road, Sec 3, P.O. Box 22978,  
Canada: INTEGRATED CIRCUITS:  
Tel. (800)234-7381, Fax. (708)296-8556  
DISCRETE SEMICONDUCTORS: 601 Milner Ave,  
SCARBOROUGH, ONTARIO, M1B 1M8,  
Tel. (0416)292 5161 ext. 2336, Fax. (0416)292 4477  
Chile: Av. Santa Maria 0760, SANTIAGO,  
Tel. (02)773 816, Fax. (02)777 6730  
Colombia: Carrera 21 No. 56-17, BOGOTA, D.E., P.O. Box 77621,  
Tel. (571)217 4609, Fax. (01)217 4549  
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,  
TAIPEI 10446, Tel. (2)509 7666, Fax. (2)500 5899  
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,  
60/14 MOO 11, Bangna - Trad Road Km. 3  
Prakanong, BANGKOK 10260,  
Tel. (032)88 2636, Fax. (031)57 1949  
Tel. (2)399-3280 to 9, (2)398-2083, Fax. (2)398-2080  
Finland: Sinikalliontie 3, FIN-02630 ESPOO,  
Tel. (9)0-50261, Fax. (9)0-520971  
Turkey: Talatpasa Cad. No. 5, 80640 LEVENT/ISTANBUL,  
Tel. (0212)279 2770, Fax. (0212)269 3094  
France: 4 Rue du Port-aux-Vins, BP317,  
92156 SURESNES Cedex,  
Tel. (01)4099 6161, Fax. (01)4099 6427  
Germany: P.O. Box 10 63 23, 20095 HAMBURG ,  
United Kingdom: Philips Semiconductors Limited, P.O. Box 65,  
Philips House, Torrington Place, LONDON, WC1E 7HD,  
Tel. (071)436 41 44, Fax. (071)323 03 42  
Tel. (040)3296-0, Fax. (040)3296 213  
United States:INTEGRATED CIRCUITS:  
811 East Arques Avenue, SUNNYVALE, CA 94088-3409,  
Tel. (800)234-7381, Fax. (708)296-8556  
Greece: No. 15, 25th March Street, GR 17778 TAVROS,  
Tel. (01)4894 339/4894 911, Fax. (01)4814 240  
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,  
P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,  
Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300  
Hong Kong: 15/F Philips Ind. Bldg., 24-28 Kung Yip St.,  
KWAI CHUNG, Tel. (0)4245 121, Fax. (0)4806 960  
India: PEICO ELECTRONICS & ELECTRICALS Ltd.,  
Components Dept., Shivsagar Estate, Block 'A',  
Dr. Annie Besant Rd., Worli, BOMBAY 400 018,  
Tel. (022)4938 541, Fax. (022)4938 722  
Uruguay: Coronel Mora 433, MONTEVIDEO,  
Tel. (02)70-4044, Fax. (02)92 0601  
Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,  
P.O. Box 4252, JAKARTA 12950,  
Tel. (021)5201 122, Fax. (021)5205 189  
Ireland: Newstead, Clonskeagh, DUBLIN 14,  
Tel. (01)640 000, Fax. (01)640 200  
Italy: Viale F. Testi, 327, 20162 MILANO,  
Tel. (02)6752.1, Fax. (02)6752.3350  
Japan: Philips Bldg 13-37, Kohnan2-chome, Minato-ku, KOKIO 108,  
Tel. (03)3740 5101, Fax. (03)3740 0570  
Korea: (Republic of) Philips House, 260-199 Itaewon-dong,  
For all other countries apply to: Philips Semiconductors,  
International Marketing and Sales, Building BAF-1,  
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,  
Telex 35000 phtcnl, Fax. +31-40-724825  
Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022  
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,  
SELANGOR, Tel. (03)757 5511, Fax. (03)757 4880  
Mexico: Philips Components, 5900 Gateway East, Suite 200,  
EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556  
Netherlands: Postbus 90050, 5600 PB EINDHOVEN,  
Tel. (040)78 37 49, Fax. (040)78 83 99  
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,  
SCD28  
© Philips Electronics N.V. 1994  
All rights are reserved. Reproduction in whole or in part is prohibited without the  
prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation  
or contract, is believed to be accurate and reliable and may be changed without  
notice. No liability will be accepted by the publisher for any consequence of its  
use. Publication thereof does not convey nor imply any license under patent- or  
other industrial or intellectual property rights.  
Tel. (09)849-4160, Fax. (09)849-7811  
Norway: Box 1, Manglerud 0612, OSLO,  
Tel. (22)74 8000, Fax. (22)74 8341  
Philips Semiconductors  

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