PSMN8R3-40YS [NXP]
N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET; N沟道LFPAK 40 V 8.6 mΩ的标准电平MOSFET
| 型号： | PSMN8R3-40YS |
| 厂家： | 
NXP |
| 描述： | N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET |
| 文件： | 总13页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PSMN8R3-40YS
N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET
Rev. 01 — 25 June 2009
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel MOSFET in LFPAK package qualified to 175 °C. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
1.2 Features and benefits
Advanced TrenchMOS provides low
Improved mechanical and thermal
RDSon and low gate charge
characteristics
High efficiency gains in switching
LFPAK provides maximum power
power converters
density in a Power SO8 package
1.3 Applications
DC-to-DC convertors
Lithium-ion battery protection
Load switching
Motor control
Server power supplies
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C
Min
Typ
Max Unit
VDS
ID
-
-
-
-
40
70
V
A
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 2
-
-
-
74
W
Tj
junction temperature
-55
175
°C
Avalanche ruggedness
EDS(AL)S non-repetitive
drain-source
VGS = 10 V; Tj(init) = 25 °C;
ID = 62 A; Vsup ≤ 40 V;
unclamped; RGS = 50 Ω
-
-
33
mJ
avalanche energy
Dynamic characteristics
QGD
gate-drain charge
total gate charge
VGS = 10 V; ID = 25 A;
VDS = 20 V; see Figure 14;
see Figure 15
-
-
4.5
20
-
-
nC
nC
QG(tot)
PSMN8R3-40YS
NXP Semiconductors
N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET
Table 1.
Quick reference …continued
Symbol Parameter
Static characteristics
Conditions
Min
Typ
Max Unit
RDSon
drain-source
on-state resistance
VGS = 10 V; ID = 15 A;
Tj = 100 °C; see Figure 12
-
-
-
11.6 mΩ
VGS = 10 V; ID = 15 A;
6.6
8.6
mΩ
Tj = 25 °C; see Figure 12;
see Figure 13
2. Pinning information
Table 2.
Pinning information
Pin
1
Symbol Description
Simplified outline
Graphic symbol
S
S
S
G
D
source
source
source
gate
mb
D
2
3
G
4
mbb076
S
mb
drain
1
2 3 4
SOT669
(LFPAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PSMN8R3-40YS LFPAK
plastic single-ended surface-mounted package (LFPAK); 4 leads
SOT669
PSMN8R3-40YS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 25 June 2009
2 of 13
PSMN8R3-40YS
NXP Semiconductors
N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
40
Unit
V
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
-
VDGR
VGS
-
40
V
-20
20
V
ID
VGS = 10 V; Tmb = 100 °C; see Figure 1
VGS = 10 V; Tmb = 25 °C; see Figure 1
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3
-
50
A
-
70
A
IDM
peak drain current
-
274
74
A
Ptot
Tstg
Tj
total power dissipation Tmb = 25 °C; see Figure 2
storage temperature
-
W
°C
°C
°C
-55
-55
-
175
175
260
junction temperature
Tsld(M)
peak soldering
temperature
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
-
-
70
A
A
ISM
tp ≤ 10 µs; pulsed; Tmb = 25 °C
274
Avalanche ruggedness
EDS(AL)S non-repetitive
VGS = 10 V; Tj(init) = 25 °C; ID = 62 A; Vsup ≤ 40 V;
-
33
mJ
drain-source avalanche unclamped; RGS = 50 Ω
energy
003aad264
03aa16
120
80
ID
P
(%)
der
(A)
60
80
40
20
0
40
0
0
50
100
150
200
0
50
100
150
200
Tmb (°C)
T
mb
(°C)
Fig 1. Continuous drain current as a function of
mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
PSMN8R3-40YS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 25 June 2009
3 of 13
PSMN8R3-40YS
NXP Semiconductors
N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET
003aad320
103
ID
10μs
(A)
Limit RDSon = VDS / ID
102
10
1
100μs
1ms
DC
10ms
100ms
10-1
10-1
1
10
102
VDS (V)
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from see Figure 4
junction to mounting
base
-
1.39
2
K/W
003aac558
10
Zth(j-mb)
(K/W)
1
10-1
10-2
δ = 0.5
0.2
0.1
t
p
P
δ =
0.05
T
0.02
t
t
p
single shot
T
10-6
10-5
10-4
10-3
10-2
10-1
1
tp (s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN8R3-40YS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 25 June 2009
4 of 13
PSMN8R3-40YS
NXP Semiconductors
N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
36
40
-
-
-
-
-
V
V
V
-
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS; Tj = -55 °C;
4.6
voltage
see Figure 10; see Figure 11
ID = 1 mA; VDS = VGS; Tj = 175 °C;
see Figure 10; see Figure 11
1
2
-
-
V
V
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 10; see Figure 11
3
4
IDSS
drain leakage current
gate leakage current
VDS = 40 V; VGS = 0 V; Tj = 25 °C
VDS = 40 V; VGS = 0 V; Tj = 125 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
-
-
-
-
-
-
-
-
-
-
1.5
µA
µA
nA
nA
mΩ
10
IGSS
100
100
11.6
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 15 A; Tj = 100 °C;
see Figure 12
VGS = 10 V; ID = 15 A; Tj = 175 °C;
see Figure 12
-
-
-
-
16
8.6
-
mΩ
mΩ
Ω
VGS = 10 V; ID = 15 A; Tj = 25 °C;
6.6
0.63
see Figure 12; see Figure 13
RG
internal gate resistance f = 1 MHz
(AC)
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 20 V; VGS = 10 V;
see Figure 14; see Figure 15
-
20
-
nC
ID = 0 A; VDS = 0 V; VGS = 10 V
-
-
-
17
8
-
-
-
nC
nC
nC
QGS
gate-source charge
ID = 25 A; VDS = 20 V; VGS = 10 V;
see Figure 14; see Figure 15
QGS(th)
pre-threshold
4
gate-source charge
QGS(th-pl)
post-threshold
-
4
-
nC
gate-source charge
QGD
gate-drain charge
-
-
4.5
5.5
-
-
nC
V
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 20 V; see Figure 14;
see Figure 15
Ciss
Coss
Crss
input capacitance
output capacitance
VDS = 20 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 16
-
-
-
1215
270
-
-
-
pF
pF
pF
reverse transfer
capacitance
146
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 30 V; RL = 1.5 Ω; VGS = 10 V;
RG(ext) = 4.7 Ω
-
-
-
-
13
11
21
6
-
-
-
-
ns
ns
ns
ns
turn-off delay time
fall time
PSMN8R3-40YS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 25 June 2009
5 of 13
PSMN8R3-40YS
NXP Semiconductors
N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET
Table 6.
Symbol
Characteristics …continued
Parameter
Conditions
Min
Typ
Max
Unit
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 17
-
0.84
1.2
V
trr
reverse recovery time
recovered charge
IS = 50 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 20 V
-
-
29
26
-
-
ns
Qr
nC
[1] Tested to JEDEC standards where applicable.
003aad163
003aad165
80
70
ID
ID
(A)
(A)
60
20
10
8
7
6.5
60
50
40
30
20
10
0
6
40
20
0
5.5
Tj = 175 °C
Tj = 25 °C
5
VGS (V) = 4.5
0
1
2
3
4
0
3
6
9
V
DS (V)
V
GS (V)
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
003aad171
003aad170
40
40
RDSon
gfs
(mΩ)
(S)
30
20
10
0
30
20
10
0
0
5
10
15
20
0
20
40
60
ID (A)
VGS (V)
Fig 7. Drain-source on-state resistance as a function
of gate-source voltage; typical values
Fig 8. Forward transconductance as a function of
drain current; typical values
PSMN8R3-40YS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 25 June 2009
6 of 13
PSMN8R3-40YS
NXP Semiconductors
N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET
003aad169
03aa35
−1
10
1800
I
D
Ciss
C
(pF)
(A)
min
typ
max
−2
−3
−4
−5
−6
10
1500
1200
900
10
10
10
10
Crss
600
0
3
6
9
12
0
2
4
6
VGS (V)
V
GS
(V)
Fig 9. Input and reverse transfer capacitances as a
function of gate-source voltage; typical values
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
003aad280
03aa27
5
2
V
GS(th)
(V)
a
4
3
2
1
0
max
1.5
typ
1
0.5
0
min
−60
0
60
120
180
−60
0
60
120
180
T ( C)
°
j
T (°C)
j
Fig 11. Gate-source threshold voltage as a function of
junction temperature
Fig 12. Normalized drain-source on-state resistance
factor as a function of junction temperature
PSMN8R3-40YS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 25 June 2009
7 of 13
PSMN8R3-40YS
NXP Semiconductors
N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET
003aad164
20
6.5
VGS (V) = 6
V
DS
RDSon
(mΩ)
I
D
15
V
GS(pl)
7
V
GS(th)
V
GS
7.5
8
10
Q
GS1
Q
GS2
Q
GS
Q
GD
10
20
Q
G(tot)
003aaa508
5
Fig 14. Gate charge waveform definitions
0
20
40
60
ID (A)
Fig 13. Drain-source on-state resistance as a function
of drain current; typical values
003aad167
003aad168
10
104
VGS
(V)
C
(pF)
8
32V
VDS = 20V
8V
6
Ciss
103
4
2
0
Coss
Crss
102
10-1
0
5
10
15
20
25
G (nC)
1
10
102
Q
VDS (V)
Fig 15. Gate-source voltage as a function of gate
charge; typical values
Fig 16. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PSMN8R3-40YS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 25 June 2009
8 of 13
PSMN8R3-40YS
NXP Semiconductors
N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET
003aad166
100
IS
(A)
80
60
40
20
0
Tj = 175 °C
Tj = 25 °C
0
0.3
0.6
0.9
1.2
SD (V)
V
Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values
PSMN8R3-40YS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 25 June 2009
9 of 13
PSMN8R3-40YS
NXP Semiconductors
N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads
SOT669
A
2
E
A
C
c
E
b
b
2
1
2
L
3
1
mounting
base
b
4
D
1
D
H
L
2
1
2
3
4
X
e
w
M
c
A
b
1/2 e
A
(A )
3
C
A
1
θ
L
detail X
y
C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
(1)
D
(1)
(1)
1
A
A
A
H
L
L
L
2
w
y
θ
UNIT
A
b
b
b
b
c
c
E
E
1
e
1
2
3
1
2
3
4
2
max
1.20 0.15 1.10
1.01 0.00 0.95
0.50 4.41 2.2 0.9 0.25 0.30 4.10
0.35 3.62 2.0 0.7 0.19 0.24 3.80
5.0 3.3
4.8 3.1
6.2 0.85 1.3 1.3
5.8 0.40 0.8 0.8
8°
0°
mm
0.25
4.20
1.27
0.25 0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
04-10-13
06-03-16
SOT669
MO-235
Fig 18. Package outline SOT669 (LFPAK)
PSMN8R3-40YS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 25 June 2009
10 of 13
PSMN8R3-40YS
NXP Semiconductors
N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PSMN8R3-40YS_1
20090625
Product data sheet
-
-
PSMN8R3-40YS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 25 June 2009
11 of 13
PSMN8R3-40YS
NXP Semiconductors
N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET
9. Legal information
9.1 Data sheet status
Document status [1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
Applications — Applications that are described herein for any of these
9.2 Definitions
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
9.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PSMN8R3-40YS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 25 June 2009
12 of 13
PSMN8R3-40YS
NXP Semiconductors
N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1
1.2
1.3
1.4
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits. . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
Ordering information. . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10
Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . .12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
9.1
9.2
9.3
9.4
10
Contact information. . . . . . . . . . . . . . . . . . . . . .12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 June 2009
Document identifier: PSMN8R3-40YS_1
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