PSMN1R8-40YLC [NXP]
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower technology; N沟道40 V 1.8英里©逻辑电平LFPAK采用NextPower技术MOSFET
| 型号： | PSMN1R8-40YLC |
| 厂家： | 
NXP |
| 描述： | N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower technology |
| 文件： | 总14页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PSMN1R8-40YLC
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using
NextPower technology
22 August 2012
Product data sheet
1. Product profile
1.1 General description
Logic level enhancement mode N-channel MOSFET in LFPAK package. This product
is designed and qualified for use in a wide range of industrial, communications and
domestic equipment.
1.2 Features and benefits
High reliability Power SO8 package, qualified to 175°C
•
•
•
•
Optimised for 4.5V Gate drive utilising NextPower Superjunction technology
Ultra low QG, QGD, & QOSS for high system efficiencies at low and high loads
Ultra low Rdson and low parasitic inductance
1.3 Applications
DC-to-DC converters
Load switching
Power OR-ing
Server power supplies
Sync rectifier
•
•
•
•
•
1.4 Quick reference data
Table 1.
Symbol
Quick reference data
Parameter
Conditions
Min
Typ
Max
40
Unit
V
VDS
ID
drain-source voltage
drain current
25 °C ≤ Tj ≤ 175 °C
Tmb = 25 °C; VGS = 10 V; Fig. 1
-
-
-
-
-
[1]
-
100
272
175
A
Ptot
Tj
total power dissipation Tmb = 25 °C; Fig. 2
junction temperature
-
W
-55
°C
Static characteristics
RDSon drain-source on-state
resistance
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
Fig. 12
-
-
1.8
1.5
2.1
1.8
mΩ
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 12
Dynamic characteristics
QGD gate-drain charge
VGS = 4.5 V; ID = 25 A; VDS = 20 V;
Fig. 15; Fig. 14
-
10.9
-
nC
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NXP Semiconductors
PSMN1R8-40YLC
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
QG(tot)
total gate charge
VGS = 4.5 V; ID = 25 A; VDS = 20 V;
Fig. 15; Fig. 14
-
45
-
nC
[1] Continuous current is limited by package.
2. Pinning information
Table 2.
Pin
Pinning information
Symbol Description
Simplified outline
Graphic symbol
mb
D
S
1
S
S
S
G
D
source
source
source
gate
2
G
3
mbb076
4
1
2 3 4
mb
mounting base; connected to
drain
LFPAK; Power-
SO8 (SOT669)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
plastic single-ended surface-mounted package; 4 leads
Version
PSMN1R8-40YLC
LFPAK;
SOT669
Power-SO8
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
40
Unit
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
25 °C ≤ Tj ≤ 175 °C
-
V
VDGR
VGS
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
40
V
-20
20
V
ID
VGS = 10 V; Tmb = 25 °C; Fig. 1
VGS = 10 V; Tmb = 100 °C; Fig. 1
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 4
Tmb = 25 °C; Fig. 2
[1]
[1]
-
100
100
1128
272
175
175
260
A
-
A
IDM
Ptot
Tstg
Tj
peak drain current
-
A
total power dissipation
storage temperature
junction temperature
peak soldering temperature
-
W
°C
°C
°C
-55
-55
-
Tsld(M)
PSMN1R8-40YLC
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Product data sheet
22 August 2012
2 / 14
NXP Semiconductors
PSMN1R8-40YLC
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
Symbol
Parameter
Conditions
Min
Max
Unit
VESD
electrostatic discharge voltage MM (JEDEC JESD22-A115)
890
-
V
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
[1]
-
-
100
A
A
ISM
pulsed; tp ≤ 10 µs; Tmb = 25 °C
1128
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C; ID = 100 A;
Vsup ≤ 40 V; RGS = 50 Ω; unclamped;
Fig. 3
-
248
mJ
[1] Continuous current is limited by package.
003aaj880
03na19
120
320
I
D
P
der
(%)
(A)
240
80
160
80
0
(1)
40
0
0
50
100
150
200
0
50
100
150
200
T
(°C)
T
(°C)
mb
mb
Fig. 1. Continuous drain current as a function of
mounting base temperature
Fig. 2. Normalized total power dissipation as a
function of mounting base temperature
PSMN1R8-40YLC
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© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
3 / 14
NXP Semiconductors
PSMN1R8-40YLC
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
003aaj881
103
I
(A)
AL
102
(1)
10
(2)
1
10-3
10-2
10-1
1
10
t
(ms)
AL
Fig. 3. Single pulse avalanche rating; avalanche current as a function of avalanche time
003aaj882
104
I
D
(A)
103
Limit RDSon = V / I
DS
D
µ
tp =10
s
102
10
100 µs
DC
1 ms
10 ms
100 ms
1
10-1
10-1
1
10
102
V
(V)
DS
Fig. 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
0.55
Unit
Rth(j-mb)
thermal resistance
from junction to
mounting base
Fig. 5
-
0.45
K/W
PSMN1R8-40YLC
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© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
4 / 14
NXP Semiconductors
PSMN1R8-40YLC
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
003aaj883
1
Z
δ = 0.5
0.2
th(j-mb)
(K/W)
10-1
0.1
0.05
t
p
P
δ =
10-2
0.02
T
single shot
t
t
p
T
10-3
10-6
10-5
10-4
10-3
10-2
10-1
1
t (s)
p
Fig. 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
40
-
-
V
V
V
36
-
-
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C;
1.05
1.45
1.95
voltage
Fig. 10
ID = 10 mA; VDS = VGS; Tj = 150 °C;
Fig. 11
0.5
-
-
-
-
V
V
ID = 1 mA; VDS = VGS; Tj = -55 °C;
Fig. 11
2.25
IDSS
drain leakage current
gate leakage current
VDS = 40 V; VGS = 0 V; Tj = 25 °C
VDS = 40 V; VGS = 0 V; Tj = 150 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
-
-
-
-
-
-
1
µA
µA
nA
nA
mΩ
-
100
100
100
2.1
IGSS
-
-
RDSon
drain-source on-state
resistance
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
Fig. 12
1.8
VGS = 4.5 V; ID = 25 A; Tj = 150 °C;
Fig. 12; Fig. 13
-
-
-
-
3.6
mΩ
mΩ
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 12
1.5
-
1.8
VGS = 10 V; ID = 25 A; Tj = 150 °C;
Fig. 12; Fig. 13
3.25
PSMN1R8-40YLC
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Product data sheet
22 August 2012
5 / 14
NXP Semiconductors
PSMN1R8-40YLC
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RG
gate resistance
f = 1 MHz
0.5
1
2
Ω
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 20 V; VGS = 10 V;
Fig. 14; Fig. 15
-
-
96
45
-
-
nC
nC
ID = 25 A; VDS = 20 V; VGS = 4.5 V;
Fig. 15; Fig. 14
ID = 0 A; VDS = 0 V; VGS = 10 V
-
-
-
88
-
-
-
nC
nC
nC
QGS
gate-source charge
ID = 25 A; VDS = 20 V; VGS = 4.5 V;
Fig. 15; Fig. 14
15.5
8.4
QGS(th)
pre-threshold gate-
source charge
QGS(th-pl)
post-threshold gate-
source charge
-
7.1
-
nC
QGD
gate-drain charge
-
-
10.9
2.7
-
-
nC
V
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 20 V; Fig. 15; Fig. 14
Ciss
Coss
Crss
input capacitance
output capacitance
VDS = 20 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; Fig. 16
-
-
-
6680
825
-
-
-
pF
pF
pF
reverse transfer
capacitance
310
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 20 V; RL = 0.8 Ω; VGS = 4.5 V;
RG(ext) = 5 Ω
-
-
-
-
-
32.2
37
-
-
-
-
-
ns
ns
ns
ns
nC
turn-off delay time
fall time
62.5
31.7
30
Qoss
output charge
VGS = 0 V; VDS = 20 V; f = 1 MHz;
Tj = 25 °C
Source-drain diode
VSD source-drain voltage
trr
IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 17
-
-
-
-
0.77
37
1.1
V
reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
-
-
-
ns
nC
ns
VDS = 20 V
Qr
ta
recovered charge
43
reverse recovery rise
time
VGS = 0 V; IS = 25 A; dIS/dt = -100 A/µs;
VDS = 20 V; Fig. 18
21
tb
reverse recovery fall
time
-
16
-
ns
PSMN1R8-40YLC
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Product data sheet
22 August 2012
6 / 14
NXP Semiconductors
PSMN1R8-40YLC
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
003aaj884
003aaj885
100
10
I
4.5
10
D
3
R
2.6
DSon
(A)
Ω
(m
)
80
60
40
20
0
7.5
5
2.4
2.5
0
V
(V) =
2.2
GS
0
0.5
1
1.5
2
0
4
8
12
16
V
(V)
V
(V)
GS
DS
Fig. 6. Output characteristics; drain current as a
function of drain-source voltage; typical values
Fig. 7. Drain-source on-state resistance as a function
of gate-source voltage; typical values
003aaj886
003aaj887
300
100
g
I
fs
D
(S)
(A)
250
80
200
150
100
50
60
40
20
Tj = 150 °C
Tj = 25 °C
0
0
0
20
40
60
80
100
(A)
0
1
2
3
4
I
V
(V)
GS
D
Fig. 8. Forward transconductance as a function of
drain current; typical values
Fig. 9. Transfer characteristics; drain current as a
function of gate-source voltage; typical values
PSMN1R8-40YLC
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Product data sheet
22 August 2012
7 / 14
NXP Semiconductors
PSMN1R8-40YLC
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
003aaj888
003aaj889
10-1
3
I
D
V
GS(th)
(V)
(A)
Max (1mA)
10-2
I
= 5mA
D
2
1
0
Max
Min
Typ
10-3
10-4
10-5
10-6
1mA
Min (5mA)
0
1
2
3
-60
0
60
120
180
T (°C)
V
(V)
j
GS
Fig. 10. Sub-threshold drain current as a function of
gate-source voltage
Fig. 11. Gate-source threshold voltage as a function of
junction temperature
003aaj890
003aaj891
10
2
2.4
R
DSon
a
2.6
10V
(mΩ)
8
1.5
6
V
=4.5V
GS
1
0.5
0
4
3
4.5
2
10
VGS (V) =
0
0
20
40
60
80
100
-60
0
60
120
180
I (A)
T (°C)
j
D
Fig. 12. Drain-source on-state resistance as a function Fig. 13. Normalized drain-source on-state resistance
of drain current; typical values factor as a function of junction temperature
PSMN1R8-40YLC
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© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
8 / 14
NXP Semiconductors
PSMN1R8-40YLC
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
003aaj892
10
V
DS
V
GS
(V)
I
D
8
V
GS(pl)
8 V
6
4
2
0
32 V
V
GS(th)
GS
V
VDS
=
20 V
Q
GS1
Q
GS2
Q
GS
Q
GD
Q
G(tot)
003aaa508
Fig. 14. Gate charge waveform definitions
0
20
40
60
80
Q
100
(nC)
G
Fig. 15. Gate-source voltage as a function of gate
charge; typical values
003aaj893
003aaj894
104
100
I
C
S
iss
C
(A)
(pF)
80
60
40
103
C
oss
C
rss
20
Tj = 150°C
°
Tj = 25
C
102
10-1
0
1
10
102
0
0.3
0.6
0.9
V
1.2
VDS (V)
(V)
SD
Fig. 16. Input, output and reverse transfer capacitances Fig. 17. Source current as a function of source-drain
as a function of drain-source voltage; typical
values
voltage; typical values
PSMN1R8-40YLC
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Product data sheet
22 August 2012
9 / 14
NXP Semiconductors
PSMN1R8-40YLC
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
003aaf 444
ID
(A)
trr
ta
tb
0
0.25 I
RM
IRM
t (s)
Fig. 18. Reverse recovery timing definition
PSMN1R8-40YLC
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Product data sheet
22 August 2012
10 / 14
NXP Semiconductors
PSMN1R8-40YLC
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
7. Package outline
Plastic single-ended surface-mounted package (LFPAK; Power-SO8); 4 leads
SOT669
A
2
E
A
C
c
E
b
b
2
1
2
L
3
1
mounting
base
b
4
D
1
D
H
L
2
1
2
3
4
X
e
w
M
c
A
b
1/2 e
A
(A )
3
C
A
1
θ
L
detail X
y
C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
(1)
D
(1)
(1)
1
A
A
A
H
L
L
L
2
w
y
θ
UNIT
A
b
b
b
b
c
c
E
E
1
e
1
2
3
1
2
3
4
2
max
1.20 0.15 1.10
1.01 0.00 0.95
0.50 4.41 2.2 0.9 0.25 0.30 4.10
0.35 3.62 2.0 0.7 0.19 0.24 3.80
5.0 3.3
4.8 3.1
6.2 0.85 1.3
5.8 0.40 0.8
1.3
0.8
8°
0°
mm
0.25
4.20
1.27
0.25 0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
06-03-16
11-03-25
SOT669
MO-235
Fig. 19. Package outline LFPAK; Power-SO8 (SOT669)
PSMN1R8-40YLC
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© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
11 / 14
NXP Semiconductors
PSMN1R8-40YLC
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
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punitive, special or consequential damages (including - without limitation -
lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
Product
Definition
status [1][2] status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Preliminary
[short] data
sheet
Qualification This document contains data from the
preliminary specification.
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malfunction of an NXP Semiconductors product can reasonably be expected
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Product
[short] data
sheet
Production
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
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Applications — Applications that are described herein for any of these
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NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
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the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
8.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
PSMN1R8-40YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
12 / 14
NXP Semiconductors
PSMN1R8-40YLC
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of non-
automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and
(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
8.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
PSMN1R8-40YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
13 / 14
NXP Semiconductors
PSMN1R8-40YLC
N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower
technology
9. Contents
1
Product profile ....................................................... 1
1.1
1.2
1.3
1.4
General description .............................................. 1
Features and benefits ...........................................1
Applications ..........................................................1
Quick reference data ............................................ 1
2
3
4
5
6
7
Pinning information ...............................................2
Ordering information .............................................2
Limiting values .......................................................2
Thermal characteristics .........................................4
Characteristics .......................................................5
Package outline ................................................... 11
8
Legal information .................................................12
Data sheet status ............................................... 12
Definitions ...........................................................12
Disclaimers .........................................................12
Trademarks ........................................................ 13
8.1
8.2
8.3
8.4
© NXP B.V. 2012. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 August 2012
PSMN1R8-40YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
14 / 14
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