PSMN1R9-25YLC,115 [NXP]
PSMN1R9-25YLC - N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using NextPower technology SOIC 4-Pin;
| 型号： | PSMN1R9-25YLC,115 |
| 厂家： | 
NXP |
| 描述： | PSMN1R9-25YLC - N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using NextPower technology SOIC 4-Pin |
| 文件： | 总15页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PSMN1R9-25YLC
AK
LFP
N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using
NextPower technology
Rev. 1 — 2 May 2011
Product data sheet
1. Product profile
1.1 General description
Logic level enhancement mode N-channel MOSFET in LFPAK package. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
1.2 Features and benefits
High reliability Power SO8 package,
Optimised for 4.5V Gate drive utilising
qualified to 175°C
NextPower Superjunction technology
Low parasitic inductance and
Ultra low QG, QGD and QOSS for high
system efficiencies at low and high
loads
resistance
1.3 Applications
DC-to-DC converters
Lithium-ion battery protection
Load switching
Power OR-ing
Server power supplies
Sync rectifier
1.4 Quick reference data
Table 1.
Symbol
VDS
Quick reference data
Parameter
Conditions
Min
Typ
Max Unit
drain-source voltage
drain current
25 °C ≤ Tj ≤ 175 °C
-
-
-
-
25
V
A
[1]
ID
Tmb = 25 °C; VGS = 10 V;
see Figure 1
100
Ptot
Tj
total power dissipation Tmb = 25 °C; see Figure 2
junction temperature
-
-
-
141
175
W
-55
°C
Static characteristics
RDSon drain-source on-state VGS = 4.5 V; ID = 25 A;
-
-
2.2
1.7
2.7
mΩ
resistance
Tj = 25 °C;
see Figure 12
VGS = 10 V; ID = 25 A;
Tj = 25 °C;
2.05 mΩ
see Figure 12
PSMN1R9-25YLC
NXP Semiconductors
N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using
Table 1.
Symbol
Dynamic characteristics
Quick reference data …continued
Parameter
Conditions
Min
Typ
Max Unit
QGD
gate-drain charge
total gate charge
VGS = 4.5 V; ID = 25 A;
VDS = 12 V;
see Figure 14;
see Figure 15
-
-
7.4
27
-
-
nC
nC
QG(tot)
[1] Continuous current is limited by package.
2. Pinning information
Table 2.
Pinning information
Symbol Description
Pin
1
Simplified outline
Graphic symbol
S
S
S
G
D
source
source
source
gate
mb
D
2
3
G
4
mbb076
S
mb
mounting base;
1
2 3 4
connected to drain
SOT669 (LFPAK;
Power-SO8)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PSMN1R9-25YLC
LFPAK;
plastic single-ended surface-mounted package; 4 leads
SOT669
Power-SO8
4. Marking
Table 4.
Marking codes
Type number
PSMN1R9-25YLC
Marking code[1]
1C925L
[1] % = placeholder for manufacturing site code.
PSMN1R9-25YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 May 2011
2 of 15
PSMN1R9-25YLC
NXP Semiconductors
N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using
5. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
25
Unit
V
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
25 °C ≤ Tj ≤ 175 °C
-
VDGR
VGS
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
25
V
-20
20
V
[1]
[1]
ID
VGS = 10 V; Tmb = 25 °C; see Figure 1
VGS = 10 V; Tmb = 100 °C; see Figure 1
-
-
-
100
100
799
A
A
IDM
peak drain current
pulsed; tp ≤ 10 µs; Tmb = 25 °C;
A
see Figure 4
Ptot
total power dissipation
storage temperature
Tmb = 25 °C; see Figure 2
-
141
175
175
260
-
W
°C
°C
°C
V
Tstg
Tj
-55
-55
-
junction temperature
Tsld(M)
VESD
Source-drain diode
peak soldering temperature
electrostatic discharge voltage MM (JEDEC JESD22-A115)
590
IS
source current
peak source current
Tmb = 25 °C
-
-
100
799
A
A
ISM
pulsed; tp ≤ 10 µs; Tmb = 25 °C
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C; ID = 100 A;
Vsup ≤ 25 V; unclamped; RGS = 50 Ω;
see Figure 3
-
112
mJ
[1] Continuous current is limited by package.
PSMN1R9-25YLC
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 May 2011
3 of 15
PSMN1R9-25YLC
NXP Semiconductors
N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using
003aaf825
03na19
120
210
I
D
(A)
180
P
(%)
der
150
80
120
(1)
90
60
30
0
40
0
0
50
100
150
200
0
50
100
150
200
T
(°C)
T
mb
(°C)
mb
Fig 1. Continuous drain current as a function of
mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
003aaf 839
103
IAL
(A)
(1)
102
(2)
10
1
10-1
10-3
10-2
10-1
1
10
tAL (ms)
Fig 3. Single pulse avalanche rating; avalanche current as a function of avalanche time
PSMN1R9-25YLC
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 May 2011
4 of 15
PSMN1R9-25YLC
NXP Semiconductors
N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using
003aaf826
104
ID
(A)
103
102
10
1
Limit RDSon = VDS / ID
tp =10 μs
100 μs
DC
1 ms
10 ms
100 ms
10-1
10-1
1
10
102
VDS (V)
Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
6. Thermal characteristics
Table 6.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from
junction to mounting base
see Figure 5
-
0.92
1.06
K/W
003aaf827
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
10-1
10-2
10-3
0.1
0.05
tp
δ =
0.02
P
T
single shot
t
tp
T
1e-6
10-5
10-4
10-3
10-2
10-1
1
tp (s)
Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN1R9-25YLC
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 May 2011
5 of 15
PSMN1R9-25YLC
NXP Semiconductors
N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using
7. Characteristics
Table 7.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
25
-
-
V
V
V
22.5
1.05
-
-
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C;
1.47
1.95
voltage
see Figure 10; see Figure 11
ID = 10 mA; VDS = VGS; Tj = 150 °C
ID = 1 mA; VDS = VGS; Tj = -55 °C
VDS = 25 V; VGS = 0 V; Tj = 25 °C
VDS = 25 V; VGS = 0 V; Tj = 150 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
0.5
-
-
V
-
-
-
-
-
-
-
2.25
1
V
IDSS
drain leakage current
gate leakage current
-
µA
µA
nA
nA
mΩ
-
100
100
100
2.7
IGSS
-
-
RDSon
drain-source on-state
resistance
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
see Figure 12
2.2
V
GS = 4.5 V; ID = 25 A; Tj = 150 °C;
-
-
-
-
-
4.35
2.05
3.25
1.6
mΩ
mΩ
mΩ
Ω
see Figure 12; see Figure 13
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 12
1.7
-
VGS = 10 V; ID = 25 A; Tj = 150 °C;
see Figure 12; see Figure 13
RG
gate resistance
f = 1 MHz
0.8
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 12 V; VGS = 10 V;
see Figure 14; see Figure 15
-
-
57
27
-
-
nC
nC
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
see Figure 14; see Figure 15
ID = 0 A; VDS = 0 V; VGS = 10 V
-
-
-
55
-
-
-
nC
nC
nC
QGS
gate-source charge
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
see Figure 14; see Figure 15
8.4
5.9
QGS(th)
pre-threshold
gate-source charge
QGS(th-pl)
post-threshold
-
2.5
-
nC
gate-source charge
QGD
gate-drain charge
-
-
7.4
-
-
nC
V
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 12 V; see Figure 14;
see Figure 15
2.45
Ciss
Coss
Crss
input capacitance
output capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 16
-
-
-
3504
761
-
-
-
pF
pF
pF
reverse transfer
capacitance
275
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω
-
-
-
-
27
28
48
21
-
-
-
-
ns
ns
ns
ns
turn-off delay time
fall time
PSMN1R9-25YLC
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 May 2011
6 of 15
PSMN1R9-25YLC
NXP Semiconductors
N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using
Table 7.
Symbol
Qoss
Characteristics …continued
Parameter
Conditions
Min
Typ
Max
Unit
output charge
VGS = 0 V; VDS = 12 V; f = 1 MHz;
Tj = 25 °C
-
16
-
nC
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 17
-
0.8
1.1
V
trr
Qr
ta
reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
-
-
-
34
28
20
-
-
-
ns
nC
ns
VDS = 12 V
recovered charge
reverse recovery rise
time
VGS = 0 V; IS = 25 A; dIS/dt = -100 A/µs;
VDS = 12 V; see Figure 18
tb
reverse recovery fall
time
-
14
-
ns
003aaf 828
003aaf 829
100
ID
(A)
10
RDSon
(mΩ)
10 4.5 3.0
2.8
80
60
40
20
0
8
6
4
2
0
VGS (V) =
2.6
2.4
2.2
0
0.5
1
1.5
2
0
4
8
12
16
VDS (V)
VGS (V)
Fig 6. Output characteristics; drain current as a
function of drain-source voltage; typical values
Fig 7. Drain-source on-state resistance as a function
of gate-source voltage; typical values
PSMN1R9-25YLC
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 May 2011
7 of 15
PSMN1R9-25YLC
NXP Semiconductors
N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using
003aaf 834
003aaf 836
200
100
gfs
ID
(S)
(A)
80
160
120
80
60
40
T = 150 C
T = 25 C
°
°
j
j
40
20
0
0
0
20
40
60
80
100
0
1
2
3
4
VGS (V)
I
D (A)
Fig 8. Forward transconductance as a function of
drain current; typical values
Fig 9. Transfer characteristics; drain current as a
function of gate-source voltage; typical values
003aaf 833
003aaf 832
10-1
3
ID
(A)
10-2
VGS(th)
(V)
Ma x (1 mA)
ID = 5mA
Min
Typ
Ma x
2
1mA
10-3
10-4
10-5
10-6
Min (5 mA)
1
0
0
1
2
3
-60
0
60
120
180
V
GS (V)
T ( C)
°
j
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
Fig 11. Gate-source threshold voltage as a function of
junction temperature
PSMN1R9-25YLC
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 May 2011
8 of 15
PSMN1R9-25YLC
NXP Semiconductors
N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using
003aaf 830
003aaf 831
8
2
2.6
2.8
RDSon
(mΩ)
a
VGS (V)=4.5V
6
1.5
10V
VGS (V) =
3.0
4
2
0
1
0.5
0
3.5
4.5
10
0
20
40
60
80
100
-60
0
60
120
180
I
D (A)
T ( C)
°
j
Fig 12. Drain-source on-state resistance as a function
of drain current; typical values
Fig 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
003aaf 837
10
VGS
(V)
V
DS
8
I
D
6
20V
V
GS(pl)
12V
4
V
GS(th)
VDS = 5V
V
GS
2
0
Q
Q
GS1
GS2
Q
Q
GD
GS
Q
G(tot)
0
20
40
60
003aaa508
Q
G (nC)
Fig 14. Gate charge waveform definitions
Fig 15. Gate-source voltage as a function of gate
charge; typical values
PSMN1R9-25YLC
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 May 2011
9 of 15
PSMN1R9-25YLC
NXP Semiconductors
N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using
003aaf 835
003aaf 838
104
100
IS
(A)
C
(pF)
80
60
40
Cis s
103
Coss
T = 150 C
°
T = 25 C
°
j
j
Crs s
20
0
102
10-1
1
10
102
0
0.3
0.6
0.9
1.2
VSD (V)
VDS (V)
Fig 16. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
Fig 17. Source current as a function of source-drain
voltage; typical values
003aaf 444
ID
(A)
trr
ta
tb
0
0.25 I
RM
IRM
t (s)
Fig 18. Reverse recovery timing definition
PSMN1R9-25YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 May 2011
10 of 15
PSMN1R9-25YLC
NXP Semiconductors
N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using
8. Package outline
Plastic single-ended surface-mounted package (LFPAK; Power-SO8); 4 leads
SOT669
A
2
E
A
C
c
E
b
b
2
1
2
L
3
1
mounting
base
b
4
D
1
D
H
L
2
1
2
3
4
X
e
w
M
c
A
b
1/2 e
A
(A )
3
C
A
1
θ
L
detail X
y
C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
(1)
D
(1)
(1)
1
A
A
A
H
L
L
L
2
w
y
θ
UNIT
A
b
b
b
b
c
c
E
E
1
e
1
2
3
1
2
3
4
2
max
1.20 0.15 1.10
1.01 0.00 0.95
0.50 4.41 2.2 0.9 0.25 0.30 4.10
0.35 3.62 2.0 0.7 0.19 0.24 3.80
5.0 3.3
4.8 3.1
6.2 0.85 1.3 1.3
5.8 0.40 0.8 0.8
8°
0°
mm
0.25
4.20
1.27
0.25 0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
06-03-16
11-03-25
SOT669
MO-235
Fig 19. Package outline SOT669 (LFPAK; Power-SO8)
PSMN1R9-25YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 May 2011
11 of 15
PSMN1R9-25YLC
NXP Semiconductors
N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using
9. Revision history
Table 8.
Revision history
Release date
Document ID
Data sheet status
Change notice
Supersedes
PSMN1R9-25YLC v.1 20110502
Product data sheet
-
-
PSMN1R9-25YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 May 2011
12 of 15
PSMN1R9-25YLC
NXP Semiconductors
N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using
10. Legal information
10.1 Data sheet status
Document status [1] [2]
Product status [3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
Right to make changes — NXP Semiconductors reserves the right to make
10.2 Definitions
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
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applications and products.
10.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
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damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
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testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
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profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
PSMN1R9-25YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 May 2011
13 of 15
PSMN1R9-25YLC
NXP Semiconductors
N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using
Terms and conditions of commercial sale — NXP Semiconductors
In the event that customer uses the product for design-in and use in
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
10.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
non-automotive qualified products in automotive equipment or applications.
11. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PSMN1R9-25YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 May 2011
14 of 15
PSMN1R9-25YLC
NXP Semiconductors
N-channel 25 V 2.05 mΩ logic level MOSFET in LFPAK using
12. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits. . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
Ordering information. . . . . . . . . . . . . . . . . . . . . .2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
Thermal characteristics . . . . . . . . . . . . . . . . . . .5
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . .11
Revision history. . . . . . . . . . . . . . . . . . . . . . . . .12
10
Legal information. . . . . . . . . . . . . . . . . . . . . . . .13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14
10.1
10.2
10.3
10.4
11
Contact information. . . . . . . . . . . . . . . . . . . . . .14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 May 2011
Document identifier: PSMN1R9-25YLC
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