PSMN1R6-30BL_技术文档

PSMN1R6-30BL

AK

D2P

N-channel 30 V 1.9 mΩ logic level MOSFET in D2PAK

Rev. 1 — 22 March 2012

Product data sheet

1. Product profile

1.1 General description

Logic level N-channel MOSFET in D2PAK package qualified to 175 °C. This product is

designed and qualified for use in a wide range of industrial, communications and domestic

equipment.

1.2 Features and benefits

 High efficiency due to low switching

 Suitable for logic level gate drive

and conduction losses

sources

1.3 Applications

 DC-to-DC converters

 Load switching

 Motor control

 Server power supplies

1.4 Quick reference data

Table 1.

Symbol

V_DS

Quick reference data

Parameter

Conditions

Min

Typ

Max

30

Unit

V

drain-source voltage

drain current

T_j≥ 25 °C; T_j≤ 175 °C

-

[1]

I_D

T_mb= 25 °C; V_GS= 10 V;

see Figure 1

100

A

P_tot

T_j

total power dissipation

junction temperature

T_mb= 25 °C; see Figure 2

-

306

175

W

-55

°C

Static characteristics

R_DSon

drain-source on-state resistance V_GS= 10 V; I_D= 25 A; T_j= 100 °C;

see Figure 13; see Figure 6

-

2.21

1.58

2.6

1.9

mΩ

V_GS= 10 V; I_D= 25 A; T_j= 25 °C;

see Figure 6

Dynamic characteristics

Q_GD

gate-drain charge

total gate charge

V_GS= 4.5 V; I_D= 25 A; V_DS= 15 V;

see Figure 14; see Figure 15

-

27

-

nC

Q_G(tot)

101

Avalanche ruggedness

E_DS(AL)Snon-repetitive drain-source

avalanche energy

V_GS= 10 V; T_j(init)= 25 °C;

I_D= 100 A; V_sup≤ 30 V; R_GS= 50 Ω;

unclamped

-

1.7

J

[1] Continuous current is limited by package.

PSMN1R6-30BL

NXP Semiconductors

N-channel 30 V 1.9 mΩ logic level MOSFET in D2PAK

2. Pinning information

Table 2.

Pinning information

Symbol Description

1

Simplified outline

Graphic symbol

G

D

S

D

gate

drain^[1]

mb

D

S

2

3

source

G

mb

mounting base; connected to drain

mbb076

2

1

3

SOT404 (D2PAK)

[1] It is not possible to make connection to pin 2

3. Ordering information

Table 3.

Ordering information

Type number

Package

Name

Description

Version

PSMN1R6-30BL

D2PAK

plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404

(one lead cropped)

4. Marking

Table 4.

Marking codes

Type number

PSMN1R6-30BL

Marking code

PSMN1R6-30BL

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Product data sheet

Rev. 1 — 22 March 2012

2 of 15

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N-channel 30 V 1.9 mΩ logic level MOSFET in D2PAK

5. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DS

Parameter

Conditions

Min

Max

30

Unit

V

drain-source voltage

drain-gate voltage

gate-source voltage

drain current

T_j≥ 25 °C; T_j≤ 175 °C

T_j≥ 25 °C; T_j≤ 175 °C; R_GS= 20 kΩ

-

V_DGR

V_GS

-

30

V

-20

20

V

[1]

I_D

V_GS= 10 V; T_mb= 100 °C; see Figure 1

V_GS= 10 V; T_mb= 25 °C; see Figure 1

-

100

1268

A

I_DM

peak drain current

pulsed; t_p≤ 10 µs; T_mb= 25 °C;

A

see Figure 3

P_tot

T_stg

T_j

total power dissipation

storage temperature

T_mb= 25 °C; see Figure 2

-

306

175

260

W

-55

-

°C

junction temperature

T_sld(M)

peak soldering temperature

Source-drain diode

[1]

I_S

source current

peak source current

T_mb= 25 °C

-

100

A

I_SM

pulsed; t_p≤ 10 µs; T_mb= 25 °C

1268

Avalanche ruggedness

E_DS(AL)Snon-repetitive drain-source

avalanche energy

V_GS= 10 V; T_j(init)= 25 °C; I_D= 100 A;

V_sup≤ 30 V; R_GS= 50 Ω; unclamped

-

1.7

J

[1] Continuous current is limited by package.

003aad003

03aa16

120

400

I_D

P

(%)

der

(A)

300

200

80

40

100

(1)

0

50

100

150

200

0

50

100

150

200

T_mb(°C)

T

(°C)

mb

Fig 1. Continuous drain current as a function of

mounting base temperature

Fig 2. Normalized total power dissipation as a

function of mounting base temperature

PSMN1R6-30BL

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Product data sheet

Rev. 1 — 22 March 2012

3 of 15

PSMN1R6-30BL

NXP Semiconductors

N-channel 30 V 1.9 mΩ logic level MOSFET in D2PAK

003aad115

10⁴

I_D

(A)

Limit R_DSon= V_DS/ I_D

10³

10²

10

t = 10

s

μ

p

100 μs

(1)

1 ms

DC

10

10 ms

100 ms

1

10^-1

1

10²

V_DS(V)

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

PSMN1R6-30BL

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Product data sheet

Rev. 1 — 22 March 2012

4 of 15

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N-channel 30 V 1.9 mΩ logic level MOSFET in D2PAK

6. Thermal characteristics

Table 6.

Symbol

R_th(j-mb)

Thermal characteristics

Parameter

Conditions

Min

Typ

Max

Unit

thermal resistance from junction to see Figure 4

mounting base

-

0.22

0.49

K/W

R_th(j-a)

thermal resistance from junction to minimum footprint; mounted on a

-

50

-

K/W

ambient

printed-circuit board

003aad005

1

Z_th(j-mb)

(K/W)

δ = 0.5

10^-1

10^-2

10^-3

10^-4

0.2

0.1

0.05

0.02

t_p

δ =

P

T

t

t_p

single shot

T

10^-6

10^-5

10^-4

10^-3

10^-2

10^-1

1

t_p(s)

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration; typical

values

PSMN1R6-30BL

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Product data sheet

Rev. 1 — 22 March 2012

5 of 15

PSMN1R6-30BL

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N-channel 30 V 1.9 mΩ logic level MOSFET in D2PAK

7. Characteristics

Table 7.

Tested to JEDEC standards where applicable.

Symbol Parameter Conditions

Static characteristics

V_(BR)DSS

Characteristics

Min

Typ

Max

Unit

drain-source breakdown voltage I_D= 250 µA; V_GS= 0 V; T_j= 25 °C

I_D= 250 µA; V_GS= 0 V; T_j= -55 °C

30

27

1.3

-

V

-

V_GS(th)

gate-source threshold voltage

I_D= 1 mA; V_DS= V_GS; T_j= 25 °C;

see Figure 11; see Figure 12

1.7

2.15

I_D= 1 mA; V_DS= V_GS; T_j= 175 °C;

see Figure 12

0.5

-

V

I_D= 1 mA; V_DS= V_GS; T_j= -55 °C;

see Figure 12

2.45

I_DSS

drain leakage current

gate leakage current

V_DS= 30 V; V_GS= 0 V; T_j= 25 °C

V_DS= 30 V; V_GS= 0 V; T_j= 125 °C

V_GS= 16 V; V_DS= 0 V; T_j= 25 °C

V_GS= -16 V; V_DS= 0 V; T_j= 25 °C

-

5

µA

nA

mΩ

-

150

100

3.5

I_GSS

10

3

R_DSon

drain-source on-state resistance V_GS= 10 V; I_D= 25 A; T_j= 175 °C;

see Figure 13; see Figure 6

V_GS= 4.5 V; I_D= 25 A; T_j= 25 °C;

see Figure 6

-

1.84

2.21

1.58

0.98

2.2

2.6

1.9

-

mΩ

Ω

V_GS= 10 V; I_D= 25 A; T_j= 100 °C;

see Figure 13; see Figure 6

V_GS= 10 V; I_D= 25 A; T_j= 25 °C; see

Figure 6

R_G

gate resistance

f = 1 MHz

Dynamic characteristics

Q_G(tot)

total gate charge

I_D= 25 A; V_DS= 15 V; V_GS= 10 V;

see Figure 14; see Figure 15

-

212

-

nC

I_D= 0 A; V_DS= 0 V; V_GS= 10 V

-

193

101

33

-

nC

I_D= 25 A; V_DS= 15 V; V_GS= 4.5 V;

see Figure 14; see Figure 15

Q_GS

gate-source charge

Q_GS(th)

pre-threshold gate-source

charge

20

Q_GS(th-pl)

post-threshold gate-source

charge

-

13

-

nC

Q_GD

gate-drain charge

-

27

-

nC

V

V_GS(pl)

gate-source plateau voltage

I_D= 25 A; V_DS= 15 V; see Figure 14;

see Figure 15

2.5

C_iss

C_oss

C_rss

input capacitance

V_DS= 15 V; V_GS= 0 V; f = 1 MHz;

T_j= 25 °C; see Figure 16

-

12493

2486

1034

-

pF

output capacitance

reverse transfer capacitance

PSMN1R6-30BL

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Product data sheet

Rev. 1 — 22 March 2012

6 of 15

PSMN1R6-30BL

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N-channel 30 V 1.9 mΩ logic level MOSFET in D2PAK

Table 7.

Characteristics …continued

Tested to JEDEC standards where applicable.

Symbol

Parameter

Conditions

Min

Typ

104

163

174

87

Max

Unit

ns

t_d(on)

t_r

t_d(off)

t_f

turn-on delay time

rise time

V_DS= 15 V; R_L= 0.5 Ω; V_GS= 4.5 V;

R_G(ext)= 4.7 Ω

-

ns

turn-off delay time

fall time

ns

Source-drain diode

V_SD

source-drain voltage

I_S= 25 A; V_GS= 0 V; T_j= 25 °C;

see Figure 17

-

0.77

1.2

V

t_rr

reverse recovery time

recovered charge

I_S= 25 A; dI_S/dt = -100 A/µs;

-

64

79

-

ns

V_GS= 0 V; V_DS= 15 V

Q_r

nC

003aad011

003aad012

300

I_D

10

4.5

3.5

2.8

V_GS(V) = 3

2.6

3

R_DSon

(mΩ)

8

(A)

250

200

150

100

50

6

4

2

0

2.8

2.6

4.5

3.5

10

V_GS(V) = 2.4

0

2

4

6

8

10

_DS(V)

0

100

200

I_D(A)

300

V

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values

Fig 6. Drain-source on-state resistance as a function

of drain current; typical values

PSMN1R6-30BL

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Product data sheet

Rev. 1 — 22 March 2012

7 of 15

PSMN1R6-30BL

NXP Semiconductors

N-channel 30 V 1.9 mΩ logic level MOSFET in D2PAK

003aad018

003aad019

400

10

R_DSon

g_fs

(mΩ)

(S)

8

6

4

2

0

300

200

100

0

20

40

60

80

100

0

5

10

15

20

V

_GS(V)

I_D(A)

Fig 7. Forward transconductance as a function of

drain current; typical values

Fig 8. Drain-source on-state resistance as a function

of gate-source voltage; typical values

003aad017

003aad013

10⁵

100

I_D

(A)

80

C

(pF)

C_iss

T_j= 175 °C

60

25 °C

10⁴

C_rss

40

20

0

10³

10^-1

1

10

10²

0

1

2

3

4

_GS(V)

V_GS(V)

V

Fig 9. Input and reverse transfer capacitances as a

function of gate-source voltage; typical values

Fig 10. Transfer characteristics: drain current as a

function of gate-source voltage; typical values

PSMN1R6-30BL

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Product data sheet

Rev. 1 — 22 March 2012

8 of 15

PSMN1R6-30BL

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N-channel 30 V 1.9 mΩ logic level MOSFET in D2PAK

003aab271

003aac982

10^-1

I_D

3

(A)

10^-2

V_GS(th)

(V)

max

min

typ

max

2

10^-3

typ

min

10^-4

10^-5

10^-6

1

0

-60

0

1

2

V

_GS(V)

3

0

60

120

180

T_j(°C)

Fig 11. Sub-threshold drain current as a function of

gate-source voltage

Fig 12. Gate-source threshold voltage as a function of

junction temperature

03aa27

2

V

DS

a

I

D

1.5

V

GS(pl)

V

GS(th)

GS

1

0.5

0

V

Q

GS1

GS2

Q

GD

GS

Q

G(tot)

003aaa508

−60

0

60

120

180

T ( C)

°

j

Fig 13. Normalized drain-source on-state resistance

factor as a function of junction temperature

Fig 14. Gate charge waveform definitions

PSMN1R6-30BL

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Product data sheet

Rev. 1 — 22 March 2012

9 of 15

PSMN1R6-30BL

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N-channel 30 V 1.9 mΩ logic level MOSFET in D2PAK

003aad015

003aad016

10⁵

10

V_GS

(V)

8

C

(pF)

V_DS= 15 V

C_iss

10⁴

6

4

2

0

C_oss

10³

C_rss

10²

10^-1

1

10

10²

0

40

80

120

160

200

240

_G(nC)

V_DS(V)

Q

Fig 15. Gate-source voltage as a function of gate

charge; typical values

Fig 16. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

003aad014

100

I_S

(A)

80

60

40

20

0

175 °C

T_j= 25 °C

0

0.2

0.4

0.6

0.8

1

V

_SD(V)

Fig 17. Source current as a function of source-drain voltage; typical values

PSMN1R6-30BL

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Product data sheet

Rev. 1 — 22 March 2012

10 of 15

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N-channel 30 V 1.9 mΩ logic level MOSFET in D2PAK

8. Package outline

Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)

SOT404

A

E

1

mounting

base

D

1

D

H

D

2

L

p

1

3

c

b

e

Q

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

D

E

A

b

UNIT

c

D

e

L

H

Q

1

p

D

max.

4.50

4.10

1.40

1.27

0.85

0.60

0.64

0.46

1.60

1.20

10.30

9.70

2.90 15.80 2.60

2.10 14.80 2.20

mm

11

2.54

REFERENCES

JEDEC JEITA

EUROPEAN

PROJECTION

OUTLINE

VERSION

ISSUE DATE

IEC

05-02-11

06-03-16

SOT404

Fig 18. Package outline SOT404 (D2PAK)

PSMN1R6-30BL

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Product data sheet

Rev. 1 — 22 March 2012

11 of 15

PSMN1R6-30BL

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N-channel 30 V 1.9 mΩ logic level MOSFET in D2PAK

9. Revision history

Table 8.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

PSMN1R6-30BL v.1

20120322

Product data sheet

-

PSMN1R6-30BL

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Product data sheet

Rev. 1 — 22 March 2012

12 of 15

PSMN1R6-30BL

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N-channel 30 V 1.9 mΩ logic level MOSFET in D2PAK

10. Legal information

10.1 Data sheet status

Document status^{[1] [2]}

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term 'short data sheet' is explained in section "Definitions".

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URLhttp://www.nxp.com.

Right to make changes — NXP Semiconductors reserves the right to make

10.2 Definitions

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Preview — The document is a preview version only. The document is still

subject to formal approval, which may result in modifications or additions.

NXP Semiconductors does not give any representations or warranties as to

the accuracy or completeness of information included herein and shall have

no liability for the consequences of use of such information.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

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modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

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Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Applications — Applications that are described herein for any of these

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representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

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data sheet shall define the specification of the product as agreed between

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shall an agreement be valid in which the NXP Semiconductors product is

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Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

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Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

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NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

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testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with theTerms and conditions of commercial sale of NXP Semiconductors.

PSMN1R6-30BL

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Product data sheet

Rev. 1 — 22 March 2012

13 of 15

PSMN1R6-30BL

NXP Semiconductors

N-channel 30 V 1.9 mΩ logic level MOSFET in D2PAK

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published athttp://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

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applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

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reenChip,HiPerSmart,HITAG,I²C-bus

logo,ICODE,I-CODE,ITEC,Labelution,MIFARE,MIFARE Plus,MIFARE

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HD Radio andHD Radio logo — are trademarks of iBiquity Digital

Corporation.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

11. Contact information

For more information, please visit:http://www.nxp.com

For sales office addresses, please send an email to:salesaddresses@nxp.com

PSMN1R6-30BL

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 22 March 2012

14 of 15

PSMN1R6-30BL

NXP Semiconductors

N-channel 30 V 1.9 mΩ logic level MOSFET in D2PAK

12. Contents

1

Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1

1.2

1.3

1.4

General description . . . . . . . . . . . . . . . . . . . . . .1

Features and benefits. . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2

3

4

5

6

7

8

9

Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

Ordering information. . . . . . . . . . . . . . . . . . . . . .2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3

Thermal characteristics . . . . . . . . . . . . . . . . . . .5

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .6

Package outline . . . . . . . . . . . . . . . . . . . . . . . . .11

Revision history. . . . . . . . . . . . . . . . . . . . . . . . .12

10

Legal information. . . . . . . . . . . . . . . . . . . . . . . .13

Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14

10.1

10.2

10.3

10.4

11

Contact information. . . . . . . . . . . . . . . . . . . . . .14

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 22 March 2012

Document identifier: PSMN1R6-30BL


型号：	PSMN1R6-30BL
厂家：	NXP
描述：	N-channel 30 V 1.9 mÎ© logic level MOSFET in D2PAK
文件：	总15页 (文件大小：219K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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