PSMN1R6-40YLC [NXP]
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology; N沟道40 V 1.55 MI ©逻辑电平LFPAK采用NextPower技术MOSFET型号: | PSMN1R6-40YLC |
厂家: | NXP |
描述: | N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology |
文件: | 总14页 (文件大小:239K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
22 August 2012
Product data sheet
1. Product profile
1.1 General description
Logic level enhancement mode N-channel MOSFET in LFPAK package. This product
is designed and qualified for use in a wide range of industrial, communications and
domestic equipment.
1.2 Features and benefits
High reliability Power SO8 package, qualified to 150°C
•
•
•
•
Optimised for 4.5V Gate drive utilising NextPower Superjunction technology
Ultra low QG, QGD, & QOSS for high system efficiencies at low and high loads
Ultra low Rdson and low parasitic inductance
1.3 Applications
DC-to-DC converters
Load switching
Power OR-ing
Server power supplies
Sync rectifier
•
•
•
•
•
1.4 Quick reference data
Table 1.
Symbol
Quick reference data
Parameter
Conditions
Min
Typ
Max
40
Unit
V
VDS
ID
drain-source voltage
drain current
25 °C ≤ Tj ≤ 150 °C
Tmb = 25 °C; VGS = 10 V; Fig. 1
-
-
-
-
-
[1]
-
100
288
150
A
Ptot
Tj
total power dissipation Tmb = 25 °C; Fig. 2
junction temperature
-
W
-55
°C
Static characteristics
RDSon drain-source on-state
resistance
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
Fig. 12
-
-
1.45
1.25
1.8
mΩ
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 12
1.55
Dynamic characteristics
QGD gate-drain charge
VGS = 4.5 V; ID = 25 A; VDS = 20 V;
Fig. 14
-
15.3
-
nC
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NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
QG(tot)
total gate charge
VGS = 4.5 V; ID = 25 A; VDS = 20 V;
Fig. 14
-
59
-
nC
[1] Continuous current is limited by package.
2. Pinning information
Table 2.
Pin
Pinning information
Symbol Description
Simplified outline
Graphic symbol
D
S
1
S
S
S
G
D
source
source
source
gate
2
G
3
mbb076
4
mb
mounting base; connected to
drain
1
2
3
4
LFPAK; Power-
SO8 (SOT1023)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PSMN1R6-40YLC
LFPAK;
Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT1023
Power-SO8
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
40
Unit
V
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
25 °C ≤ Tj ≤ 150 °C
-
VDGR
VGS
25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ
-
40
V
-20
20
V
ID
VGS = 10 V; Tmb = 25 °C; Fig. 1
VGS = 10 V; Tmb = 100 °C; Fig. 1
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 4
Tmb = 25 °C; Fig. 2
[1]
[1]
-
100
100
1304
288
150
A
-
A
IDM
Ptot
Tstg
peak drain current
-
A
total power dissipation
storage temperature
-
W
°C
-55
PSMN1R6-40YLC
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Product data sheet
22 August 2012
2 / 14
NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
Symbol
Tj
Parameter
Conditions
Min
-55
-
Max
150
260
-
Unit
°C
junction temperature
peak soldering temperature
Tsld(M)
VESD
Source-drain diode
°C
electrostatic discharge voltage MM (JEDEC JESD22-A115)
1
kV
IS
source current
peak source current
Tmb = 25 °C
[1]
-
-
100
A
A
ISM
pulsed; tp ≤ 10 µs; Tmb = 25 °C
1304
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C; ID = 100 A;
Vsup ≤ 40 V; RGS = 50 Ω; unclamped;
Fig. 3
-
391
mJ
[1] Continuous current is limited by package.
003aag974
003aab937
120
400
I
D
(A)
P
der
(%)
300
80
200
100
0
40
(1)
0
0
50
100
150
200
T
0
50
100
150
200
mb
T
(°C)
mb
°
( C)
Fig. 2. Normalized total power dissipation as a
function of solder point temperature
Fig. 1. Continuous drain current as a function of
mounting base temperature
PSMN1R6-40YLC
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© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
3 / 14
NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
003aag975
103
I
AL
(A)
102
10
1
(1)
(2)
10-3
10-2
10-1
1
10
t
(ms)
AL
Fig. 3. Single pulse avalanche rating; avalanche current as a function of avalanche time
003aag976
104
I
D
(A)
103
Limit RDSon = VDS / ID
tp =10 µs
102
100 µs
1 ms
10
DC
10 ms
100 ms
1
10-1
10-1
1
10
102
V
(V)
DS
Fig. 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
0.43
Unit
Rth(j-mb)
thermal resistance
from junction to
mounting base
Fig. 5
-
0.35
K/W
PSMN1R6-40YLC
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© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
4 / 14
NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
003aag977
1
Z
th(j-mb)
(K/W)
δ = 0.5
10-1
0.2
0.1
0.05
t
p
P
10-2
δ =
T
0.02
single shot
t
t
p
T
10-3
10-6
10-5
10-4
10-3
10-2
10-1
1
t (s)
p
Fig. 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
40
-
-
V
V
V
36
-
-
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C;
1.05
1.46
1.95
voltage
Fig. 10; Fig. 11
ID = 10 mA; VDS = VGS; Tj = 150 °C
ID = 1 mA; VDS = VGS; Tj = -55 °C
VDS = 40 V; VGS = 0 V; Tj = 25 °C
VDS = 40 V; VGS = 0 V; Tj = 150 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
0.5
-
-
V
-
-
-
-
-
-
-
2.25
1
V
IDSS
drain leakage current
gate leakage current
-
µA
µA
nA
nA
mΩ
-
100
100
100
1.8
IGSS
-
-
RDSon
drain-source on-state
resistance
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
Fig. 12
1.45
VGS = 4.5 V; ID = 25 A; Tj = 150 °C;
Fig. 12; Fig. 13
-
-
-
-
-
3.2
mΩ
mΩ
mΩ
Ω
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 12
1.25
-
1.55
2.7
VGS = 10 V; ID = 25 A; Tj = 150 °C;
Fig. 12; Fig. 13
RG
gate resistance
f = 1 MHz
1.17
2.34
PSMN1R6-40YLC
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Product data sheet
22 August 2012
5 / 14
NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 20 V; VGS = 10 V;
Fig. 14; Fig. 15
-
-
126
59
-
-
nC
nC
ID = 25 A; VDS = 20 V; VGS = 4.5 V;
Fig. 14
ID = 0 A; VDS = 0 V; VGS = 10 V
-
-
-
115
-
-
-
nC
nC
nC
QGS
gate-source charge
ID = 25 A; VDS = 20 V; VGS = 4.5 V;
Fig. 14
17.7
12.5
QGS(th)
pre-threshold gate-
source charge
QGS(th-pl)
post-threshold gate-
source charge
-
5.2
-
nC
QGD
gate-drain charge
-
-
15.3
2.4
-
-
nC
V
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 20 V; Fig. 14
Ciss
Coss
Crss
input capacitance
output capacitance
VDS = 20 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; Fig. 16
-
-
-
7790
1063
409
-
-
-
pF
pF
pF
reverse transfer
capacitance
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 20 V; RL = 0.8 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω
-
-
-
-
-
41
-
-
-
-
-
ns
ns
ns
ns
nC
48
turn-off delay time
fall time
86
42
Qoss
output charge
VGS = 0 V; VDS = 20 V; f = 1 MHz;
Tj = 25 °C
38.7
Source-drain diode
VSD source-drain voltage
trr
IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 17
-
-
0.77
44
1.1
-
V
reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 20 V; Fig. 18
ns
Qr
recovered charge
IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 20 V
-
62
-
nC
ta
reverse recovery rise
time
VGS = 0 V; IS = 25 A; dIS/dt = -100 A/µs;
VDS = 20 V; Fig. 18
-
-
26
18
-
-
ns
ns
tb
reverse recovery fall
time
PSMN1R6-40YLC
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Product data sheet
22 August 2012
6 / 14
NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
003aag978
003aag979
100
10
3
2.8
4.5
10
I
R
D
(A)
DSon
(mΩ)
2.6
80
60
40
20
0
8
2.4
6
4
2
0
VGS (V) =
2.2
0
0.25
0.5
0.75
1
0
4
8
12
16
V
(V)
V
(V)
GS
DS
Fig. 6. Output characteristics; drain current as a
function of drain-source voltage; typical values
Fig. 7. Drain-source on-state resistance as a function
of gate-source voltage; typical values
003aag980
003aag981
360
100
g
fs
I
D
(S)
(A)
300
80
240
180
120
60
60
40
20
Tj = 150 °C
°
Tj = 25
C
0
0
0
20
40
60
80
100
0
1
2
3
4
I
(A)
V
(V)
GS
D
Fig. 8. Forward transconductance as a function of
drain current; typical values
Fig. 9. Transfer characteristics; drain current as a
function of gate-source voltage; typical values
PSMN1R6-40YLC
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Product data sheet
22 August 2012
7 / 14
NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
003aag982
003aag983
10-1
3
I
D
V
GS(th)
(V)
(A)
10-2
Max (1mA)
ID = 5mA
2
1
0
Min
Typ
Max
10-3
10-4
10-5
10-6
1mA
Min (5mA)
0
1
2
3
-60
0
60
120
180
V
(V)
T (°C)
j
GS
Fig. 10. Sub-threshold drain current as a function of
gate-source voltage
Fig. 11. Gate-source threshold voltage as a function of
junction temperature
003aag984
003aag985
5
2
2.4
VGS (V) =
R
DSon
a
(mΩ)
4
1.5
2.6
3
2
1
1
0.5
0
2.8
3
3.5
4.5
10
10
30
50
70
90
110
-60
0
60
120
180
I (A)
T (°C)
j
D
Fig. 12. Drain-source on-state resistance as a function Fig. 13. Normalized drain-source on-state resistance
of drain current; typical values factor as a function of junction temperature
PSMN1R6-40YLC
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© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
8 / 14
NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
003aag986
10
V
DS
V
GS
(V)
I
D
8
V
GS(pl)
6
8 V
32 V
V
GS(th)
GS
V
4
VDS = 20 V
Q
GS1
Q
GS2
Q
Q
GD
GS
2
0
Q
G(tot)
003aaa508
Q
Fig. 15. Gate charge waveform definitions
0
30
60
90
120
150
G
(nC)
Fig. 14. Gate-source voltage as a function of gate
charge; typical values
003aag987
003aag988
104
100
Ciss
I
S
C
(A)
(pF)
80
60
40
20
0
103
Coss
Crss
Tj = 150°C
°
Tj = 25
0.9
C
102
10-1
1
10
102
0
0.3
0.6
1.2
V
(V)
V
(V)
SD
DS
Fig. 16. Input, output and reverse transfer capacitances Fig. 17. Source current as a function of source-drain
as a function of drain-source voltage; typical
values
voltage; typical values
PSMN1R6-40YLC
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Product data sheet
22 August 2012
9 / 14
NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
003aaf 444
ID
(A)
trr
ta
tb
0
0.25 I
RM
IRM
t (s)
Fig. 18. Reverse recovery timing definition
PSMN1R6-40YLC
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© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
10 / 14
NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads
SOT1023
E
A
E
A
1
b
(3x)
2
b
c
1
1
mounting
base
D
1
D
H
L
1
2
3
4
b
X
e
w
A
c
C
A
1
θ
L
p
y
C
detail X
0
1
2.5
5 mm
scale
Dimensions
Unit
(1)
(1)
(1)
E
(1)
A
A
b
b
b
c
c
D
D
1
E
e
H
L
L
p
w
y
θ
1
1
2
1
°
max 1.10 0.15 0.50 4.41
nom
min 0.95 0.00 0.35 3.62
0.25 0.30 4.70 4.45 5.30 3.7
6.2 1.3 0.85
5.9 0.8 0.40
8
0
mm
0.85
1.27
0.25 0.1
°
0.19 0.24 4.45
4.95 3.5
Note
1. Plastic or metal protrusions of 0.15 mm per side are not included.
sot1023_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
09-05-26
11-12-09
SOT1023
Fig. 19. Package outline LFPAK; Power-SO8 (SOT1023)
PSMN1R6-40YLC
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© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
11 / 14
NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation -
lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
Product
Definition
status [1][2] status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Preliminary
[short] data
sheet
Qualification This document contains data from the
preliminary specification.
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authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
Product
[short] data
sheet
Production
This document contains the product
specification.
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the Internet at URL http://www.nxp.com.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
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representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
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subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
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applications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
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associated with their applications and products.
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internal review and subject to formal approval, which may result in
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representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
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damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
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and the products or of the application or use by customer’s third party
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with the same product type number(s) and title. A short data sheet is
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detailed and full information. For detailed and full information see the
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data sheet shall define the specification of the product as agreed between
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is deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
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purchase of NXP Semiconductors products by customer.
8.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
PSMN1R6-40YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
12 / 14
NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of non-
automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and
(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
8.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
PSMN1R6-40YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
13 / 14
NXP Semiconductors
PSMN1R6-40YLC
N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using
NextPower technology
9. Contents
1
Product profile ....................................................... 1
1.1
1.2
1.3
1.4
General description .............................................. 1
Features and benefits ...........................................1
Applications ..........................................................1
Quick reference data ............................................ 1
2
3
4
5
6
7
Pinning information ...............................................2
Ordering information .............................................2
Limiting values .......................................................2
Thermal characteristics .........................................4
Characteristics .......................................................5
Package outline ................................................... 11
8
Legal information .................................................12
Data sheet status ............................................... 12
Definitions ...........................................................12
Disclaimers .........................................................12
Trademarks ........................................................ 13
8.1
8.2
8.3
8.4
© NXP B.V. 2012. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 August 2012
PSMN1R6-40YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
22 August 2012
14 / 14
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