PSMN1R5-25YL_技术文档

PSMN1R5-25YL

N-channel TrenchMOS logic level FET

Rev. 01 — 16 June 2009

Product data sheet

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product is designed and qualified for use in

industrial and communications applications.

1.2 Features and benefits

High efficiency due to low switching

Suitable for logic level gate drive

and conduction losses

sources

1.3 Applications

Class-D amplifiers

Motor control

DC-to-DC converters

Server power supplies

1.4 Quick reference data

Table 1.

Quick reference

Symbol Parameter

Conditions

drain-source voltage T_j≥ 25 °C; T_j≤ 150 °C

Min

Typ

Max Unit

V_DS

I_D

-

25

V

A

drain current

T_mb= 25 °C; V_GS= 10 V;

see Figure 1;

[1]

100

P_tot

total power

dissipation

T_mb= 25 °C; see Figure 2

-

109

W

Dynamic characteristics

Q_GD

gate-drain charge

V_GS= 4.5 V; I_D= 10 A;

V_DS= 12 V; see Figure 14;

see Figure 15

-

9.2

36

-

nC

Q_G(tot)

total gate charge

V_GS= 4.5 V; I_D= 10 A;

V_DS= 12 V; see Figure 14;

see Figure 15

Static characteristics

R_DSon

drain-source

on-state resistance

V_GS= 10 V; I_D= 15 A;

T_j= 25 °C

-

1.13 1.5

mΩ

[1] Continuous current is limited by package.

PSMN1R5-25YL

NXP Semiconductors

N-channel TrenchMOS logic level FET

2. Pinning information

Table 2.

Pinning information

1

Symbol Description

Simplified outline

Graphic symbol

S

G

D

source

gate

mb

D

2

3

G

4

mbb076

S

mb

mounting base; connected to

drain

1

2 3 4

SOT669

(LFPAK)

3. Ordering information

Table 3.

Ordering information

Type number

Package

Name

Description

plastic single-ended surface-mounted package (LFPAK); 4 leads

Version

PSMN1R5-25YL

LFPAK

SOT669

4. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DS

Parameter

Conditions

Min

Max

25

Unit

drain-source voltage

drain-gate voltage

gate-source voltage

drain current

T_j≥ 25 °C; T_j≤ 150 °C

T_j≥ 25 °C; T_j≤ 150 °C; R_GS= 20 kΩ

-

V

V_DGR

V_GS

-

25

V

-20

20

V

I_D

V_GS= 10 V; T_mb= 100 °C; see Figure 1

V_GS= 10 V; T_mb= 25 °C; see Figure 1

t_p≤ 10 µs; pulsed; T_mb= 25 °C; see Figure 3

[1]

-

100

815

109

150

A

-

A

I_DM

P_tot

T_stg

T_j

peak drain current

-

A

total power dissipation T_mb= 25 °C; see Figure 2

storage temperature

-

W

°C

-55

junction temperature

Source-drain diode

I_S

source current

peak source current

T_mb= 25 °C;

[1]

-

100

815

A

I_SM

t_p≤ 10 µs; pulsed; T_mb= 25 °C

Avalanche ruggedness

E_DS(AL)S

non-repetitive

V_GS= 10 V; T_j(init)= 25 °C; I_D= 100 A; V_sup≤ 25 V;

-

290

mJ

drain-source avalanche R_GS= 50 Ω; unclamped

energy

[1] Continuous current is limited by package.

PSMN1R5-25YL_1

Product data sheet

Rev. 01 — 16 June 2009

2 of 13

PSMN1R5-25YL

NXP Semiconductors

N-channel TrenchMOS logic level FET

003aac900

03aa15

120

250

I_D

(A)

200

P

(%)

der

80

150

100

(1)

40

50

0

50

100

150

200

0

50

100

150

200

T

_mb(°C)

T

mb

(°C)

Fig 1. Continuous drain current as a function of

mounting base temperature

Fig 2. Normalized total power dissipation as a

function of mounting base temperature

003aac901

10⁴

I_D

(A)

Limit R_DSon= V_DS/ I_D

10³

10 μs

10²

(1)

100 μs

1 ms

10

DC

10 ms

100 ms

1

10^-1

1

10

10²

V_DS(V)

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

PSMN1R5-25YL_1

Product data sheet

Rev. 01 — 16 June 2009

3 of 13

PSMN1R5-25YL

NXP Semiconductors

N-channel TrenchMOS logic level FET

5. Thermal characteristics

Table 5.

Symbol

R_th(j-mb)

Thermal characteristics

Parameter

Conditions

Min

Typ

Max

Unit

thermal resistance from see Figure 4

junction to mounting

base

-

0.5

1.1

K/W

003aac456

10

Z_th(j-mb)

(K/W)

1

10^-1

10^-2

10^-3

δ = 0.5

0.2

0.1

0.05

t

p

P

δ =

T

0.02

single shot

t

p

T

10^-6

10^-5

10^-4

10^-3

10^-2

10^-1

1

t_p(s)

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

PSMN1R5-25YL_1

Product data sheet

Rev. 01 — 16 June 2009

4 of 13

PSMN1R5-25YL

NXP Semiconductors

N-channel TrenchMOS logic level FET

6. Characteristics

Table 6.

Symbol

Characteristics

Parameter

Conditions

Min

Typ

Max

Unit

Static characteristics

V_(BR)DSS

drain-source

breakdown voltage

I_D= 250 µA; V_GS= 0 V; T_j= 25 °C

I_D= 250 µA; V_GS= 0 V; T_j= -55 °C

25

22

1.3

-

V

-

V_GS(th)

gate-source threshold I_D= 1 mA; V_DS= V_GS; T_j= 25 °C;

1.7

2.15

voltage

see Figure 11; see Figure 12

I_D= 1 mA; V_DS= V_GS; T_j= 150 °C;

see Figure 12

0.65

-

V

I_D= 1 mA; V_DS= V_GS; T_j= -55 °C;

see Figure 12

2.45

I_DSS

drain leakage current

gate leakage current

V_DS= 25 V; V_GS= 0 V; T_j= 25 °C

V_DS= 25 V; V_GS= 0 V; T_j= 150 °C

V_GS= 16 V; V_DS= 0 V; T_j= 25 °C

V_GS= -16 V; V_DS= 0 V; T_j= 25 °C

V_GS= 4.5 V; I_D= 15 A; T_j= 25 °C

-

1

µA

nA

-

100

2.2

2.6

I_GSS

-

nA

R_DSon

drain-source on-state

resistance

1.61

-

mΩ

V_GS= 10 V; I_D= 15 A; T_j= 150 °C;

see Figure 13

V_GS= 10 V; I_D= 15 A; T_j= 25 °C

f = 1 MHz

-

1.13

0.77

1.5

-

mΩ

R_G

gate resistance

Ω

Dynamic characteristics

Q_G(tot)

total gate charge

I_D= 10 A; V_DS= 12 V; V_GS= 10 V;

see Figure 14; see Figure 15

-

76

-

nC

I_D= 0 A; V_DS= 0 V; V_GS= 10 V

-

71

36

-

nC

I_D= 10 A; V_DS= 12 V; V_GS= 4.5 V;

see Figure 14; see Figure 15

Q_GS

gate-source charge

I_D= 10 A; V_DS= 12 V; V_GS= 4.5 V;

see Figure 14; see Figure 15

-

12.3

7.8

-

nC

Q_GS(th)

pre-threshold

gate-source charge

Q_GS(th-pl)

post-threshold

-

4.5

-

nC

gate-source charge

Q_GD

gate-drain charge

-

9.2

2.4

-

nC

V

V_GS(pl)

gate-source plateau

voltage

V_DS= 12 V; see Figure 14

C_iss

C_oss

C_rss

input capacitance

output capacitance

V_DS= 12 V; V_GS= 0 V; f = 1 MHz;

T_j= 25 °C; see Figure 16

-

4830

1280

465

-

pF

reverse transfer

capacitance

t_d(on)

t_r

t_d(off)

t_f

turn-on delay time

rise time

V_DS= 12 V; R_L= 0.5 Ω; V_GS= 4.5 V;

R_G(ext)= 4.7 Ω

-

50

97

72

36

-

ns

turn-off delay time

fall time

PSMN1R5-25YL_1

Product data sheet

Rev. 01 — 16 June 2009

5 of 13

PSMN1R5-25YL

NXP Semiconductors

N-channel TrenchMOS logic level FET

Table 6.

Symbol

Characteristics …continued

Parameter

Conditions

Min

Typ

Max

Unit

Source-drain diode

V_SD

source-drain voltage

I_S= 25 A; V_GS= 0 V; T_j= 25 °C;

see Figure 17

-

0.78

1.2

V

t_rr

reverse recovery time

recovered charge

I_S= 20 A; dI_S/dt = -100 A/µs; V_GS= 0 V;

V_DS= 20 V

-

43

50

-

ns

Q_r

nC

[1] Tested to JEDEC standards where applicable.

003aac903

003aac902

80

180

I_D

10

I_D

4

3.6

3.4

(A)

150

(A)

60

40

20

0

3

3.2

120

90

60

30

0

2.8

2.6

T_j= 150 ˚C

25 ˚C

V_GS(V) = 2.4

0

2

4

6

8

10

0

1

2

3

4

_GS(V)

V

V_DS(V)

Fig 5. Transfer characteristics: drain current as a

function of gate-source voltage; typical values

Fig 6. Output characteristics: drain current as a

function of drain-source voltage; typical values

003aac909

003aac910

4

180

g_fs

R_DSon

(S)

150

(mΩ)

3

120

90

60

30

0

V_GS(V) = 3.4

2

4

10

1

0

20

40

60

0

50

100

150

I_D(A)

Fig 7. Forward transconductance as a function of

drain current; typical values

Fig 8. Drain-source on-state resistance as a function

of drain current; typical values

PSMN1R5-25YL_1

Product data sheet

Rev. 01 — 16 June 2009

6 of 13

PSMN1R5-25YL

NXP Semiconductors

N-channel TrenchMOS logic level FET

003aac908

003aac907

12

8000

R_DSon

C_iss

C

(pF)

(mΩ)

10

6000

4000

2000

0

8

6

4

2

0

C_rss

2

4

6

8

10

2

4

6

8

10

V

_GS(V)

V_GS(V)

Fig 9. Drain-source on-state resistance as a function

of gate-source voltage; typical values

Fig 10. Input and reverse transfer capacitances as a

function of gate-source voltage; typical values

003aac337

003aab271

−3

10

3

I

D

V_GS(th)

(V)

(A)

−4

−5

−6

max

10

2

max

min

typ

min

10

1

0

-60

0

0.5

1

1.5

2

2.5

(V)

0

60

120

180

T_j(°C)

V

GS

Fig 11. Sub-threshold drain current as a function of

gate-source voltage

Fig 12. Gate-source threshold voltage as a function of

junction temperature

PSMN1R5-25YL_1

Product data sheet

Rev. 01 — 16 June 2009

7 of 13

PSMN1R5-25YL

NXP Semiconductors

N-channel TrenchMOS logic level FET

03aa27

2

V

DS

a

I

D

1.5

V

GS(pl)

V

GS(th)

1

V

GS

Q

GS1

Q

GS2

0.5

0

Q

GD

GS

Q

G(tot)

003aaa508

Fig 14. Gate charge waveform definitions

-60

0

60

120

180

T ( C)

°

j

Fig 13. Normalized drain-source on-state resistance

factor as a function of junction temperature

003aac904

003aac906

10

6000

V_GS

(V)

C_iss

C

(pF)

8

4000

2000

0

C_oss

6

V_DS= 12 V

V_DS= 19 V

4

C_rss

2

0

40

80

10^-1

1

10

10²

Q

_G(nC)

V_DS(V)

Fig 15. Gate-source voltage as a function of gate

charge; typical values

Fig 16. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

PSMN1R5-25YL_1

Product data sheet

Rev. 01 — 16 June 2009

8 of 13

PSMN1R5-25YL

NXP Semiconductors

N-channel TrenchMOS logic level FET

003aac905

100

I_S

(A)

80

60

40

20

0

T_j= 150 °C

25 °C

0

0.2

0.4

0.6

0.8

1

V

_SD(V)

Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values

PSMN1R5-25YL_1

Product data sheet

Rev. 01 — 16 June 2009

9 of 13

PSMN1R5-25YL

NXP Semiconductors

N-channel TrenchMOS logic level FET

7. Package outline

Plastic single-ended surface-mounted package (LFPAK); 4 leads

SOT669

A

2

E

A

C

c

E

1

b

2

b

3

L

1

mounting

base

b

4

D

1

D

H

L

2

1

2

3

4

X

e

w

M

c

A

b

1/2 e

A

(A )

3

C

A

1

θ

L

detail X

y

C

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

D

(1)

D

(1)

1

A

H

L

2

w

y

θ

UNIT

A

b

c

E

1

e

1

2

3

1

2

3

4

2

max

1.20 0.15 1.10

1.01 0.00 0.95

0.50 4.41 2.2 0.9 0.25 0.30 4.10

0.35 3.62 2.0 0.7 0.19 0.24 3.80

5.0 3.3

4.8 3.1

6.2 0.85 1.3 1.3

5.8 0.40 0.8 0.8

8°

0°

mm

0.25

4.20

1.27

0.25 0.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

04-10-13

06-03-16

SOT669

MO-235

Fig 18. Package outline SOT669 (LFPAK)

PSMN1R5-25YL_1

Product data sheet

Rev. 01 — 16 June 2009

10 of 13

PSMN1R5-25YL

NXP Semiconductors

N-channel TrenchMOS logic level FET

8. Revision history

Table 7.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

PSMN1R5-25YL_1

20090616

Product data sheet

-

PSMN1R5-25YL_1

Product data sheet

Rev. 01 — 16 June 2009

11 of 13

PSMN1R5-25YL

NXP Semiconductors

N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

Document status ^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term 'short data sheet' is explained in section "Definitions".

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URL http://www.nxp.com.

Applications — Applications that are described herein for any of these

9.2 Definitions

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between information in this document and such

terms and conditions, the latter will prevail.

9.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein may

be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

9.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

TrenchMOS — is a trademark of NXP B.V.

10. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PSMN1R5-25YL_1

Product data sheet

Rev. 01 — 16 June 2009

12 of 13

PSMN1R5-25YL

NXP Semiconductors

N-channel TrenchMOS logic level FET

11. Contents

1

Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1

1.2

1.3

1.4

General description . . . . . . . . . . . . . . . . . . . . . .1

Features and benefits. . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2

3

4

5

6

7

8

Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

Ordering information. . . . . . . . . . . . . . . . . . . . . .2

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2

Thermal characteristics . . . . . . . . . . . . . . . . . . .4

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10

Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11

9

Legal information. . . . . . . . . . . . . . . . . . . . . . . .12

Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12

9.1

9.2

9.3

9.4

10

Contact information. . . . . . . . . . . . . . . . . . . . . .12

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 16 June 2009

Document identifier: PSMN1R5-25YL_1


型号：	PSMN1R5-25YL
厂家：	NXP
描述：	N-channel TrenchMOS logic level FET N沟道的TrenchMOS逻辑电平FET 晶体晶体管功率场效应晶体管开关脉冲
文件：	总13页 (文件大小：200K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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