PSMN059-150Y,115 [NXP]
N-channel TrenchMOS SiliconMAX standard level FET SOIC 4-Pin;型号: | PSMN059-150Y,115 |
厂家: | NXP |
描述: | N-channel TrenchMOS SiliconMAX standard level FET SOIC 4-Pin 开关 脉冲 晶体管 |
文件: | 总13页 (文件大小:182K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PSMN059-150Y
AK
LFP
N-channel TrenchMOS SiliconMAX standard level FET
Rev. 03 — 17 March 2011
Product data sheet
1. Product profile
1.1 General description
SiliconMAX standard level N-channel enhancement mode Field-Effect Transistor (FET) in
a plastic package using TrenchMOS technology. This product is designed and qualified for
use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Higher operating power due to low
Suitable for high frequency
applications due to fast switching
characteristics
thermal resistance
1.3 Applications
Class D amplifier
Motion control
DC-to-DC converters
Switched-mode power supplies
1.4 Quick reference data
Table 1.
Symbol
VDS
Quick reference data
Parameter
Conditions
Min Typ Max Unit
drain-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 150 °C
-
-
-
-
150
43
V
A
ID
Tmb = 25 °C; VGS = 10 V;
see Figure 1; see Figure 3
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
-
-
113
59
W
Static characteristics
RDSon drain-source on-state
resistance
VGS = 10 V; ID = 12 A;
Tj = 25 °C; see Figure 9;
see Figure 10
46
mΩ
Dynamic characteristics
QGD gate-drain charge
VGS = 10 V; ID = 12 A;
-
9.1
-
nC
VDS = 75 V; see Figure 11;
see Figure 12
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
2. Pinning information
Table 2.
Pinning information
Symbol Description
Pin
1
Simplified outline
Graphic symbol
S
S
S
G
D
source
mb
D
S
2
source
3
source
G
4
gate
mbb076
mb
mounting base; connected to drain
1
2 3 4
SOT669 (LFPAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PSMN059-150Y
LFPAK
plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
150
150
20
Unit
V
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 150 °C
Tj ≥ 25 °C; Tj ≤ 150 °C; RGS = 20 Ω
-
VDGR
VGS
-
V
-20
-
V
ID
VGS = 10 V; Tmb = 25 °C; see Figure 1;
see Figure 3
43
A
VGS = 10 V; Tmb = 100 °C; see Figure 1
-
-
27.7
129
A
A
IDM
peak drain current
pulsed; tp ≤ 10 µs; Tmb = 25 °C;
see Figure 3
Ptot
Tstg
Tj
total power dissipation
storage temperature
junction temperature
Tmb = 25 °C; see Figure 2
-
113
150
150
W
-55
-55
°C
°C
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
-
-
52
A
A
ISM
pulsed; tp ≤ 10 µs; Tmb = 25 °C
208
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C; ID = 12.1 A;
Vsup ≤ 150 V; unclamped; tp = 0.21 ms;
RGS = 50 Ω
-
255
mJ
PSMN059-150Y
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 03 — 17 March 2011
2 of 13
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
003aac023
003aab937
120
120
I
P
der
der
(%)
(%)
80
80
40
40
0
0
0
50
100
150
200
0
50
100
150
200
T
mb
(°C)
T
mb
(°C)
Fig 1. Normalized continuous drain current as a
function of mounting base temperature
Fig 2. Normalized total power dissipation as a
function of solder point temperature
003aab749
3
10
I
D
Limit R
= V / I
DS D
DSon
(A)
2
10
t
p
= 10 μs
10
100 μs
1 ms
DC
10 ms
1
100 ms
−1
10
2
3
1
10
10
10
V
DS
(V)
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN059-150Y
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 03 — 17 March 2011
3 of 13
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from
junction to mounting base
mounted on a printed-circuit board;
vertical in still air; see Figure 4
-
-
1.1
K/W
003aac268
10
Z
th(j-mb)
(K/W)
1
d = 0.5
0.2
−1 0.1
10
10
10
0.05
t
p
0.02
P
δ =
T
−2
single shot
t
t
p
T
−3
10
−6
−5
−4
−3
−2
−1
10
10
10
10
10
1
t
p
(s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN059-150Y
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 03 — 17 March 2011
4 of 13
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS drain-source breakdown
voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
150
133
2
-
-
V
V
V
-
-
VGS(th)
gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 7; see Figure 8
3
4
ID = 1 mA; VDS = VGS; Tj = 150 °C;
see Figure 7; see Figure 8
1
-
-
-
-
V
V
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 7; see Figure 8
4.4
IDSS
drain leakage current
gate leakage current
VDS = 120 V; VGS = 0 V; Tj = 25 °C
VDS = 120 V; VGS = 0 V; Tj = 150 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
-
-
-
-
-
-
1
µA
µA
nA
nA
mΩ
-
100
100
100
59
IGSS
-
-
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 12 A; Tj = 25 °C;
see Figure 9; see Figure 10
46
VGS = 10 V; ID = 12 A; Tj = 150 °C;
see Figure 9; see Figure 10
-
-
101
1.1
135
-
mΩ
RG
gate resistance
f = 1 MHz
Ω
Dynamic characteristics
QG(tot)
QGS
total gate charge
ID = 12 A; VDS = 75 V; VGS = 10 V;
see Figure 11; see Figure 12
-
-
-
-
27.9
6.3
9.1
-
-
-
-
nC
nC
nC
V
gate-source charge
QGD
gate-drain charge
VGS(pl)
gate-source plateau voltage
ID = 12 A; VDS = 75 V; see Figure 11;
see Figure 12
4.8
Ciss
Coss
Crss
td(on)
tr
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
VDS = 30 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 13
-
-
-
-
-
-
-
1529
208
66
-
-
-
-
-
-
-
pF
pF
pF
ns
ns
ns
ns
VDS = 75 V; RL = 3 Ω; VGS = 10 V;
RG(ext) = 5.6 Ω
14.2
42
td(off)
tf
turn-off delay time
fall time
54.2
11.1
Source-drain diode
VSD source-drain voltage
IS = 12 A; VGS = 0 V; Tj = 25 °C;
see Figure 14
-
-
-
0.9
1.2
V
trr
reverse recovery time
recovered charge
IS = 12 A; dIS/dt = -100 A/µs;
VGS = 0 V; VDS = 30 V
114
175
-
-
ns
nC
Qr
IS = 12 A; dIS/dt = -100 A/µs;
VGS = 0 V
PSMN059-150Y
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 03 — 17 March 2011
5 of 13
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
003aab751
003aab753
50
60
V
DS
> I × R
D
DSon
10
7
6
I
D
I
D
(A)
(A)
40
45
V
GS
(V) = 5.5
30
20
10
0
30
15
0
T = 150 °C
25 °C
j
5
4.5
0
1
2
3
4
5
0
2
4
6
8
V
(V)
V
(V)
DS
GS
Tj = 25 °C
Tj = 25 °C and 150 °C; VDS > ID x RDSon
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
003aab852
003aab853
−1
5
10
I
V
D
GS(th)
(V)
(A)
min
typ
max
−2
−3
−4
−5
−6
4
10
10
10
10
10
max
3
typ
2
min
1
0
−60
0
60
120
160
0
2
4
6
T (°C)
j
V
GS
(V)
Fig 7. Gate-source threshold voltage as a function of
junction temperature
Fig 8. Sub-threshold drain current as a function of
gate-source voltage
PSMN059-150Y
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 03 — 17 March 2011
6 of 13
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
03al51
003aab752
3
150
4.5
5
5.5
R
DSon
(mΩ)
a
120
V
(V) = 6
2
1
0
GS
90
60
30
0
7
10
−75
−25
25
75
125
175
0
10
20
30
40
50
T (°C)
j
I (A)
D
Fig 9. Normalized drain-source on-state resistance
factor as a function of junction temperature
Fig 10. Drain-source on-state resistance as a function
of drain current; typical values
003aab754
10
V
DS
I
= 12 A
V
(V)
D
GS
T = 25 °C
j
I
D
8
6
4
2
0
30
75
V
GS(pl)
V
GS(th)
V
DS
= 120 V
V
GS
Q
Q
GS1
GS2
Q
Q
GD
GS
Q
G(tot)
003aaa508
0
7.5
15
22.5
30
Q
G
(nC)
Fig 11. Gate charge waveform definitions
Fig 12. Gate-source voltage as a function of gate
charge; typical values
PSMN059-150Y
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 03 — 17 March 2011
7 of 13
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
003aab755
003aab756
4
10
80
I
S
C
(pF)
(X)
60
C
iss
3
10
40
20
0
T = 25 °C
150 °C
j
C
C
oss
2
10
rss
10
10
−1
2
1
10
10
0
0.3
0.6
0.9
1.2
V
DS
(V)
V
(V)
SD
Fig 13. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
Fig 14. Source current as a function of source-drain
voltage; typical values
PSMN059-150Y
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 03 — 17 March 2011
8 of 13
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads
SOT669
A
2
E
A
C
c
E
b
b
2
1
2
L
3
1
mounting
base
b
4
D
1
D
H
L
2
1
2
3
4
X
e
w
M
c
A
b
1/2 e
A
(A )
3
C
A
1
θ
L
detail X
y
C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
(1)
D
(1)
(1)
1
A
A
A
H
L
L
L
2
w
y
θ
UNIT
A
b
b
b
b
c
c
E
E
1
e
1
2
3
1
2
3
4
2
max
1.20 0.15 1.10
1.01 0.00 0.95
0.50 4.41 2.2 0.9 0.25 0.30 4.10
0.35 3.62 2.0 0.7 0.19 0.24 3.80
5.0 3.3
4.8 3.1
6.2 0.85 1.3 1.3
5.8 0.40 0.8 0.8
8°
0°
mm
0.25
4.20
1.27
0.25 0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
04-10-13
06-03-16
SOT669
MO-235
Fig 15. Package outline SOT669 (LFPAK)
PSMN059-150Y
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 03 — 17 March 2011
9 of 13
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PSMN059-150Y v.3
Modifications:
20110317
Product data sheet
-
PSMN059-150Y v.2
• Various changes to content.
20101220 Product data sheet
PSMN059-150Y v.2
-
PSMN059-150Y v.1
PSMN059-150Y
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 03 — 17 March 2011
10 of 13
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
9. Legal information
9.1 Data sheet status
Document status [1] [2]
Product status [3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
9.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
9.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
PSMN059-150Y
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 03 — 17 March 2011
11 of 13
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
non-automotive qualified products in automotive equipment or applications.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PSMN059-150Y
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 03 — 17 March 2011
12 of 13
PSMN059-150Y
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1
1.2
1.3
1.4
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits. . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
Ordering information. . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . .11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
9.1
9.2
9.3
9.4
10
Contact information. . . . . . . . . . . . . . . . . . . . . .12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 March 2011
Document identifier: PSMN059-150Y
相关型号:
PSMN063-150D/T3
TRANSISTOR 29 A, 150 V, 0.063 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252AA, PLASTIC, SC-63, TO-252, DPAK-3, FET General Purpose Power
NXP
PSMN069-100YS,115
PSMN069-100YS - N-channel LFPAK 100 V 72.4 mΩ standard level MOSFET SOIC 4-Pin
NXP
©2020 ICPDF网 联系我们和版权申明