PM908E625ACDWBR2_技术文档

Freescale Semiconductor, Inc.

MOTOROLA

Document order number: MM908E625

Rev 3.0, 09/2004

SEMICONDUCTOR TECHNICAL DATA

Advance Information

908E625

Integrated Quad Half H-Bridge with

Power Supply, Embedded MCU, and

LIN Serial Communication

The 908E625 is an integrated single-package solution that includes a high-

performance HC08 microcontroller with a SMARTMOS^TManalog control IC.

The HC08 includes flash memory, a timer, enhanced serial communications

interface (ESCI), an analog-to-digital converter (ADC), serial peripheral

interface (SPI), and an internal clock generator (ICG) module. The analog

control die provides fully protected H-Bridge/high-side outputs, voltage

regulator, autonomous watchdog with cyclic wake-up, and local interconnect

network (LIN) physical layer.

H-BRIDGE POWER SUPPLY

WITH EMBEDDED MCU AND LIN

The single-package solution, together with LIN, provides optimal

application performance adjustments and space-saving PCB design. It is well

suited for the control of automotive mirror, door lock, and light-levelling

applications.

DWB SUFFIX

CASE 1400-01

54-TERMINAL SOICWB-EP

Features

• High-Performance M68HC08EY16 Core

• 16 K Bytes of On-Chip Flash Memory

• 512 Bytes of RAM

• Internal Clock Generation Module

• Two 16-Bit, 2-Channel Timers

• 10-Bit Analog-to-Digital Converter

• Three 2-Terminal Hall-Effect Sensor Input Ports

• One Analog Input with Switchable Current Source

• Four Low R_DS(ON)Half-Bridge Outputs

ORDERING INFORMATION

Temperature

Package

Device

Range (T )

A

54 SOIC

WB-EP

MM908E625ACDWB/R2 -40°C to 85°C

• One Low R_DS(ON)High-Side Output

• 13 Microcontroller I/Os

908E625_SS_imi_pm_lifiep_dl_Ai_pf_pie_licd_atioA_{n D}p_iap_grl_ai_mcation Diagram

908E625

LIN

HB1

VSUP[1:3]

VREFH

VDDA

EVDD

VDD

4 Half-Bridges

Controlling 3 Loads

M

HB2

HB3

HB4

VREFL

VSSA

EVSS

VSS

HS

High-Side

Output

RST

Switchable Internal

RST_A

IRQ

HVDD

V

Output

DD

IRQ_A

SS

PTB1/AD1

RXD

H1

H2

H3

Three

2-Terminal Hall-Effect

Sensor Inputs

Analog Input with

Current Source

PTE1/RXD

PTD1/TACH1

FGEN

PA1

Port A I/Os

Port B I/Os

Port C I/Os

Microcontroller

Ports

BEMF

PTD0/TACH0/BEMF GND[1:2] EP

This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

For More Information On This Product,

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Figure 1. 908E625 Simplified Internal Block Diagram

GND1-2

VSUP1-3

RST_A

IRQ_A

BEMF

FGEN

LIN

RXD

SS

PTE1/RXD

PTD1/TACH1

PTD0/TACH0

PTB1/AD1

RST

C T

P O R

D T

P O R

E T

P O R

D D R C

D D R D

D D R E

IRQ

VREFL

VSSA

I n t e r n a l B u s

D D R A

P O R

D D R B

P O R

A T

B T

EVSS

EVDD

VDDA

VREFH

908E625

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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Transparent Top

View of Package

PTB7/AD7/TBCH1

PTB6/AD6/TBCH0

PTC4/OSC1

PTC3/OSC2

PTC2/MCLK

PTB5/AD5

PTB4/AD4

PTB3/AD3

IRQ

1

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

PTA0/KBD0

PTA1/KBD1

PTA2/KBD2

FLSVPP

PTA3/KBD3

PTA4/KBD4

VREFH

VDDA

EVDD

EVSS

2

3

4

5

6

7

8

9

RST

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

PTB1/AD1

PTD0/TACH0/BEMF

PTD1/TACH1

NC

VSSA

VREFL

PTE1/RXD

RXD

VSS

PA1

VDD

H1

H2

H3

HVDD

NC

HB4

VSUP3

GND2

HB3

Exposed

Pad

FGEN

BEMF

RST_A

IRQ_A

SS

LIN

NC

HB1

VSUP1

GND1

HB2

VSUP2

HS

TERMINAL DEFINITIONS

A functional description of each terminal can be found in the System/Application Information section beginning on page 15.

Die

Terminal

Terminal Name

Formal Name

Definition

MCU

1

2

6

PTB7/AD7/TBCH1

PTB6/AD6/TBCH0

PTB5/AD5

Port B I/Os

These terminals are special-function, bidirectional I/O port terminals that

are shared with other functional modules in the MCU.

7

PTB4/AD4

8

PTB3/AD3

11

PTB1/AD1

MCU

3

4

5

PTC4/OSC1

PTC3/OSC2

PTC2/MCLK

Port C I/Os

These terminals are special-function, bidirectional I/O port terminals that

are shared with other functional modules in the MCU.

MCU

9

External Interrupt

Input

IRQ

This terminal is an asynchronous external interrupt input terminal.

10

External Reset

RST

This terminal is bidirectional, allowing a reset of the entire system. It is

driven low when any internal reset source is asserted.

MCU

12

13

PTD0/TACH0/BEMF

PTD1/TACH1

Port D I/Os

These terminals are special-function, bidirectional I/O port terminals that

are shared with other functional modules in the MCU.

–

14, 21, 22,

33

NC

No Connect

Port E I/O

Not connected.

MCU

42

PTE1/RXD

This terminal is a special-function, bidirectional I/O port terminal that can

is shared with other functional modules in the MCU.

MCU

43

48

VREFL

VREFH

ADC References

These terminals are the reference voltage terminals for the analog-to-

digital converter (ADC).

44

47

VSSA

VDDA

ADC Supply

Terminals

These terminals are the power supply terminals for the analog-to-digital

converter.

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TERMINAL DEFINITIONS (continued)

A functional description of each terminal can be found in the System/Application Information section beginning on page 15.

Die

Terminal

Terminal Name

Formal Name

Definition

MCU

45

46

EVSS

EVDD

MCU Power Supply

Terminals

These terminals are the ground and power supply terminals, respectively.

The MCU operates from a single power supply.

MCU

49

50

52

53

54

PTA4/KBD4

PTA3/KBD3

PTA2/KBD2

PTA1/KBD1

PTA0/KBD0

Port A I/Os

These terminals are special-function, bidirectional I/O port terminals that

are shared with other functional modules in the MCU.

MCU

51

15

FLSVPP

FGEN

Test Terminal

For test purposes only. Do not connect in the application.

Analog

Current Limitation

Frequency Input

This is the input terminal for the half-bridge current limitation and the high-

side inrush current limiter PWM frequency.

Analog

16

BEMF

Back Electromagnetic This terminal gives the user information about back electromagnetic force

Force Output

(BEMF).

Analog

17

18

Internal Reset

RST_A

IRQ_A

This terminal is the bidirectional reset terminal of the analog die.

Internal Interrupt

Output

This terminal is the interrupt output terminal of the analog die indicating

errors or wake-up events.

Analog

19

20

Slave Select

LIN Bus

This terminal is the SPI slave select terminal for the analog chip.

This terminal represents the single-wire bus transmitter and receiver.

SS

LIN

23

26

29

32

HB1

HB2

HB3

HB4

Half-Bridge Outputs

This device includes power MOSFETs configured as four half-bridge

driver outputs. These outputs may be configured for step motor drivers,

DC motor drivers, or as high-side and low-side switches.

Analog

24

27

31

VSUP1

VSUP2

VSUP3

Power Supply

Terminals

These terminals are device power supply terminals.

25

30

GND1

GND2

Power Ground

Terminals

These terminals are device power ground connections.

This output terminal is a low R_DS(ON)high-side switch.

Analog

28

34

HS

High-Side Output

HVDD

Switchable V_DD

Output

This terminal is a switchable V_DDoutput for driving resistive loads

requiring a regulated 5.0 V supply; e.g., 3-terminal Hall-effect sensors.

Analog

35

36

37

H3

H2

H1

Hall-Effect Sensor

Inputs

These terminals provide inputs for Hall-effect sensors and switches.

38

VDD

Voltage Regulator

Output

The +5.0 V voltage regulator output terminal is intended to supply the

embedded microcontroller.

Analog

39

40

PA1

VSS

Analog Input

This terminal is an analog input port with selectable source values.

Voltage Regulator

Ground

Ground terminal for the connection of all non-power ground connections

(microcontroller and sensors).

Analog

–

41

RXD

LIN Transceiver

Output

This terminal is the output of LIN transceiver.

EP

Exposed Pad

The exposed pad terminal on the bottom side of the package conducts

heat from the chip to the PCB board.

908E625

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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MAXIMUM RATINGS

All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to

the device.

Rating

Symbol

Value

Unit

ELECTRICAL RATINGS

Supply Voltage

V

-0.3 to 28

-0.3 to 40

-0.3 to 6.0

SUP(

)

SS

Analog Chip Supply Voltage under Normal Operation (Steady-State)

Analog Chip Supply Voltage under Transient Conditions (Note 1)

Microcontroller Chip Supply Voltage

V

SUP(PK)

V

DD

Input Terminal Voltage

Analog Chip

V

-0.3 to 5.5

IN(ANALOG)

Microcontroller Chip

V

-0.3 to V +0.3

DD

V

SS

IN(MCU)

Maximum Microcontroller Current per Terminal

All Terminals Except VDD, VSS, PTA0:PTA6, PTC0:PTC1

Terminals PTA0:PTA6, PTC0:PTC1

mA

I

±15

±25

(1)

PIN(2)

Maximum Microcontroller V_SSOutput Current

Maximum Microcontroller V_DDInput Current

I

100

mA

V

MVSS

I

MVDD

LIN Supply Voltage

Normal Operation (Steady-State)

Transient Conditions (Note 1)

V

-18 to 28

40

BUS(SS)

V

BUS(DYNAMIC)

ESD Voltage

V

±3000

±150

±500

ESD1

Human Body Model (Note 2)

Machine Model (Note 3)

Charge Device Model (Note 4)

V

ESD2

ESD3

V

THERMAL RATINGS

Storage Temperature

T

-40 to 150

-40 to 85

°C

STG

Operating Case Temperature (Note 5)

T

C

Operating Junction Temperature

T

J(ANALOG)

Analog

MCU

-40 to 150

-40 to 125

T

J(MCU)

Terminal Soldering Temperature (Note 6)

T

245

°C

SOLDER

Thermal Resistance (Junction to Ambient)

All Outputs ON (Note 7), (Note 9)

°C/W

R

24

27

θJA1

Single Output ON (Note 8), (Note 9)

R

θJA2

Notes

1. Transient capability for pulses with a time of t < 0.5 sec.

2. ESD1 testing is performed in accordance with the Human Body Model (C

= 100 pF, R

= 1500 Ω).

ZAP

3. ESD2 testing is performed in accordance with the Machine Model (C

=200 pF, R

= 0 Ω).

ZAP

4. ESD3 testing is performed in accordance with Charge Device Model, robotic (C

=4.0 pF).

ZAP

5. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking.

6. Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

7. All outputs ON and dissipating equal power.

8. One output ON and dissipating power.

9. Per JEDEC JESD51-2 at natural convection, still air condition; and 2s2p thermal test board per JEDEC JESD51-7 and JESD51-5 (thermal

vias connected to top ground plane).

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STATIC ELECTRICAL CHARACTERISTICS

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip.

Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values noted reflect

the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SUPPLY VOLTAGE

Nominal Operating Voltage

V

8.0

–

18

V

SUP

SUPPLY CURRENT

NORMAL Mode

I

mA

RUN

V

= 12 V, Power Die ON (PSON=1), MCU Operating Using Internal

SUP

–

20

–

Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC Enabled

STOP Mode (Note 10)

µA

I

STOP

60

V

= 12 V, Cyclic Wake-Up Disabled

SUP

DIGITAL INTERFACE RATINGS (ANALOG DIE)

V

Output Terminals RST_A, IRQ_A

V_OL

V_OH

–

0.4

–

Low-State Output Voltage (I_OUT= -1.5 mA)

High-State Output Voltage (I_OUT= 1.0 µA)

3.85

Output Terminals BEMF, RXD

Low-State Output Voltage (I_OUT= -1.5 mA)

High-State Output Voltage (I_OUT= 1.5 mA)

V_OL

V_OH

–

0.4

–

3.85

Output Terminal RXD–Capacitance (Note 11)

C_IN

–

4.0

–

pF

V

Input Terminals RST_A, FGEN, SS

Input Logic Low Voltage

V_IL

V_IH

–

1.5

–

3.5

Input Logic High Voltage

Input Terminals RST_A, FGEN, SS–Capacitance (Note 11)

Terminals RST_A, IRQ_A–Pullup Resistor

Terminal SS–Pullup Resistor

C_IN

–

4.0

10

60

35

–

pF

kΩ

µA

R

PULLUP1

PULLUP2

Terminals FGEN, MOSI, SPSCK–Pulldown Resistor

Terminal TXD–Pullup Current Source

Notes

R

PULLDOWN

I

PULLUP

10. STOP mode current will increase if V

exceeds 15 V.

SUP

11. This parameter is guaranteed by process monitoring but is not production tested.

908E625

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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STATIC ELECTRICAL CHARACTERISTICS (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip.

Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values noted reflect

the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SYSTEM RESETS AND INTERRUPTS

High-Voltage Reset

Threshold

V

27

–

30

33

–

HVRON

Hysteresis

1.5

V

HVRH

Low-Voltage Reset

Threshold

3.6

–

4.0

4.5

–

V

LVRON

Hysteresis

100

mV

V

LVRH

High-Voltage Interrupt

Threshold

V

17.5

–

21

23

–

HVION

Hysteresis

1.0

V

HVIH

Low-Voltage Interrupt

Threshold

V

6.5

–

8.0

–

LVION

Hysteresis

0.4

V

LVIH

High-Temperature Reset (Note 12)

Threshold

°C

T

–

170

–

RON

Hysteresis

5.0

T

RH

High-Temperature Interrupt (Note 13)

Threshold

Hysteresis

T

–

160

–

ION

5.0

T

IH

VOLTAGE REGULATOR

Normal Mode Output Voltage

V

mV

V

DDRUN

I

_OUT= 60 mA, 6.0 V < V

< 18 V

4.75

5.0

5.25

SUP

Load Regulation

I_OUT= 80 mA, V

V

LR

–

100

4.9

= 9.0 V, T_J= 125°C

SUP

STOP Mode Output Voltage (Maximum Output Current 100 µA)

V

4.5

4.7

DDSTOP

Notes

12. This parameter is guaranteed by process monitoring but is not production tested.

13. High-Temperature Interrupt (HTI) threshold is linked to High-Temperature Reset (HTR) threshold (HTR = HTI + 10°C).

908E625

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STATIC ELECTRICAL CHARACTERISTICS (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip.

Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values noted reflect

the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

V

LIN PHYSICAL LAYER

Output Low Level

V

LIN-LOW

LIN-HIGH

TXD LOW, 500 Ω Pullup to V

–

1.4

SUP

Output High Level

V

TXD HIGH, I

= 1.0 µA

V_SUP-1.0

20

–

OUT

Pullup Resistor to V_SUP

R

30

60

kΩ

µA

SLAVE

Leakage Current to GND

I

BUS_PAS_rec

Recessive State (-0.5 V < V_LIN< V_SUP

)

0

–

20

Leakage Current to GND (V_SUPDisconnected)

Including Internal Pullup Resistor, V_LIN@ -18 V

Including Internal Pullup Resistor, V_LIN@ +18 V

µA

I

–

-600

25

–

BUS_NO_GND

I

BUS

LIN Receiver

Recessive

V

0.6 V

LIN

–

V_SUP

IH

Dominant

V

IL

0.4 V_LIN

0

–

V

/2

Threshold

SUP

V

–

ITH

Input Hysteresis

0.01 V

SUP

–

0.1 V_SUP

V

IHY

LIN Wake-Up Threshold

V

–

/2

–

V

WTH

SUP

HIGH-SIDE OUTPUT (HS)

R

–

600

–

700

7.0

mΩ

Switch ON Resistance @ T_J= 25°C with I_LOAD= 1.0 A

DS(ON)HS

High-Side Overcurrent Shutdown

I

3.9

A

HSOC

908E625

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STATIC ELECTRICAL CHARACTERISTICS (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip.

Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values noted reflect

the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

HALF-BRIDGE OUTPUTS (H1:H4)

mΩ

Switch ON Resistance @ T_J= 25°C with I_LOAD= 1.0 A

R

–

425

400

500

High Side

Low Side

DS(ON)HB_HS

R

DS(ON)HB_LS

High-Side Overcurrent Shutdown

Low-Side Overcurrent Shutdown

Low-Side Current Limitation @ T_J= 25°C

4.0

3.5

–

7.5

I

A

HBHSOC

I

HBLSOC

mA

I

–

55

–

CL1

Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1)

Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0)

Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1)

Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0)

Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1)

I

210

300

450

600

260

370

550

740

315

440

650

880

CL2

I

CL3

I

CL4

CL5

Half-Bridge Output HIGH Threshold for BEMF Detection

Half-Bridge Output LOW Threshold for BEMF Detection

Hysteresis for BEMF Detection

V

–

-30

-60

30

0

-5.0

–

V

BEMFH

V

mV

V/A

BEMFL

V

BEMFHY

Low-Side Current-to-Voltage Ratio (V

[V]/I [A])

HB

ADOUT

RATIO

7.0

1.0

12.0

2.0

14.0

3.0

H

CSA = 1

CSA = 0

RATIO

L

SWITCHABLE V_DDOUTPUT (HVDD)

Overcurrent Shutdown Threshold

I

24

30

40

mA

–

HVDDOCT

V_SUPDOWN-SCALER

Voltage Ratio (RATIO_VSUP= V_SUP/V_ADOUT

)

RATIO_VSUP

4.8

5.1

5.35

INTERNAL DIE TEMPERATURE SENSOR

Voltage/Temperature Slope

S

–

19

–

mV/°C

V

TtoV

Output Voltage @ 25°C

V

1.7

2.1

2.5

T25

HALL-EFFECT SENSOR INPUTS (H1:H3)

Output Voltage

V

< 16.2 V

> 16.2 V

V

–

V

_SUP-1.2

SUP

HALL1

HALL2

15

–

Sense Current

Threshold

mA

I

6.9

–

8.8

11

–

HSCT

0.88

Hysteresis

I

HSCH

Output Current Limitation

–

90

3.0

0.5

–

mA

V

I

HL

Overcurrent Warning HP_OCF Flag Threshold]

V_HPOCT

Dropout Voltage @ I

= 15 mA

V

LOAD

HPDO

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STATIC ELECTRICAL CHARACTERISTICS (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip.

Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values noted reflect

the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

ANALOG INPUT (PA1)

Current Source PA1

µA

I_CSPA1

CSSEL1 = 1, CSSEL0 = 1

570

670

770

Selectable Scaling Factor Current Source PA1 (I(N) = I_CSPA1* N)

%

N_CSPA1-0

N_CSPA1-1

N_CSPA1-2

8.5

10

30

60

11.5

31.5

61.5

CSSEL1 = 0, CSSEL0 = 0

CSSEL1 = 0, CSSEL0 = 1

CSSEL1 = 1, CSSEL0 = 0

28.5

58.5

908E625

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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DYNAMIC ELECTRICAL CHARACTERISTICS

All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the microcontroller

chip. Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values noted

reflect the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

LIN PHYSICAL LAYER

Propagation Delay (Note 14), (Note 15)

TXD LOW to LIN LOW

TXD HIGH to LIN HIGH

LIN LOW to RXD LOW

LIN HIGH to RXD HIGH

TXD Symmetry

µs

t

–

6.0

8.0

2.0

TXD-LIN-low

t

TXD-LIN-high

t

–

4.0

–

LIN-RXD-low

LIN-RXD-high

–

t

-2.0

t

TXD-SYM

RXD-SYM

–

RXD Symmetry

Output Falling Edge Slew Rate (Note 14), (Note 16)

80% to 20%

SR

V/µs

F

-1.0

-2.0

-3.0

Output Rising Edge Slew Rate (Note 14), (Note 16)

SR

R

20% to 80%, R_BUS> 1.0 kΩ, C_BUS< 10 nF

1.0

2.0

–

3.0

2.0

LIN Rise/Fall Slew Rate Symmetry (Note 14), (Note 16)

SR

-2.0

µs

S

HALL-EFFECT SENSOR INPUTS (H1:H3)

Propagation Delay

t

–

1.0

–

HPPD

AUTONOMOUS WATCHDOG (AWD)

AWD Oscillator Period

t

–

16

8.0

–

40

22

11

90

–

28

14

–

µs

ms

µs

OSC

AWD Period Low = 512 t_OSC

AWD Period High = 256 t_OSC

AWD Cyclic Wake-Up On Time

Notes

t

AWDPH

AWDPL

t

AWDHPON

14. All LIN characteristics are for initial LIN slew rate selection (20 kBaud) (SRS0:SRS1= 00).

15. See Figure 2, page 11.

16. See Figure 3, page 11.

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.

MICROCONTROLLER

For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.

Module

Description

Core

Timer

Flash

RAM

ADC

SPI

High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz

Two 16-Bit Timers with Two Channels (TIM A and TIM B)

16 K Bytes

512 Bytes

10-Bit Analog-to-Digital Converter

SPI Module

ESCI

Standard Serial Communication Interface (SCI) Module

Bit-Time Measurement

Arbitration

Prescaler with Fine Baud-Rate Adjustment

ICG

Internal Clock Generation Module (25% Accuracy with Trim Capability to 2%)

BEMF Counter

Special Counter for SMARTMOS BEMF Output

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Timing Diagrams

t

TXD-LIN-low

TXD-LIN-high

Tx-LIN-high

Tx-LIN-low

TXD

Tx

TXD

LIN

0.9 V

0.9 VSUP

Recessive State

SUP

0.6 V

0.6 VSUP

SUP

0.4 VSUP

0.4 V

SUP

0.1 V

SUP

0.1 VSUP

Dominant State

Rx

RXD

t

_Lt_IN_LI_-_N_R_-_X_R_D_x_-_-_l_l_o_o_w_w

t_LIN-RXD-high

LIN-Rx-high

Figure 2. LIN Timing Description

∆t Fall-time

∆t Rise-time

0.8 V

0.8 VSUP

SUP

00..88VVSUP

SUP

∆V Fall

∆V Rise

0.2 V

0.2 VSUP

SUP

0.2 V

0.2 VSUP

SUP

Dominant State

∆V Fall

∆V Rise

∆t Rise-time

SR_F=

SR_R=

∆t Fall-time

Figure 3. LIN Slew Rate Description

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Functional Diagrams

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

T = 25°C

J

0.0

0.5

1.0

1.5

2.0

2.5

Amperes

3.0

3.5

4.0

4.5

5.0

Amperes

H-Bridge Low Side

Figure 4. Free Wheel Diode Forward Voltage

250

200

150

100

50

T = 125°C

A

T = 25°C

A

T = -40°C

A

0

55.0

10

15

20

25

I

(mA)

Load

I_LOAD(mA)

Figure 5. Dropout Voltage on HVDD

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SYSTEM/APPLICATION INFORMATION

INTRODUCTION

The 908E625 device was designed and developed as a

high-side switch. Other ports are also provided; they include

Hall-effect sensor input ports, analog input ports, and a

selectable HVDD terminal. An internal voltage regulator is

provided on the SMARTMOS IC chip, which provides power to

the MCU chip.

highly integrated and cost-effective solution for automotive and

industrial applications. For automotive body electronics, the

908E625 is well suited to perform complete mirror, door lock,

and light-levelling control all via a 3-wire LIN bus.

This device combines an standard HC08 MCU core

(68HC908EY16) with flash memory together with a

SMARTMOS IC chip. The SMARTMOS IC chip combines

power and control in one chip. Power switches are provided on

the SMARTMOS IC configured as half-bridge outputs with one

Also included in this device is a LIN physical layer, which

communicates using a single wire. This enables the device to

be compatible with 3-wire bus systems, where one wire is used

for communication, one for battery, and the third for ground.

FUNCTIONAL TERMINAL DESCRIPTION

See Figure 1, 908E625 Simplified Internal Block Diagram,

page 2, for a graphic representation of the various terminals

referred to in the following paragraphs. Also, see the terminal

diagram on page 3 for a depiction of the terminal locations on

the package.

Port D I/O Terminals

PTD1/TACH1 and PTD0/TACH0/BEMF are special-

function, bidirectional I/O port terminals that can also be

programmed to be timer terminals.

In step motor applications the PTD0 terminal should be

connected to the BEMF output of the analog die in order to

evaluate the BEMF signal with a special BEMF module of the

MCU.

Port A I/O Terminals

These terminals are special-function, bidirectional I/O port

terminals that are shared with other functional modules in the

MCU. PTA0:PTA4 are shared with the keyboard interrupt

terminals, KBD0:KBD4.

PTD1 terminal is recommended for use as an output terminal

for generating the FGEN signal (PWM signal) if required by the

application.

The PTA5/SPSCK terminal is not accessible in this device

and is internally connected to the SPI clock terminal of the

analog die. The PTA6/SS terminal is likewise not accessible.

Port E I/O Terminal

PTE1/RXD and PTE0/TXD are special-function,

bidirectional I/O port terminals that can also be programmed to

be enhanced serial communication.

For details refer to the 68HC908EY16 datasheet.

Port B I/O Terminals

PTE0/TXD is internally connected to the TXD terminal of the

analog die. The connection for the receiver must be done

externally.

These terminals are special-function, bidirectional I/O port

terminals that are shared with other functional modules in the

MCU. All terminals are shared with the ADC module. The

PTB6:PTB7 terminals are also shared with the Timer B module.

External Interrupt Terminal (IRQ)

PTB0/AD0 is internally connected to the ADOUT terminal of

the analog die, allowing diagnostic measurements to be

The IRQ terminal is an asynchronous external interrupt

terminal. This terminal contains an internal pullup resistor that

is always activated, even when the IRQ terminal is pulled LOW.

calculated; e.g., current recopy, V

, etc. The PTB2/AD2

SUP

terminal is not accessible in this device.

For details refer to the 68HC908EY16 datasheet.

External Reset Terminal (RST)

Port C I/O Terminals

A logic [0] on the RST terminal forces the MCU to a known

startup state. RST is bidirectional, allowing a reset of the entire

system. It is driven LOW when any internal reset source is

asserted.

These terminals are special-function, bidirectional I/O port

terminals that are shared with other functional modules in the

MCU. For example, PTC2:PTC4 are shared with the ICG

module.

This terminal contains an internal pullup resistor that is

always activated, even when the reset terminal is pulled LOW.

PTC0/MISO and PTC1/MOSI are not accessible in this

device and are internally connected to the MISO and MOSI SPI

terminals of the analog die.

For details refer to the 68HC908EY16 datasheet.

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All VSUP terminals must be connected to get full chip

functionality.

Current Limitation Frequency Input Terminal (FGEN)

Input terminal for the half-bridge current limitation and the

high-side inrush current limiter PWM frequency. This input is

not a real PWM input terminal; it should just supply the period

of the PWM. The duty cycle will be generate automatically.

Power Ground Terminals (GND1 and GND2)

GND1 and GND2 are device power ground connections.

Owing to the low ON-resistance and current requirements of the

half-bridge driver outputs and high-side output driver, multiple

terminals are provided.

Important The recommended FGEN frequency should be

in the range of 0.1 kHz to 20 kHz.

GND1 and GND2 terminals must be connected to get full

chip functionality.

Back Electromagnetic Force Output Terminal (BEMF)

This terminal gives the user information about back

electromagnetic force (BEMF). This feature is mainly used in

step motor applications for detecting a stalled motor. In order to

evaluate this signal the terminal must be directly connected to

terminal PTD0/TACH0/BEMF.

High-Side Output Terminal (HS)

The HS output terminal is a low R_DS(ON)high-side switch. The

switch is protected against overtemperature and overcurrent.

The output is capable of limiting the inrush current with an

automatic PWM generation using the FGEN module.

Reset Terminal (RST_A)

RST_A is the bidirectional reset terminal of the analog die. It

is an open drain with pullup resistor and must be connected to

the RST terminal of the MCU.

Switchable V_DDOutput Terminal (HVDD)

The HVDD terminal is a switchable V_DDoutput for driving

resistive loads requiring a regulated 5.0 V supply; e.g.,

3-terminal Hall-effect sensors. The output is short-circuit

protected.

Interrupt Terminal (IRQ_A)

IRQ_A is the interrupt output terminal of the analog die

indicating errors or wake-up events. It is an open drain with

pullup resistor and must be connected to the IRQ terminal of the

MCU.

Hall-Effect Sensor Input Terminals (H1:H3)

The Hall-effect sensor input terminals H1:H3 provide inputs

for Hall-effect sensors and switches.

Slave Select Terminal (SS)

+5.0 V Voltage Regulator Output Terminal (VDD)

This terminal is the SPI Slave Select terminal for the analog

chip. All other SPI connections are done internally. SS must be

connected to PTB1 or any other logic I/O of the microcontroller.

The VDD terminal is needed to place an external capacitor to

stabilize the regulated output voltage. The VDD terminal is

intended to supply the embedded microcontroller.

LIN Bus Terminal (LIN)

Important The VDD terminal should not be used to supply

other loads; use the HVDD terminal for this purpose. The VDD,

EVDD, VDDA, and VREFH terminals must be connected

together.

The LIN terminal represents the single-wire bus transmitter

and receiver. It is suited for automotive bus systems and is

based on the LIN bus specification.

Analog Input Terminal (PA1)

Half-Bridge Output Terminals (HB1:HB4)

This terminal is an analog input port with selectable current

source values.

The 908E625 device includes power MOSFETs configured

as four half-bridge driver outputs. The HB1:HB4 outputs may

be configured for step motor drivers, DC motor drivers, or as

high-side and low-side switches.

Voltage Regulator Ground Terminal (VSS)

The HB1:HB4 outputs are short-circuit and overtemperature

protected, and they feature current recopy, current limitation,

and BEMF generation. Current limitation and recopy are done

on the low-side MOSFETs.

The VSS terminal is the ground terminal for the connection

of all non-power ground connections (microcontroller and

sensors).

Important VSS, EVSS, VSSA, and VREFL terminals must

be connected together.

Power Supply Terminals (VSUP1:VSUP3)

VSUP1:VSUP3 are device power supply terminals. The

nominal input voltage is designed for operation from 12 V

systems. Owing to the low ON-resistance and current

requirements of the half-bridge driver outputs and high-side

output driver, multiple VSUP terminals are provided.

LIN Transceiver Output Terminal (RXD)

This terminal is the output of LIN transceiver. The terminal

must be connected to the microcontroller’s Enhanced Serial

Communications Interface (ESCI) module (RXD terminal).

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ADC Reference Terminals (VREFL and VREFH)

MCU Power Supply Terminals (EVDD and EVSS)

VREFL and VREFH are the reference voltage terminals for

the ADC. It is recommended that a high-quality ceramic

decoupling capacitor be placed between these terminals.

EVDD and EVSS are the power supply and ground

terminals. The MCU operates from a single power supply.

Fast signal transitions on MCU terminals place high, short-

duration current demands on the power supply. To prevent

noise problems, take special care to provide power supply

bypassing at the MCU.

Important VREFH is the high reference supply for the ADC

and should be tied to the same potential as VDDA via separate

traces. VREFL is the low reference supply for the ADC and

should be tied to the same potential as VSS via separate traces.

For details refer to the 68HC908EY16 datasheet.

Test Terminal (FLSVPP)

ADC Supply Terminals (VDDA and VSSA)

For test purposes only. Do not connect in the application.

VDDA and VSSA are the power supply terminals for the

analog-to-digital converter (ADC). It is recommended that a

high-quality ceramic decoupling capacitor be placed between

these terminals.

Exposed Pad Terminal

The exposed pad terminal on the bottom side of the package

conducts heat from the chip to the PCB board. For thermal

performance the pad must be soldered to the PCB board. It is

recommended that the pad be connected to the ground

potential.

Important VDDA is the supply for the ADC and should be

tied to the same potential as EVDD via separate traces. VSSA

is the ground terminal for the ADC and should be tied to the

same potential as EVSS via separate traces.

For details refer to the 68HC908EY16 datasheet.

ANALOG DIE DESCRIPTION

High-Temperature Interrupt

Interrupts

The High-Temperature Interrupt (HTI) is generated by the

on-chip temperature sensors. If the chip temperature is above

the HTI threshold, the HTI flag will be set. If the High-

The 908E625 has seven different interrupt sources as

described in the following paragraphs. The interrupts can be

disabled or enabled via the SPI. After reset all interrupts are

automatically disabled.

Temperature Interrupt is enabled, an interrupt will be initiated.

During STOP mode the HTI circuitry is disabled.

Low-Voltage Interrupt

Autonomous Watchdog Interrupt (AWD)

The Low-Voltage Interrupt (LVI) is related to the external

supply voltage, V

. If this voltage falls below the LVI

SUP

Refer to Autonomous Watchdog (AWD) on page 36.

threshold, it will set the LVI flag. If the low-voltage interrupt is

enabled, an interrupt will be initiated.

LIN Interrupt

With LVI the H-Bridges (high-side MOSFET only) and the

high-side driver are switched off. All other modules are not

influenced by this interrupt.

If the LINIE bit is set, a falling edge on the LIN terminal will

generate an interrupt. During STOP mode this interrupt will

initiate a system wake-up.

During STOP mode the LVI circuitry is disabled.

Hall-Effect Sensor Input Terminal Interrupt

High-Voltage Interrupt

If the PHIE bit is set, the enabled Hall-effect sensor input

terminals H1:H3 can generate an interrupt if a current above

the threshold is detected. During STOP mode this interrupt,

combined with the cyclic wake-up feature of the AWD, can

wake up the system (refer to Hall-Effect Sensor Input Terminals

(H1:H3) on page 25).

The High-Voltage Interrupt (HVI) is related to the external

supply voltage, V

. If this voltage rises above the HVI

SUP

threshold, it will set the HVI flag. If the High-Voltage Interrupt is

enabled, an interrupt will be initiated.

With HVI the H-Bridges (high-side MOSFET only) and the

high-side driver are switched off. All other modules are not

influenced by this interrupt.

Overcurrent Interrupt

If an overcurrent condition on a half-bridge occurs, the high-

side or the HVDD output is detected and the OCIE bit is set and

an interrupt generated.

During STOP mode the HVI circuitry is disabled.

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Interrupt Flag Register (IFR)

System Wake-Up

System wake-up can be initiated by any of four events:

Register Name and Address: IFR - $05

• A falling edge on the LIN terminal.

• A wake-up signal from the AWD.

• A logic [1] at Hall-effect sensor input terminal during cyclic

check via AWD.

Bit7

6

HPF

0

5

LINF

0

4

HTF

0

3

LVF

0

2

HVF

0

1

Bit0

0

Read

Write

Reset

OCF

0

• An LVR condition.

0

If one of these wake-up events occurs and the interrupt mask

bit for this event is set, the interrupt will wake up the

microcontroller as well as the main voltage regulator (MREG)

(Figure 6).

HPF—Hall-Effect Sensor Input Terminal Flag Bit

This read/write flag is set depending on RUN/STOP mode.

RUN Mode An interrupt will be generated when a state

change on any enabled Hall-effect sensor input terminal is

detected. Clear HPF by writing a logic [1] to HPF. Reset clears

the HPF bit. Writing a logic [0] to HPF has no effect.

MCU Die

Analog Die

From Reset

• 1 = State change on the hallflags detected.

• 0 = No state change on the hallflags detected.

STOP Mode An interrupt will be generated when AWDCC is

set and a current above the threshold is detected on any

enabled Hall-effect sensor input terminal. Clear HPF by writing

a logic [1] to HPF. Reset clears the HPF bit. Writing a logic [0]

to HPF has no effect.

Initialize

Operate

• 1 = One or more of the selected Hall-effect sensor input

terminals had been pulled HIGH.

• 0 = None of the selected Hall-effect sensor input terminals

has been pulled HIGH.

SPI:

GS =1

(MREG off)

STOP MREG

LINF—LIN Flag Bit

This read/write flag is set on the falling edge at the LIN data

line. Clear LINF by writing a logic [1] to LINF. Reset clears the

LINF bit. Writing a logic [0] to LINF has no effect.

Wait for Action

LIN

STOP

AWD

Hallport

• 1 = Falling edge on LIN data line has occurred.

• 0 = Falling edge on LIN data line has not occurred since

last clear.

HTF—High-Temperature Flag Bit

IRQ

Interrupt?

Assert IRQ_A

This read/write flag is set on a high-temperature condition.

Clear HTF by writing a logic [1] to HTF. If a high-temperature

condition is still present while writing a logic [1] to HTF, the

writing has no effect. Therefore, a high-temperature interrupt

cannot be lost due to inadvertent clearing of HTF. Reset clears

the HTF bit. Writing a logic [0] to HTF has no effect.

SPI: Reason for

Interrupt

Start

MREG

• 1 = High-temperature condition has occurred.

• 0 = High-temperature condition has not occurred.

Operate

MREG = Main Voltage

Regulator

Figure 6. STOP Mode/Wake-Up Procedure

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LVF—Low-Voltage Flag Bit

Interrupt Mask Register (IMR)

This read/write flag is set on a low-voltage condition. Clear

LVF by writing a logic [1] to LVF. If a low-voltage condition is still

present while writing a logic [1] to LVF, the writing has no effect.

Therefore, a low-voltage interrupt cannot be lost due to

inadvertent clearing of LVF. Reset clears the LVF bit. Writing a

logic [0] to LVF has no effect.

Register Name and Address: IMR - $04

Bit7

6

HPIE

0

5

LINIE

0

4

HTIE

0

3

LVIE

0

2

HVIE

0

1

OCIE

0

Bit0

0

Read

Write

Reset

0

• 1 = Low-voltage condition has occurred.

• 0 = Low-voltage condition has not occurred.

HPIE—Hall-Effect Sensor Input Terminal Interrupt Enable

Bit

HVF—High-Voltage Flag Bit

This read/write bit enables CPU interrupts by the Hall-effect

sensor input terminal flag, HPF. Reset clears the HPIE bit.

This read/write flag is set on a high-voltage condition. Clear

HVF by writing a logic [1] to HVF. If high-voltage condition is still

present while writing a logic [1] to HVF, the writing has no effect.

Therefore, a high-voltage interrupt cannot be lost due to

inadvertent clearing of HVF. Reset clears the HVF bit. Writing a

logic [0] to HVF has no effect.

• 1 = Interrupt requests from HPF flag enabled.

• 0 = Interrupt requests from HPF flag disabled.

LINIE—LIN Line Interrupt Enable Bit

• 1 = High-voltage condition has occurred.

• 0 = High-voltage condition has not occurred.

This read/write bit enables CPU interrupts by the LIN flag,

LINF. Reset clears the LINIE bit.

• 1 = Interrupt requests from LINF flag enabled.

• 0 = Interrupt requests from LINF flag disabled.

OCF—Overcurrent Flag Bit

This read-only flag is set on an overcurrent condition. Reset

clears the OCF bit. To clear this flag, write a logic [1] to the

appropriate overcurrent flag in the SYSSTAT Register. See

Figure 7, which shows the three signals triggering the OCF.

HTIE—High-Temperature Interrupt Enable Bit

This read/write bit enables CPU interrupts by the high-

temperature flag, HTF. Reset clears the HTIE bit.

• 1 = High-current condition has occurred.

• 0 = High-current condition has not occurred.

• 1 = Interrupt requests from HTF flag enabled.

• 0 = Interrupt requests from HTF flag disabled.

HVDD_OCF

LVIE—Low-Voltage Interrupt Enable Bit

HS_OCF

HB_OCF

OCF

This read/write bit enables CPU interrupts by the low-

voltage flag, LVF. Reset clears the LVIE bit.

• 1 = Interrupt requests from LVF flag enabled.

• 0 = Interrupt requests from LVF flag disabled.

Figure 7. Principal Implementation for OCF

HVIE—High-Voltage Interrupt Enable Bit

This read/write bit enables CPU interrupts by the high-

voltage flag, HVF. Reset clears the HVIE bit.

• 1 = Interrupt requests from HVF flag enabled.

• 0 = Interrupt requests from HVF flag disabled.

OCIE—Overcurrent Interrupt Enable Bit

This read/write bit enables CPU interrupts by the overcurrent

flag, OCF. Reset clears the OCIE bit.

• 1 = Interrupt requests from OCF flag enabled.

• 0 = Interrupt requests from OCF flag disabled.

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Reset

The 908E625 chip has four internal reset sources and one

external reset source, as explained in the paragraphs below.

Figure 8 depicts the internal reset sources.

SPI REGISTERS

AWDRE Flag

HVRE Flag

AWD Reset

Sensor

VDD

High-Voltage

Reset Sensor

HTRE Flag

High-Temperature

Reset Sensor

RST_A

MONO

FLOP

Low-Voltage Reset

Figure 8. Internal Reset Routing

Reset Internal Sources

Autonomous Watchdog

Reset External Source

External Reset Terminal

AWD modules generates a reset because of a timeout

(watchdog function).

The microcontroller has the capability of resetting the

SMARTMOS device by pulling down the RST terminal.

High-Temperature Reset

Reset Mask Register (RMR)

To prevent damage to the device, a reset will be initiated if

the temperature rises above a certain value. The reset is

maskable with bit HTRE in the Reset Mask Register. After a

reset the high-temperature reset is disabled.

Register Name and Address: RMR - $06

Bit7

TTEST

0

6

0

5

0

4

0

3

0

2

0

1

Bit0

Read

Write

Reset

HVRE HTRE

Low-Voltage Reset

0

The LVR is related to the internal V . In case the voltage

DD

falls below a certain threshold, it will pull down the RST_A

terminal.

TTEST—High-Temperature Reset Test

This read/write bit is for test purposes only. It decreases the

overtemperature shutdown limit for final test. Reset clears the

HTRE bit.

High-Voltage Reset

The HVR is related to the external V

voltage. In case the

SUP

• 1 = Low-temperature threshold enabled.

• 0 = Low-temperature threshold disabled.

voltage is above a certain threshold, it will pull down the RST_A

terminal. The reset is maskable with bit HVRE in the Reset

Mask Register. After a reset the high-voltage reset is disabled.

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HVRE—High-Voltage Reset Enable Bit

HTRE—High-Temperature Reset Enable Bit

This read/write bit enables resets on high-voltage

conditions. Reset clears the HVRE bit.

This read/write bit enables resets on high-temperature

conditions. Reset clears the HTRE bit.

1 = High-voltage reset enabled.

0 = High-voltage reset disabled.

• 1 = High-temperature reset enabled.

• 0 = High-temperature reset disabled.

SERIAL PERIPHERAL INTERFACE

The serial peripheral interface (SPI) creates the

communication link between the microcontroller and the

908E625.

A complete data transfer via the SPI consists of 2 bytes. The

master sends address and data, slave system status, and data

of the selected address.

The interface consists of four terminals (see Figure 9):

•

SS—Slave Select

• MOSI—Master-Out Slave-In

• MISO—Master-In Slave-Out

• SPSCK—Serial Clock

SS

Read/Write, Address, Parity

Data (Register write)

R/W

A4

S6

A3

A2

A1

A0

P

X

D7

D6

D5

D4

D3

D2

D1

D0

MOSI

MISO

System Status Register

Data (Register read)

S7

S5

S4

S3

S2

S1

S0

D5

D4

D3

D2

SPSCK

Rising edge of SPSCK

Change MISO/MOSI

Output

Falling edge of SPSCK

Sample MISO/MOSI

Input

Slave latch

register address

Slave latch

data

Figure 9. SPI Protocol

During the inactive phase of SS, the new data transfer is

prepared. The falling edge on the SS line indicates the start of

a new data transfer and puts MISO in the low-impedance mode.

The first valid data are moved to MISO with the rising edge of

SPSCK.

data transfer is only valid if exactly 16 sample clock edges are

present in the active phase of SS.

After a write operation, the transmitted data is latched into

the register by the rising edge of SS. Register read data is

internally latched into the SPI at the time when the parity bit is

transferred. SS HIGH forces MISO to high impedance.

The MISO output changes data on a rising edge of SPSCK.

The MOSI input is sampled on a falling edge of SPSCK. The

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Bit X

Master Address Byte

Not used.

A4:A0

Master Data Byte

Contains the address of the desired register.

Contains data to be written or no valid data during a read

operation.

R/W

Contains information about a read or a write operation.

Slave Status Byte

• If R/W = 1, the second byte of master contains no valid

information, slave just transmits back register data.

• If R/W = 0, the master sends data to be written in the

second byte, slave sends concurrently contents of

selected register prior to write operation, write data is

latched in the SMARTMOS register on rising edge of SS.

Contains the contents of the System Status Register ($0c)

independent of whether it is a write or read operation or which

register was selected.

Slave Data Byte

Contains the contents of selected register. During a write

operation it includes the register content prior to a write

operation.

Parity P

The parity bit is equal to “0” if the number of 1 bits is an even

number contained within R/W, A4:A0. If the number of 1 bits is

odd, P equals “1”. For example, if R/W = 1, A4:A0 = 00001,

then P equals “0.”

SPI Register Overview

Table 1 summarizes the SPI Register addresses and the bit

names of each register.

The parity bit is only evaluated during a write operation.

Table 1. List of Registers

Bit

Addr

$01

$02

$03

$04

$05

$06

$07

Register Name

R/W

7

6

5

HB3_H

0

4

HB3_L

0

3

HB2_H

0

2

1

0

R

W

R

H-Bridge Output

(HBOUT)

HB4_H

HB4_L

HB2_L

HB1_H

HB1_L

H-Bridge Control

(HBCTL)

OFC_EN

CSA

SRS1

HPIE

CLS2

0

CLS1

0

CLS0

W

R

0

GS

0

System Control

(SYSCTL)

PSON

SRS0

LINIE

W

R

Interrupt Mask

(IMR)

0

HTIE

LVIE

HVIE

OCIE

OCF

W

R

0

Interrupt Flag

(IFR)

HPF

0

LINF

0

HTF

0

LVF

0

HVF

0

W

R

Reset Mask

(RMR)

TTEST

0

HVRE

SS1

HTRE

SS0

W

R

0

Analog Multiplexer

Configuration (ADMUX)

SS3

0

SS2

W

R

Hall-Effect Sensor Input

Terminal Control

(HACTL)

0

$08

$09

H3EN

H3F

H2EN

H2F

H1EN

H1F

W

R

Hall-Effect Sensor Input

Terminal Status

(HASTAT)

0

W

R

W

R

0

AWD Control

(AWDCTL)

$0a

$0b

$0c

AWDRE

CSSEL0

AWDIE

AWDCC

AWDF

AWDR

AWDRST

Power Output

(POUT)

CSSEL1

CSEN1

LVF

CSEN0

HVF

HVDDON

HB_OCF

HS_ON

HTF

W

R

LINCL

System Status

(SYSSTAT)

HP_OCF

HVDD_OCF HS_OCF

W

908E625

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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Analog Multiplexer/ADOUT Terminal

Analog Die I/Os

LIN Physical Layer

The ADOUT terminal is the analog output interface to the

ADC of the MCU (see Figure 1, page 2). An analog multiplexer

is used to read seven internal diagnostic analog voltages.

The LIN bus terminal provides a physical layer for single-wire

communication in automotive applications. The LIN physical

layer is designed to meet the LIN physical layer specification.

Current Recopy

The analog multiplexer is connected to the four low-side

current sense circuits of the half-bridges. These sense circuits

offer a voltage proportional to the current through the low-side

MOSFET. High or low resolution is selectable: 5.0 V/2.5 A or

5.0 V/500 mA, respectively. (Refer to Half-Bridge Current

Recopy on page 31.)

The LIN driver is a low-side MOSFET with internal current

limitation and thermal shutdown. An internal pullup resistor with

a serial diode structure is integrated, so no external pullup

components are required for the application in a slave node.

The fall time from dominant to recessive and the rise time from

recessive to dominant is controlled. The symmetry between

both slew rate controls is guaranteed.

Analog Input PA1

The LIN terminal offers high susceptibility immunity level

from external disturbance, guaranteeing communication during

external disturbance.

The analog input PA1 is directly connected to the analog

multiplexer, permitting analog values from the periphery to be

read.

The LIN transmitter circuitry is enabled by setting the PSON

bit in the System Control Register (SYSCTL). If the transmitter

works in the current limitation region, the LINCL bit in the

System Status Register (SYSSTAT) is set. Due to excessive

power dissipation in the transmitter, software is advised to

monitor this bit and turn the transmitter off immediately.

Temperature Sensor

The 908E625 includes an on-chip temperature sensor. This

sensor offers a voltage that is proportional to the actual chip

junction temperature.

TXD Terminal

V_SUPPrescaler

The TXD terminal is the MCU interface to control the state of

the LIN transmitter (see Figure 1, page 2). When TXD is LOW,

LIN output is low (dominant state). When TXD is HIGH, the LIN

output MOSFET is turned off. The TXD terminal has an internal

pullup current source in order to set the LIN bus in recessive

state in the event, for instance, the microcontroller could not

control it during system power-up or power-down.

The V prescaler permits the reading or measurement of

SUP

the external supply voltage. The output of this voltage is V_SUP

RATIO_VSUP

/

.

The different internal diagnostic analog voltages can be

selected with the ADMUX Register.

Analog Multiplexer Configuration Register (ADMUX)

Register Name and Address: ADMUX - $07

RXD Terminal

The RXD transceiver terminal is the MCU interface, which

reports the state of the LIN bus voltage. LIN HIGH (recessive

state) is reported by a high level on RXD, LIN LOW (dominant

state) by a low level on RXD.

Bit7

0

6

0

5

0

4

0

3

SS3

0

2

SS2

0

1

SS1

0

Bit0

SS0

0

Read

Write

Reset

STOP Mode/Wake-Up Feature

0

During STOP mode operation the transmitter of the physical

layer is disabled. The receiver terminal is still active and able to

detect wake-up events on the LIN bus line.

SS3, SS2, SS1, and SS0—A/D Input Select Bits

These read/write bits select the input to the ADC in the

microcontroller according to Table 2, page 24. Reset clears

SS3, SS2, SS1, and SS0 bits.

If LIN interrupt is enabled (LINIE bit in the Interrupt Mask

Register is set), a falling edge on the LIN line causes an

interrupt. This interrupt switches on the main voltage regulator

and generates a system wake-up.

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Table 2. Analog Multiplexer Configuration Register

Analog Input PA1

The Analog input PA1 terminal provides an input for reading

analog signals and is internally connected to the analog

multiplexer. It can be used for reading switches, potentiometers

or resistor values, etc.

SS3

0

SS2

0

SS1

0

SS0

0

Channel

Current Recopy HB1

Current Recopy HB2

Current Recopy HB3

Current Recopy HB4

V_SUPPrescaler

0

1

0

1

0

Analog Input PA1 Current Source

0

1

The analog input PA1 has an additional selectable current

source. It enables the reading of switches, NTC, etc., without

the need of an additional supply line for the sensor (Figure 10).

With this feature it is also possible to read multiple switches on

one input.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Temperature Sensor

Not Used

PA1 Terminal

Current source is enabled if the PSON bit in the System

Control Register (SYSCTL) and the CSEN bit in the Power

Output Register (POUT) is set.

Four different current source values can be selected with the

CSSELx bits (Table 3). This function ceases during STOP

mode operation.

Not Used

Table 3. PA1 Current Source Level Selection Bits

CSSEL1

CSSEL0

Current Source Enable (typ.)

0

1

0

1

0

1

10%

30%

60%

100%

Source Selection Bits

SSx

VDD

3

Selectable

Current

CSSEL

Source

PSON

CSEN

Analog

Multiplexer

ADOUT

PA1

Analog Input PA1

NTC

Figure 10. Analog Input PA1 and Multiplexer6

908E625

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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Power Output Register (POUT)

Hall-Effect Sensor Input Terminals (H1:H3)

Register Name and Address: POUT - $0b

Function

The Hall-effect sensor input terminals provide three inputs

for two-terminal Hall-effect sensors for detecting stall and

position or reading Hall-effect sensor contact switches. The

Hall-effect sensor input terminals are not influenced by the

PSON bit in the System Control Register.

Bit7

0

6

0

5

4

3

2

1

Bit0

Read

Write

Reset

Notes

0

CSSEL1 CSSEL0 CSEN

HVDDON HS_ON

(Note 17)

0

Each terminal of the Hall-effect sensor can be enabled by

setting the HxEN bit in the Hall-Effect Sensor Input Terminal

Control Register (HACTL). If the terminals are enabled, the

Hall-effect sensors are supplied with V_SUPvoltage and the

17. This bit must always be set to 0.

CSSEL0:CSSEL1—Current Source Select Bits

sense circuitry is working. An internal clamp circuity limits the

supply voltage to the sensor to 15 V. This sense circuitry

monitors the current to VSS. The result of this sense operation

is given by the HxF flags in the Hall-Effect Sensor Input

Terminal Status Register (HASTAT).

This read/write bit selects the current source values. Reset

clears the CSSEL0:CSSEL1 bits.

CSEN—Current Source Enable Bit

This read/write bit enables the current source for PA1. Reset

clears the CSEN bit (Table 4).

The flag is set if the sensed current is higher than I

.

HSCT

To prevent noise on this flag, a hysteresis is implemented on

these terminals.

Table 4. PA1 Current Source Enable Bit

After switching on the Hall-effect sensor input terminals

(HxEN = 1), the Hall-effect sensors need some time to stabilize

the output. In RUN mode the software must wait at least 40 µs

between enabling the Hall-effect sensor and reading the

hallflag.

CSEN

Current Source Enable

Current Source Off

Current Source On

0

1

The Hall-effect sensor input terminal works in an dynamic

output voltage range from V_SUPdown to 2.0 V. Below 2.0 V the

HVDDON—HVDD On Bit

This read/write bit enables HVDD output. Reset clears the

HVDDON bit.

hallflags are not functional anymore. If the output voltage is

below a certain threshold, the Hall-Effect Sensor Input Terminal

Overcurrent Flag (HP_OCF) in the System Status Register is

set.

• 1 = HVDD enabled.

• 0 = HVDD disabled.

Figures 11 through 13, pp. 26–27, show the connections to

the Hall-effect input sensors.

HS_ON—Lamp Driver On Bit

This read/write bit enables the Lamp driver. Reset clears the

HS_ON bit.

• 1 = Lamp driver enabled.

• 0 = Lamp driver disabled.

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HxEN

Two-Terminal Hall-Effect Sensor

Hx

Sense

Circuitry

HxF

GND

V

Figure 11. Hall-Effect Sensor Input Terminal Connected to Two-Terminal Hall-Effect Sensor

HxEN

Rv

Hx

Sense

Circuitry

HxF

GND

V

Figure 12. Hall-Effect Sensor Input Terminal Connected to Local Switch

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Three-Terminal Hall-Effect Sensor

Vs

HxEN

Hx

Out

Sense

Circuitry

HxF

GND

V

Figure 13. Hall-Effect Sensor Input Terminal Connected to Three-Terminal Hall-Effect Sensor

Cyclic Wake-Up

Interrupts

The Hall-effect sensor input terminals are interrupt capable.

How and when an interrupt occurs is dependent on the

operating mode, RUN or Stop.

The Hall-effect sensor inputs can be used to wake up the

system. This wake-up function is provided by the cyclic check

wake-up feature of the AWD (autonomous watchdog).

If the cyclic check wake-up feature is enabled (AWDCC bit is

set), the AWD switches on the enabled Hall-effect sensor

terminals periodically. To ensure that the Hall-effect sensor

current is stabilized after switching on, the inputs are sensed

RUN Mode

In RUN mode the Hall-effect sensor input terminal interrupt

flag (HPF) will be set if a state change on the hallflags (HxF) is

detected. The interrupt is maskable with the HPIE bit in the

Interrupt Mask Register. Before enabling the interrupt, the flag

should be cleared in order to prevent a wrong interrupt.

after ~40 µs. If a “1” is detected (I

> I

) and the

HSCT

Hall sensor

interrupt mask bit HPIE is set, an interrupt is performed. This

wakes up the MCU and starts the main voltage regulator.

The wake-up function via this input is available when all three

conditions exist:

STOP Mode

In STOP mode the Hall-effect sensor input terminals are

disabled independent of the state of the HxEN flags.

• The two-terminal Hall-effect sensor input is enabled

(HxEN = 1).

• The cyclic wake-up of the AWD is enabled (AWDCC = 1)

(see Figure 14, page 28).

• The Hall-effect sensor input terminal interrupt is enabled

(HPIE = 1).

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SPI:

AWDCC = 1

GS = 1

SPI Command

STOP

MREG

No

AWD

Timer Overflow?

STOP

Yes

No

Switch on

Selected Hallport

IRQ?

Yes

SPI:

Wait 40 µs

Reason for Wakeup

Yes

Operate

Assert IRQ_A

Hallport = 1

No

Switch off

Selected Hallport

MREG = Main Voltage

Regulator

Figure 14. Hall-Effect Sensor Input Terminal Cyclic Check Wake-Up Feature

Hall-Effect Sensor Input Terminal Control Register

(HACTL)

Hall-Effect Sensor Input Terminal Status Register

(HASTAT)

Register Name and Address: HACTL - $08

Register Name and Address: HASTAT - $09

Bit7

6

0

5

0

4

0

3

0

2

1

Bit0

Bit7

6

0

5

0

4

0

3

0

2

1

Bit0

H1F

Read

Write

Reset

Read

Write

Reset

0

H3F

H2F

H3EN H2EN H1EN

0

H3EN:H1EN—Hall-Effect Sensor Input Terminal Enable

Bits

H3F:H1F—Hall-Effect Sensor Input Terminal Flag Bits

These read-only flag bits reflect the input Hx while the Hall-

effect sensor input terminal Hx is enabled (HxEN = 1). Reset

clears the H3F:H1F bits.

These read/write bits enable the Hall-effect sensor input

terminals. Reset clears the H3EN:H1EN bits.

• 1 = Hall-effect sensor input terminal Hx switched on and

sensed.

• 1 = Hall-effect sensor input terminal current above

threshold.

• 0 = Hall-effect sensor input terminal Hx disabled.

• 0 = Hall-effect sensor input terminal current below

threshold.

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HB1:HB4 output features:

Half-Bridges

• Short circuit (overcurrent) protection on high-side and low-

side MOSFETs.

• Current recopy feature (low side MOSFET).

• Overtemperature protection.

• Overvoltage and undervoltage protection.

• Current limitation feature (low side MOSFET).

Outputs HB1:HB4 provide four low-resistive half-bridge

output stages. The half-bridges can be used in H-Bridge, high-

side, or low-side configurations.

Reset clears all bits in the H-Bridge Output Register

(HBOUT) owing to the fact that all half-bridge outputs are

switched off.

VSUP

On/Off

High-Side Driver

Charge Pump,

Overtemperature Protection,

Overcurrent Protection

Status

BEMF

Control

HBx

On/Off

Status

Low-Side Driver

Current Recopy,

Current Limitation,

Overcurrent Protection

Current

Limit

GND

Figure 15. Half-Bridge Push-Pull Output Driver

Half-Bridge Output Register (HBOUT)

Half-Bridge Control

Each output MOSFET can be controlled individually. The

general enable of the circuitry is done by setting PSON in the

System Control Register (SYSCTL). HBx_L and HBx_H form

one half-bridge. It is not possible to switch on both MOSFETs in

one half-bridge at the same time. If both bits are set, the high-

side MOSFET has a higher priority.

Register Name and Address: HBOUT - $01

Bit7

6

5

4

3

2

1

Bit0

Read

Write

Reset

HB4_H HB4_L HB3_H HB3_L HB2_H HB2_L HB1_H HB1_L

0

To avoid both MOSFETs (high side and low side) of one half-

bridge being on at the same time, a break-before-make circuit

exists. Switching the high-side MOSFET on is inhibited as long

HBx_L—Low-Side On/Off Bits

as the potential between gate and V is not below a certain

SS

These read/write bits turn on the low-side MOSFETs. Reset

clears the HBx_L bits.

threshold. Switching the low-side MOSFET on is blocked as

long as the potential between gate and source of the high-side

MOSFET did not fall below a certain threshold.

• 1 = Low-side MOSFET turned on for half-bridge output x.

• 0 = Low-side MOSFET turned off for half-bridge output x.

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HBx_H—High-Side On/Off Bits

the load characteristics. The FGEN input provides the PWM

frequency, whereas the duty cycle is controlled by the load

characteristics.

These read/write bits turn on the high-side MOSFETs. Reset

clears the HBx_H bits.

The recommended frequency range for the FGEN and the

PWM is 0.1 kHz to 20 kHz.

1 = High-side MOSFET turned on for half-bridge output x.

0 = High-side MOSFET turned on for half-bridge output x.

Functionality

Half-Bridge Current Limitation

Each low-side MOSFET switches off if a current above the

selected current limit was detected. The 908E625 offers five

different current limits (refer to Table 5, page 33, for current limit

values). The low-side MOSFET switches on again if a rising

edge on the FGEN input was detected (Figure 16).

Each low-side MOSFET offers a current limit or constant

current feature. This features is realized by a pulse width

modulation on the low-side MOSFET. The pulse width

modulation on the outputs is controlled by the FGEN input and

H-Bridge low-side

MOSFET will be switched

off if select current limit is

reached.

Coil Current

H-Bridge low-side

MOSFET will be turned on

with each rising edge of

the FGEN input.

t (µs)

Half-Bridge

Low-Side Output

t (µs)

FGEN Input

(MCU PWM

Signal)

t (µs)

Minimum 50 µs

Figure 16. Half-Bridge Current Limitation

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Offset Chopping

HB4 will switch on the low-side MOSFETs with the falling edge

on the FGEN input. In step motor applications this feature

allows the reduction of EMI due to a reduction of the di/dt

(Figure 17).

If bit OFC_EN in the H-Bridge Control Register (HBCTL) is

set, HB1 and HB2 will continue to switch on the low-side

MOSFETs with the rising edge of the FGEN signal and HB3 and

Coil1 Current

Coil2 Current

FGEN Input

(MCU PWM

Signal)

HB1

Coil1…..

HB2

HB3

Coil2…..

HB4

Current in

VSUP Line

Figure 17. Offset Chopping for Step Motor Control

Half-Bridge Current Recopy

Half-Bridge BEMF Generation

Each low-side MOSFET has an additional sense output to

allow a current recopy feature. This sense source is internally

connected to a shunt resistor. The drop voltage is amplified and

switched to the analog multiplexer.

The BEMF output is set to “1” if a recirculation current is

detected in any half-bridge. This recirculation current flows via

the two freewheeling diodes of the power MOSFETs. The

BEMF circuitry detects that and generates a HIGH on the BEMF

output as long as a recirculation current is detected. This signal

provides a flexible and reliable detection of stall in step motor

applications. For this the BEMF circuitry takes advantage of the

instability of the electrical and mechanical behavior of a step

motor when blocked. In addition the signal can be used for open

load detection (absence of this signal) (see Figure 18,

page 32).

The factor for the current sense amplification can be selected

via bit CSA in the System Control Register.

• CSA = 1: Low resolution selected (500 mA measurement

range).

• CSA = 0: High resolution selected (2.5 A measurement

range).

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Coil Current

1

Voltage on

1

BEMF Signal

Figure 18. BEMF Signal Generation

The overvoltage/undervoltage status flags are cleared (and

the outputs re-enabled) by writing a logic [1] to the LVF/HVF

flags in the Interrupt Flag Register or by reset. Clearing this flag

is useless as long as a high- or low-voltage condition is present.

Half-Bridge Overtemperature Protection

The half-bridge outputs provide an overtemperature pre-

warning with the HTF in the Interrupt Flag Register (IFR). In

order to protect the outputs against overtemperature, the High-

Temperature Reset must be enabled. If this value is reached,

the part generates a reset and disables all power outputs.

Half-Bridge Control Register (HBCTL)

Register Name and Address: HBCTL - $02

Half-Bridge Overcurrent Protection

Bit7

6

5

0

4

0

3

0

2

1

Bit0

The half-bridges are protected against short to GND, short to

VSUP, and load shorts.

Read

Write

Reset

OFC_EN CSA

CLS2 CLS1 CLS0

In the event an overcurrent on the high side is detected, the

high-side MOSFETs on all HB high-side MOSFETs are

switched off automatically. In the event an overcurrent on the

low side is detected, all HB low-side MOSFETs are switched off

automatically. In both cases the overcurrent status flag

HB_OCF in the System Status Register (SYSSTAT) is set.

0

OFC_EN—H-Bridge Offset Chopping Enable Bit

This read/write bit enables offset chopping. Reset clears the

OFC_EN bit.

The overcurrent status flag is cleared (and the outputs re-

enabled) by writing a logic [1] to the HB_OCF flag in the System

Status Register or by reset.

• 1 = Offset chopping enabled.

• 0 = Offset chopping disabled.

CSA—H-Bridges Current Sense Amplification Select Bit

Half-Bridge Overvoltage/Undervoltage

This read/write bit selects the current sense amplification of

the H-Bridges. Reset clears the CSA bit.

The half-bridge outputs are protected against undervoltage

and overvoltage conditions. This protection is done by the low-

and high-voltage interrupt circuitry. If one of these flags (LVF,

HVF) is set, the outputs are automatically disabled.

• 1 = Current sense amplification set for measuring 0.5 A.

• 0 = Current sense amplification set for measuring 2.5 A.

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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CLS2:CLS0—H-Bridge Current Limitation Selection Bits

High-Side Driver

These read/write bits select the current limitation value

according to Table 5. Reset clears the CLS2:CLS0 bits.

The high-side output is a low-resistive high-side switch

targeted for driving lamps. The high side is protected against

overtemperature. To limit the high inrush current of bulbs,

overcurrent protection circuitry is used to limit the current. The

output is enabled with bit PSON in the System Control Register

and can be switched on/off with bit HS_ON in the Power Output

Register. Figure 19 depicts the high-side switch circuitry and

connection to external lamp.

Table 5. H-Bridge Current Limitation Value Selection Bits

CLS2

CLS1

CLS0

Current Limit

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No Limit

High-Side Overvoltage/Undervoltage Protection

55 mA (typ)

260 mA (typ)

370 mA (typ)

550 mA (typ)

740 mA (typ)

The high-side output terminal, HS, is protected against

undervoltage/overvoltage conditions. This protection is done

by the low- and high-voltage interrupt circuitry. If one of these

flags (LVF, HVF) is set, the output is disabled.

The overvoltage/undervoltage status flags are cleared and

the output re-enabled by writing a logic [1] to the LVF/HVF flags

in the Interrupt Flag Register or by reset. Clearing this flag is

useless as long as a high- or low-voltage condition is present.

VSUP

On/Off

High-Side Driver

Charge Pump,

Status

Control

Overcurrent Protection,

Inrush Current Limiter

Current

Limit

HS

Figure 19. High-Side Circuitry

Due to the high inrush current of bulbs, a special feature of

the 908E625 prevents an overcurrent shutdown during this

inrush. If an PWM frequency is supplied to the FGEN output

during the switching on of a bulb, the inrush current is limited to

the overcurrent shutdown limit. This means if the current

reaches the overcurrent shutdown, the high side will be

switched off, but each rising edge on the FGEN input will enable

the driver again.

High-Side Overtemperature Protection

The high-side output provides an overtemperature pre-

warning with the HTF in the Interrupt Flag Register. In order to

protect the output against overtemperature, the High-

Temperature Reset must be enabled. If this value is reached,

the part generates a reset and disables all power outputs.

High-Side Overcurrent Protection

To distinguish between a shutdown due to an inrush current

or a real shutdown, the software must check if the overcurrent

status flag (HS_OCF) in the System Status Register is set

beyond a certain period of time. The overcurrent status flag is

cleared by writing a logic [1] to the HS_OCF in the System

Status Register (see Figure 20, page 34).

The high-side output is protected against overcurrent. In the

event overcurrent limit is or was reached, the output

automatically switches off and the overcurrent flag is set.

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HS Current

HS Overcurrent Shutdown Threshold

t

FGEN Input

(MCU PWM

Signal)

t

Figure 20. Inrush Current Limiter on High-Side Output

System Control Register (SYSCTL)

Switchable VDD Outputs

The HVDD terminal is a switchable VDD output terminal. It

can be used for driving external circuitry that requires a V

Register Name and Address: SYSCTL - $03

DD

Bit7

6

5

4

0

3

0

2

0

1

0

Bit0

0

voltage. The output is enabled with bit PSON in the System

Control Register and can be switched on/off with bit HVDDON

in the Power Output Register. Low- or high-voltage conditions

(LVI/HVI) have no influence on this circuitry.

Read

Write

Reset

PSON SRS1 SRS0

GS

0

HVDD Overtemperature Protection

PSON—Power Stages On Bit

Overtemperature protection is enabled if the high-

temperature reset is enabled.

This read/write bit enables the power stages (half-bridges,

high side, LIN transmitter, Analog Input PA1 current sources,

and HVDD output). Reset clears the PSON bit.

HVDD Overcurrent Protection

• 1 = Power stages enabled.

• 0 = Power stages disabled.

The HVDD output is protected against overcurrent. In the

event the overcurrent limit is or was reached, the output

automatically switches off and the HVDD overcurrent flag in the

System Status Register is set.

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SRS0:SRS1—LIN Slew Rate Selection Bits

HVDD_OCF—HVDD Output Overcurrent Flag Bit

These read/write bits enable the user to select the

appropriate LIN slew rate for different baud rate configurations

as shown in Table 6.

This read/write flag is set on an overcurrent condition at the

HVDD terminal. Clear HVDD_OCF and enable the output by

writing a logic [1] to the HVDD_OCF Flag. Reset clears the

HVDD_OCF bit. Writing a logic [0] to HVDD_OCF has no effect.

The high speed slew rates are used, for example, for

programming via the LIN and are not intended for use in the

application.

• 1 = Overcurrent condition on HVDD has occurred.

• 0 = No overcurrent condition on HVDD has occurred.

Table 6. LIN Slew Rate Selection Bits

HS_OCF—High-Side Overcurrent Flag Bit

SRS1

SRS0

LIN Slew Rate

Initial Slew Rate (20 kBaud)

Slow Slew Rate (10 kBaud)

High Speed II (8x)

This read/write flag is set on an overcurrent condition at the

high-side driver. Clear HS_OCF and enable the high-side driver

by writing a logic [1] to HS_OCF. Reset clears the HS_OCF bit.

Writing a logic [0] to HS_OCF has no effect.

0

1

0

1

0

1

• 1 = Overcurrent condition on high-side drivers has

occurred.

High Speed I (4x)

• 0 = No overcurrent condition on high-side drivers has

occurred.

GS—Go to STOP Mode Bit

This write-only bit instructs the 908E625 to power down and

go into STOP mode. Reset or CPU interrupt requests clear the

GS bit.

LVF—Low-Voltage Bit

This read only bit is a copy of the LVF bit in the Interrupt Flag

Register.

• 1 = Power down and go into STOP mode.

• 0 = Not in STOP mode.

• 1 = Low-voltage condition has occurred.

• 0 = No low-voltage condition has occurred.

System Control Register (SYSSTAT)

Register Name and Address: SYSSTAT - $0c

HVF—High-Voltage Sensor Bit

This read-only bit is a copy of the HVF bit in the Interrupt Flag

Register.

Bit7

6

5

4

3

2

1

Bit0

HTF

• 1 = High-voltage condition has occurred.

• 0 = No high-voltage condition has occurred.

Read

Write

Reset

LINCL

LVF

HVF

HP_

OCF

HVDD

_OCF

HS_

OCF

HB_

OCF

0

HB_OCF—H-Bridge Overcurrent Flag Bit

This read/ write flag is set on an overcurrent condition at the

H-Bridges. Clear HB_OCF and enable the H-Bridge driver by

writing a logic [1] to HB_OCF. Reset clears the HB_OCF bit.

Writing a logic [0] to HB_OCF has no effect.

HP_OCF—Hall-Effect Sensor Input Terminal Overcurrent

Flag Bit

This read/write flag is set on an overcurrent condition at one

of the Hall-effect sensor input terminals. Clear HP_OCF and

enable the output by writing a logic [1] to the HP_OCF flag.

Reset clears the HP_OCF bit. Writing a logic [0] to HP_OCF

has no effect.

• 1 = Overcurrent condition on H-Bridges has occurred.

• 0 = No overcurrent condition on H-Bridges has occurred.

HTF—Overtemperature Status Bit

• 1 = Overcurrent condition on Hall-effect sensor input

terminal has occurred.

• 0 = No overcurrent condition on Hall-effect sensor input

terminal has occurred.

This read-only bit is a copy of the HTF bit in the Interrupt Flag

Register.

• 1 = Overtemperature condition has occurred.

• 0 = No overtemperature condition has occurred.

LINCL — LIN Current Limitation Bit

This read-only bit is set if the LIN transmitter operates in

current limitation region. Due to excessive power dissipation in

the transmitter, software is advised to turn the transmitter off

immediately.

• 1 = Transmitter operating in current limitation region.

• 0 = Transmitter not operating in current limitation region.

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AWDRE—Autonomous Watchdog Reset Enable Bit

Autonomous Watchdog (AWD)

This read/write bit enables resets on AWD timeouts. A reset

on the RST_A is only asserted when the device is in RUN mode.

AWDRE is one-time setable (write once) after each reset. Reset

clears the AWDRE bit.

The Autonomous Watchdog module consists of three

functions:

• Watchdog function for the CPU in RUN mode

• Periodic interrupt function in STOP mode

• Cyclic wake-up function in STOP mode

• 1 = Autonomous watchdog enabled.

• 0 = Autonomous watchdog disabled.

The AWD is enabled if AWDIE, AWDRE, or AWDCC in the

AWDCTL Register is set. If these bits are cleared, the AWD

oscillator is disabled and the watchdog switched off.

AWDIE—Autonomous Watchdog Interrupt Enable Bit

This read/write bit enables CPU interrupts by the

Autonomous Watchdog timeout flag, AWFD. IRQ_A is only

asserted when the device is in STOP mode. Reset clears the

AWDIE bit.

Watchdog

The watchdog function is only available in RUN mode. On

setting the AWDRE bit, watchdog functionality in RUN mode is

activated. Once this function is enabled, it is not possible to

disable it via software.

• 1 = CPU interrupt requests from AWDF enabled.

• 0 = CPU interrupt requests from AWDF disabled.

If the timer reaches end value and AWDRE is set, a system

reset is initiated. Operations of the watchdog function cease in

STOP mode. Normal operation will be continued when the

system is back to RUN mode.

AWDCC— Autonomous Watchdog Cyclic Check

This read/write bit enables the cyclic check of the two-

terminal Hall-effect sensor and the analog inputs. Reset clears

the AWDCC bit.

To prevent a watchdog reset, the watchdog timeout counter

must be reset before it reaches the end value. This is done by

a write to the AWDRST bit in the AWDCTL Register.

• 1 = Cyclic check of the Hall-effect sensor and analog port.

• 0 = No cyclic check of the Hall-effect sensor and analog

port.

Periodic Interrupt

AWDF—Autonomous Watchdog Timeout Flag Bit

Periodic interrupt is only available in STOP mode. It is

enabled by setting the AWDIE bit in the AWDCTL Register. If

AWDIE is set, the AWD wakes up the system after a fixed

period of time. This time period can be selected with bit AWDR

in the AWDCTL Register.

This read/write flag is set when the Autonomous Watchdog

has timed out. Clear AWDF by writing a logic [1] to AWDF.

Clearing AWDF also resets the AWD counter and starts a new

timeout period. Reset clears the AWDF bit. Writing a logic [0] to

AWDF has no effect.

• 1 = AWD has timed out.

• 0 = AWD has not yet timed out.

Cyclic Wake-Up

The cyclic wake-up feature is only available in STOP mode.

If this feature is enabled, the selected Hall-effect sensor input

terminals are switched on and sensed. If a “1” is detected on

one of these inputs and the interrupt for the Hall-effect sensors

is enabled, a system wake-up is performed. (Switch on main

voltage regulator and assert IRQ_A to the microcontroller).

AWDR—Autonomous Watchdog Rate Bit

This read/write bit selects the clock rate of the Autonomous

Watchdog. Reset clears the AWDR bit.

• 1 = Fast rate selected (10 ms).

• 0 = Slow rate selected (20 ms).

Autonomous Watchdog Control Register (AWDCTL)

Register Name and Address: AWDCTL - $0a

Voltage Regulator

The 908E625 chip contains a low-power, low-drop voltage

regulator to provide internal power and external power for the

MCU. The on-chip regulator consist of two elements, the main

voltage regulator and the low-voltage reset circuit.

Bit7

0

6

0

5

4

3

2

1

Bit0

0

AWDRST

0

Read

Write

Reset

ADRE AWDIE AWDCC AWDF AWDR

The V regulator accepts a unregulated input supply and

0

DD

provides a regulated V_DDsupply to all digital sections of the

device. The output of the regulator is also connected to the VDD

terminal to provide the 5.0 V to the microcontroller.

AWDRST—Autonomous Watchdog Reset Bit

This write-only bit resets the Autonomous Watchdog timeout

period. AWDRST always reads 0. Reset clears AWDRST bit.

• 1 = Reset AWD and restart timeout period.

• 0 = No effect.

908E625

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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RUN Mode

STOP Mode

During RUN mode the main voltage regulator is on. It

provides a regulated supply to all digital sections.

During STOP mode the STOP mode regulator supplies a

regulated output voltage. The STOP mode regulator has a very

limited output current capability. The output voltage will be

lower than the output voltage of the main voltage regulator.

FACTORY TRIMMING AND CALIBRATION

To enhance the ease-of-use of the 908E625, various

parameters (e.g. ICG trim value) are stored in the flash memory

of the device. The following flash memory locations are

reserved for this purpose and might have a value different from

the “empty” (0xFF) state:

In the event the application uses these parameters, one has

to take care not to erase or override these values. If these

parameters are not used, these flash locations can be erased

and otherwise used.

• 0xFD800xFDDF Trim and Calibration Values

• 0xFFFE:0xFFFF Reset Vector

PACKAGE THERMAL PERFORMANCE

Figure 21 shows a thermal response curve for a package

mounted onto a thermally enhanced PCB.

Note The PCB board is a multi-layer with two inner copper

planes (2s2p). The board conforms to JEDEC EIA/JESD 51-5

and JESD51-7. Substrate thickness is 1.60 mm. Top and

bottom copper trace layers are 0.7 mm thick, with two inner

copper planes of 0.35 mm thickness. Thermal vias have

0.35 mm thick plating.

30

25

20

15

10

5

5.0

0

0.00001 0.0001 0.001

0.01

0.1

11.0

10

100

1000

10000

Time (s)

time[s]

Figure 21. Thermal Response of H-Bridge Driver with Package Soldered to a JEDEC PCB Board

908E625

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PACKAGE DIMENSIONS

DWB SUFFIX

54-TERMINAL SOIC WIDE BODY EXPOSED PAD

PLASTIC PACKAGE

CASE 1400-01

ISSUE B

10.3

5

9

NOTES:

7.6

7.4

1. DIMENSIONS ARE IN MILLIMETERS.

2. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

C

2.65

2.35

B

3. DATUMS B AND C TO BE DETERMINED AT THE

PLANE WHERE THE BOTTOM OF THE LEADS

EXIT THE PLASTIC BODY.

4. THIS DIMENSION DOES NOT INCLUDE MOLD

FLASH, PROTRUSION OR GATE BURRS. MOLD

FLASH, PROTRUSION OR GATE BURRS SHALL

NOT EXCEED 0.15 MM PER SIDE. THIS

DIMENSION IS DETERMINED AT THE PLANE

WHERE THE BOTTOM OF HTE LEADS EXIT THE

PLASTIC BODY.

52X

1

54

0.65

PIN 1 INDEX

5. THIS DIMENSION DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH AND PROTRUSIONS SHALL

NOT EXCEED 0.25 MM PER SIDE. THIS

DIMENSION IS DETERMINED AT THE PLANE

WHERE THE BOTTOM OF THE LEADS EXIT THE

PLASTIC BODY.

6. THIS DIMENSION DOES NOT INCUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL NOT CAUSE THE LEAD

WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT

BE LOCATED ON THE LOWER RADIUS OR THE

FOOT. MINIMUM SPACE BETWEEN PROTRUSION

AND ADJACENT LEAD SHALL NOT BE LESS THAN

0.07 MM.

4

9

18.0

17.8

C

L

B

7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.

8. THESE DIMENSIONS APPLY TO THE FLAT

SECTION OF THE LEAD BETWEEN 0.1 MM AND

0.3 MM FROM THE LEAD TIP.

9. THE PACKAGE TOP MAY BE SMALLER THAN

THE PACKAGE BOTTOM. THIS DIMENSION IS

DETERMINED AT THE OUTERMOST EXTREMES

OF THE PLASTIC BODY EXCLUSIVE OF MOLD

FLASH, TIE BAR BURRS, GATE BURRS AND

INTER-LEAD FLASH, BUT INCLUDING ANY

MISMATCH BETWEEN THE TOP AND BOTOM

OF THE PLASTIC BODY.

27

28

SEATING

A

PLANE

5.15

2X 27 TIPS

54X

0.10

A

0.3

A B C

A

R0.08 MIN

˚

MIN

0

C

0.25

GAUGE PLANE

(1.43)

0.1

0.0

0.9

0.5

˚

8

˚

0

10.9

9.7

SECTION B-B

0.30

A B C

(0.29)

BASE METAL

0.30

0.25

(0.25)

5.3

4.8

0.38

0.22

0.30 A B C

PLATING

6

M

0.13

A B C

8

SECTION A-A

ROTATED 90˚ CLOCKWISE

VIEW C-C

908E625

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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NOTES

908E625

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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied

copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee

regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product

or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be

provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating

parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license

under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product

could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all

claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated

with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their

respective owners.

HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:

JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center

3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan

81-3-3440-3569

Motorola Literature Distribution

P.O. Box 5405, Denver, Colorado 80217

1-800-521-6274 or 480-768-2130

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre

2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong

852-26668334

HOME PAGE: http://motorola.com/semiconductors

MM908E625

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型号：	PM908E625ACDWBR2
厂家：	NXP
描述：	8-BIT, FLASH, 8MHz, MICROCONTROLLER, PDSO54, SOIC-54 光电二极管外围集成电路
文件：	总40页 (文件大小：578K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PM908E625ACDWBR2 [NXP]

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