PIP3102-R [NXP]
LOGIC LEVEL TOPFET; 逻辑电平TOPFET
| 型号： | PIP3102-R |
| 厂家： | 
NXP |
| 描述： | LOGIC LEVEL TOPFET |
| 文件： | 总13页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product Specification
Logic level TOPFET
PIP3102-R
DESCRIPTION
QUICK REFERENCE DATA
Monolithic logic level protected
power MOSFET using TOPFET2
technology assembled in a 5 pin
surface mounting plastic package.
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Ptot
Tj
Continuous drain source voltage
Continuous drain current
Total power dissipation
Continuous junction temperature
Drain-source on-state resistance
50
30
90
150
28
V
A
W
˚C
mΩ
APPLICATIONS
RDS(ON)
General purpose switch for driving
lamps
SYMBOL
PARAMETER
NOM.
UNIT
motors
solenoids
heaters
VPS
Protection supply voltage
5
V
FEATURES
FUNCTIONAL BLOCK DIAGRAM
TrenchMOS output stage with
low on-state resistance
Separate input pin for higher
frequency drive
PROTECTION SUPPLY
DRAIN
5 V logic compatible input
Separate supply pin for logic
and protection circuits with low
operating current
FLAG
OC LOAD
O/V
DETECT
CLAMP
POWER
Overtemperature protection
Drain current limiting
INPUT
MOSFET
RIG
Short circuit load protection
Latched overload trip state reset
by the protection pin
Diagnostic flag pin indicates
protection supply connected,
overtemperature condition,overload
tripped state, or open circuit load
(detected in the off-state)
ESD protection on all pins
Overvoltage clamping
LOGIC AND
PROTECTION
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT426
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
mb
D
S
input
flag
TOPFET
2
P
F
I
P
3
(connected to mb)
protection supply
source
3
4
1 2
4 5
5
Fig. 2.
Fig. 3.
mb drain
October 2002
1
Rev 1.000
Philips Semiconductors
Product Specification
Logic level TOPFET
PIP3102-R
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER
Continuous voltage
CONDITIONS
MIN.
MAX.
UNIT
V
VDS
Drain source voltage1
Continuous currents
Drain current
VIS = 0 V
-
-
50
ID
VPS = 5 V; Tmb =25˚C
VPS = 0 V; Tmb =85˚C
self -
limited
30
5
5
5
A
-
A
II
IF
IP
Input current
-5
-5
-5
mA
mA
mA
Flag current
Protection supply current
Thermal
Ptot
Total power dissipation
Tmb = 25˚C
-
90
W
Tstg
Tj
Tsold
Storage temperature
-55
-
-
175
150
260
˚C
˚C
˚C
Junction temperature2
Mounting base temperature
continuous
during soldering
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VC
Electrostatic discharge capacitor
voltage
Human body model;
C = 250 pF; R = 1.5 kΩ
-
2
kV
OVERLOAD PROTECTION LIMITING VALUE
With an adequate protection supply
connected, TOPFET can protect
itself from two types of overload -
overtemperature and short circuit
load.
For overload conditions an n-MOS
The drain current is limited to
reduce dissipation in case of short
circuit load. Refer to OVERLOAD
CHARACTERISTICS.
transistor turns on between the
input and source to quickly
discharge the power MOSFET
gate capacitance.
SYMBOL PARAMETER
Overload protection3
REQUIRED CONDITION
protection supply
PS ≥ 4 V
MIN.
MAX.
UNIT
VDS
Drain source voltage
V
0
35
V
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL PARAMETER
Inductive load turn off
CONDITIONS
IDM = 20 A; VDD ≤ 20 V
Tmb = 25˚C
MIN.
MAX.
UNIT
EDSM
EDRM
Non-repetitive clamping energy
Repetitive clamping energy
-
-
350
45
mJ
mJ
Tmb ≤ 95˚C; f = 250 Hz
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch.
3 All control logic and protection functions are disabled during conduction of the source drain diode. If the protection circuit was previously
latched, it would be reset by this condition.
October 2002
2
Rev 1.000
Philips Semiconductors
Product Specification
Logic level TOPFET
PIP3102-R
THERMAL CHARACTERISTIC
SYMBOL PARAMETER
Thermal resistance
CONDITIONS
MIN. TYP. MAX. UNIT
Rth j-mb
Junction to mounting base
-
-
1.2
1.39
K/W
OUTPUT CHARACTERISTICS
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified.
SYMBOL PARAMETER
Off-state
CONDITIONS
MIN. TYP. MAX. UNIT
VIS = 0 V
V(CL)DSS
Drain-source clamping voltage ID = 10 mA
IDM = 4 A; tp ≤ 300 µs; δ ≤ 0.01
VPS = 0 V; VDS = 40 V
50
50
-
70
70
V
V
60
IDSS
Drain source leakage current1
-
-
-
100
10
µA
µA
Tmb = 25˚C
0.1
On-state
tp ≤ 300 µs; δ ≤ 0.01; VPS ≥ 4 V
RDS(ON)
Drain-source resistance
IDM = 10 A; VIS ≥ 4.4 V
-
-
-
21
50
28
mΩ
mΩ
Tmb = 25˚C
INPUT CHARACTERISTICS
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified.
SYMBOL PARAMETER
Normal operation
CONDITIONS
MIN. TYP. MAX. UNIT
VIS(TO)
Input threshold voltage2
ID = 1 mA
0.6
1.1
-
2.6
2.1
V
V
Tmb = 25˚C
1.6
IIS
Input current
VIS = 5 V
II = 1 mA
-
5.5
-
16
6.4
1.7
100
8.5
-
µA
V
V(CL)IS
RIG
Input clamping voltage
Internal series resistance3
Overload protection latched
Input current
to gate of power MOSFET
PS ≥ 4 V
VIS = 5 V
kΩ
V
IISL
1
2.7
4
mA
1 The drain current required for open circuit load detection is switched off when there is no protection supply, in order to ensure a low off-state
quiescent current. Refer to OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS.
2 The measurement method is simplified if VPS = 0 V, in order to distinguish ID from IDSP. Refer to OPEN CIRCUIT LOAD DETECTION
CHARACTERISTICS.
3 This is not a directly measurable parameter.
October 2002
3
Rev 1.000
Philips Semiconductors
Product Specification
Logic level TOPFET
PIP3102-R
PROTECTION SUPPLY CHARACTERISTICS
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C.
SYMBOL PARAMETER
Protection & detection
Threshold voltage1
CONDITIONS
MIN. TYP. MAX. UNIT
VPSF
IF = 100 µA; VDS = 5 V
2.5
3.45
4
V
Normal operation or
protection latched
Supply current
IPS, IPSL
V(CL)PS
VPS = 4.5 V
IP = 1.5 mA
-
210
6.5
450
8.5
µA
Clamping voltage
5.5
V
Overload protection latched
VPSR
tpr
Reset voltage
Reset time
1
10
1.8
45
3
120
V
µs
VPS ≤ 1 V
OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS
An open circuit load condition can be detected while the TOPFET is in the off-state. Refer to TRUTH TABLE.
VPS = 5 V. Limits are for -40˚C ≤ Tmb ≤ 150˚C and typicals are for Tmb = 25˚C.
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IDSP
VDSF
VISF
Off-state drain current2
Drain threshold voltage3
Input threshold voltage4
VIS = 0 V; 2 V ≤ VDS ≤ 40 V
VIS = 0 V
0.9
0.2
0.3
1.8
1
2.7
2
mA
V
ID = 100 µA
0.8
1.1
V
OVERLOAD CHARACTERISTICS
Tmb = 25˚C unless otherwise specified.
SYMBOL PARAMETER
Short circuit load
CONDITIONS
MIN. TYP. MAX. UNIT
VPS > 4 V
ID
Drain current limiting
VIS = 5 V;
-40˚C ≤ Tmb ≤ 150˚C
28.5
44
60
A
Overload protection
VPS > 4 V
PD(TO)
TDSC
Overload power threshold
Characteristic time
device trips if PD > PD(TO)
which determines trip time5
75
185
380
250
600
W
250
µs
Overtemperature protection
VPS = 5 V
Tj(TO)
Threshold temperature
from ID ≥ 4 A or VDS > 0.2 V
150
170
-
˚C
1 When VPS is less than VPSF the flag pin indicates low protection supply voltage. Refer to TRUTH TABLE.
2 The drain source current which flows in a normal load when the protection supply is high and the input is low.
3 If VDS < VDSF then the flag indicates open circuit load.
4 For open circuit load detection, VIS must be less than VISF
.
5 Trip time td sc varies with overload dissipation PD according to the formula td sc ≈ TDSC / ln[ PD / PD(TO)].
October 2002
4
Rev 1.000
Philips Semiconductors
Product Specification
Logic level TOPFET
PIP3102-R
TRUTH TABLE
For normal, open-circuit load and overload conditions or inadequate protection supply voltage.
Assumes proper external pull-up for flag pin. Refer to FLAG CHARACTERISTICS.
CONDITION
PROTECTION
INPUT
FLAG
OUTPUT
Normal on-state
Normal off-state
Open circuit load
Open circuit load
Short circuit load1
Over temperature
1
1
0
ON
1
1
1
1
1
0
0
0
1
0
1
X
1
0
0
0
1
1
1
1
1
OFF
ON
OFF
OFF
OFF
ON
Low protection supply voltage
Low protection supply voltage
OFF
KEY ‘0’ equals low
‘1’ equals high
‘X’ equals don’t care.
FLAG CHARACTERISTICS
The flag is an open drain transistor which requires an external pull-up circuit.
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C.
SYMBOL PARAMETER
Flag ‘low’
CONDITIONS
normal operation; VPS = 5 V
IF = 100 µA
MIN. TYP. MAX. UNIT
VFSF
IFSF
Flag voltage
-
-
0.8
10
1
-
V
Flag saturation current
Flag ‘high’
VFS = 5 V
mA
overload or fault
VFS = 5 V
IFSO
Flag leakage current
Flag clamping voltage
Application information
-
0.1
6.2
10
µA
V(CL)FS
IF = 100 µA
5.5
8.5
V
RF
Suitable external pull-up
resistance
VFF = 5 V
-
47
-
kΩ
SWITCHING CHARACTERISTICS
Tmb = 25˚C; RI = 50 Ω; RIS = 50 Ω; VDD = 15 V; resistive load RL = 10 Ω.
SYMBOL PARAMETER CONDITIONS
MIN. TYP. MAX. UNIT
td on
tr
td off
tf
Turn-on delay time
Rise time
VIS: 0 V
VIS: 5 V
5 V
0 V
-
-
-
-
1.8
3.5
11
5
5
8
µs
µs
µs
µs
Turn-off delay time
Fall time
30
12
1 In this condition the protection circuit is latched. To reset the latch the protection pin must be taken low. Refer to PROTECTION SUPPLY
CHARACTERISTICS.
October 2002
5
Rev 1.000
Philips Semiconductors
Product Specification
Logic level TOPFET
PIP3102-R
CAPACITANCES
Tmb = 25 ˚C; f = 1 MHz
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Ciss
Coss
Crss
Cpso
Input capacitance
VDS = 25 V; VIS = 0 V
VDS = 25 V; VIS = 0 V
VDS = 25 V; VIS = 0 V
VPS = 5 V
-
-
-
-
710
370
26
1050
550
40
pF
pF
pF
pF
Output capacitance
Reverse transfer capacitance
Protection supply pin
capacitance
22
-
Cfso
Flag pin capacitance
VFS = 5 V; VPS = 0 V
-
12
-
pF
PD%
Normalise Power Derating
ID / A
120
80
70
60
50
40
30
20
10
0
VIS / V =
100
80
60
40
20
0
7
6
5
4
3
0
20
40
60
Tmb
80
100
120
140
0
2
4
6
8
10
12
14
16
/
OC
VDS / V
Fig.4. Normalised limiting power dissipation.
PD% = 100 PD/PD(25˚C) = f(Tmb)
Fig.6. Typical output characteristics, Tj = 25˚C.
ID = f(VDS); parameter VIS; tp = 300 µs & tp < td sc
y
ID / A
ID / A
80
70
60
50
40
30
20
10
0
40
VIS / V =
7
6
30
20
10
0
5
4
3
2
0
20
40
60
80
OC
100
120
140
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
VDS / V
Tmb
/
Fig.5. Continuous drain current.
ID = f(Tamb); condition: VIS = 5 V
Fig.7. Typical on-state characteristics, Tj = 25˚C.
ID = f(VDS); parameter VIS; tp = 300 µs
October 2002
6
Rev 1.000
Philips Semiconductors
Product Specification
Logic level TOPFET
PIP3102-R
Tj (TO) OC
Normalised R DS(ON) = f(Tj)
a
2
200
190
180
170
160
150
Data below 4V is for
1.8
1.6
1.4
1.2
1
information only. All
spec. values are for
normal operation at
4V and above.
0.8
0.6
0.4
0.2
0
-50
0
50
100
150
3
4
5
6
7
8
Tj / O
C
VPS / V
Fig.8. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25˚C = f(Tj); ID = 10 A; VIS = 4.4 V
Fig.11. Typical overtemperature protection threshold.
Tj(TO) = f(VPS); conditions: VIS = 5 V
IDSS / A
100E-6
R
DS(ON) / mOhm
50
40
30
20
10
0
max.
10E-6
1E-6
max.
typ.
typ.
100E-9
10E-9
1E-9
-50
0
50
Tj / O
100
150
0
1
2
3
4
5
6
7
8
C
VIS / V
Fig.9. Typical on-state resistance, Tj = 25˚C. RDS(ON)
= f(VIS); conditions: ID = 10 A; VPS = 4 V; tp = 300 µs
Fig.12. Typical drain source leakage current.
IDSS = f(Tj); conditions: VDS = 40 V; VPS = VIS = 0 V
y
ID / A
IIS / mA
3.5
80
70
60
50
40
30
20
10
0
3.0
2.5
2.0
VDS = 13V
1.5
Latched
1.0
0.5
Unlatched
0
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
V
IS / V
VIS / V
Fig.10. Typical transfer characteristics, Tj = 25˚C.
Fig.13. Typical DC input characteristics, Tj = 25˚C.
IIS & IISL = f(VIS); normal operation & protection latched
ID = f(VIS); conditions: VPS ≥ 4 V tp = 300 µs
October 2002
7
Rev 1.000
Philips Semiconductors
Product Specification
Logic level TOPFET
PIP3102-R
IIS & IISL
10E-3
IDSP / mA
2.5
2.0
1.5
1.0
0.5
0
IISL
1E-3
00E-6
10E-6
IDSP is constant from Vds = 2V to 40V
IIS
-50
0
50
100
150
0
1
2
3
4
5
Tj / O
C
V
DS / V
Fig.14. Typical DC input currents. IIS & IISL = f(Tj);
normal & latched; conditions: VIS = 5 V; VPS = 5 V
Fig.17. Off state drain current characteristic.
IDSP = f(VDS); conditions: Tj = 25˚C; VPS = 5 V; VIS = 0 V
V
IS(TO) / V
I
DSP / mA
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.5
2.0
1.5
1.0
0.5
0
max.
typ.
min.
-50
0
50
100
150
Tj / O
C
0
1
2
3
4
5
6
7
8
VPS / V
Fig.15. Input threshold voltage.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
Fig.18. Off state drain current vs protection supply.
IDSP = f(VPS); Tj = 25˚C; VDS = 13 V; VIS = 0 V
IDSP / mA
2.5
IIS / mA
10
8
6
2.0
4
2
1.5
0
-50
0
50
100
150
0
2
4
6
8
Tj / O
C
V
IS / V
Fig.16. Typical input clamping characteristic.
II = f(VIS); normal operation, Tj = 25˚C
Fig.19. Typical off state drain current IDSP = f(Tj);
conditions: VDS = 13 V; VPS = 5 V; VIS = 0 V
October 2002
8
Rev 1.000
Philips Semiconductors
Product Specification
Logic level TOPFET
PIP3102-R
VPSR / V
VDSF / V
2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
Normal load
typ.
1
Open circuit load
0
-50
0
50
Tj / O
100
150
-50
0
50
100
150
Tj / O
C
C
Fig.20. Open circuit detection threshold voltage.
Fig.23. Typical protection reset voltage.
VDSF = f(Tj); VPS ≥ 4 V ; VIS = 0 V
VPSR = f(Tj); tlr = 100 µs
VISF / V
1.0
IFS / A
10E-6
1E-6
Normal operation
VPS = 0 or 5V
max.
typ.
typ.
0.5
Open circuit detection
00E-9
10E-9
0
-50
0
50
100
150
-50
0
50
Tj / O
100
150
Tj / O
C
C
Fig.21. Open circuit input threshold voltage.
Fig.24. Typical flag characteristics. IFS = f(Tj);
fault & overload operation; VIS = 5 V; VFS = 5 V
VISF = f(Tj); VPS ≥ 4 V ; ID = 100 µA
V
PSF / V
IPS / mA
4.0
3.8
3.6
3.4
3.2
3.0
2
1
0
-50
0
50
100
150
0
1
2
3
4
5
6
7
8
VPS / V
Tj / O
C
Fig.22. Typical DC protection supply characteristics.
IPS = f(VPS); normal or overload operation; Tj = 25 ˚C
Fig.25. Typical protection threshold voltage.
VPSF = f(Tj); VDS = 5 V ; IF = 100 µA
October 2002
9
Rev 1.000
Philips Semiconductors
Product Specification
Logic level TOPFET
PIP3102-R
V(CL)DSR
VDS
VII
VDD
VDD
+
-
0
L
D
ID
RI
TOPFET
VDS
VPS
+
P
F
I
0
P
VIS
D
VIS
RF
TOPFET
-ID/100
P
F
I
P
D.U.T.
0
S
RIS
RI = RIS
R 01
shunt
S
Fig.26. Clamping energy test circuit, RIS = 100 Ω.
EDSM = 0.5 LID2 V(CL)DSR/(V(CL)DSR − VDD
Fig.29. Test circuit for resistive load switching times.
VIS = 5 V
)
VIS & VDS / V
EDSM / J
16
14
12
10
8
1.2
1.0
0.8
0.6
0.4
0.2
0
VDS
25OC
VIS
150OC
6
4
2
0
0
5
10
15
20
25
Time / µs
30
35
40
45
50
0.1
1
10
100
L / mH
Fig.27. Typical non-repetitive clamping energy.
EDSM = f(L); conditions: VIS = 0 V
Fig.30. Typical switching waveforms, resistive load.
RL = 10 Ω; adjust VDD to obtain ID = 1.5 A; Tj = 25˚C
ID / A
VDSS / V
65
4
ID
=
3
2
1
0
4A
10mA
60
-50
0
50
100
150
50
60
DS / V
70
Tj / O
C
V
Fig.28. Typical clamping characteristic, 25˚C.
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 300 µs
Fig.31. Overvoltage clamping characteristic.
VDS = f(Tj); conditions: VIS = 0 V; tp ≤ 300 µs
October 2002
10
Rev 1.000
Philips Semiconductors
Product Specification
Logic level TOPFET
PIP3102-R
Capacitance / pF
ID / A
80
10000
1000
100
70
60
50
40
30
20
10
0
max.
typ.
Ciss
Coss
min.
Crss
10
-50
0
50
100
150
Tj / O
C
0
10
20
30
40
50
VDS / V
Fig.32. Typical overload current, VDS = 5 V.
ID = f(Tj); conditions: VIS = 5 V; VPS = 4 V; tp = 300 µs
Fig.34. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VIS = 0 V; f = 1 MHz
Zth / ( K / W )
IS / A
15
1E+01
1E+00
1E-01
1E-02
1E-03
0.5
0.2
10
5
0.1
PD
tp
0.05
tp
T
D =
0.02
0
T
0
0
0.5
VSD / V
1
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
t / s
Fig.33. Typical reverse diode current, Tj = 25 ˚C.
Fig.35. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
IS = f(VSDS); conditions: VIS = 0 V; tp = 300 µs
October 2002
11
Rev 1.000
Philips Semiconductors
Product Specification
Logic level TOPFET
PIP3102-R
MECHANICAL DATA
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 5 leads
(one lead cropped)
SOT426
A
A
E
1
D
1
mounting
base
D
H
D
3
L
p
1
2
4
5
b
c
e
e
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
A
A
L
H
Q
UNIT
b
c
D
E
e
1
p
D
1
max.
1.40
1.27
4.50
4.10
0.85
0.60
0.64
0.46
2.90 15.80 2.60
2.10 14.80 2.20
1.60
1.20
10.30
9.70
mm
11
1.70
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
98-12-14
99-06-25
SOT426
Fig.36. SOT426 surface mounting package1, centre pin connected to mounting base.
1 Epoxy meets UL94 V0 at 1/8". Net mass: 1.5 g.
For soldering guidelines and SMD footprint design, please refer to Data Handbook SC18.
October 2002
12
Rev 1.000
Philips Semiconductors
Product Specification
Logic level TOPFET
PIP3102-R
DEFINITIONS
DATA SHEET STATUS
DATA SHEET
STATUS1
PRODUCT
DEFINITIONS
STATUS2
Objective data
Development
This data sheet contains data from the objective specification for
product development. Philips Semiconductors reserves the right to
change the specification in any manner without notice
Preliminary data
Qualification
Production
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in
order to improve the design, manufacturing and supply. Changes will
be communicated according to the Customer Product/Process
Change Notification (CPCN) procedure SNW-SQ-650A
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 2002
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
1 Please consult the most recently issued datasheet before initiating or completing a design.
2 The product status of the device(s) described in this datasheet may have changed since this datasheet was published. The latest information is
available on the Internet at URL http://www.semiconductors.philips.com.
October 2002
13
Rev 1.000
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