PIP3104-P [NXP]
PowerMOS transistor Logic level TOPFET; 功率MOS晶体管逻辑电平TOPFET
| 型号： | PIP3104-P |
| 厂家： | 
NXP |
| 描述： | PowerMOS transistor Logic level TOPFET |
| 文件： | 总6页 (文件大小：34K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
PIP3104-P
DESCRIPTION
QUICK REFERENCE DATA
Monolithic temperature and
overload protected logic level power
MOSFET in TOPFET2 technology
assembled in a 3 pin plastic
package.
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
PD
Tj
Continuous drain source voltage
Continuous drain current
50
8
V
A
Total power dissipation
40
W
Continuous junction temperature
150
˚C
APPLICATIONS
RDS(ON)
IISL
Drain-source on-state resistance
100
650
mΩ
µA
General purpose switch for driving
Input supply current
VIS = 5 V
lamps
motors
solenoids
heaters
FEATURES
FUNCTIONAL BLOCK DIAGRAM
TrenchMOS output stage
Current limiting
Overload protection
DRAIN
Overtemperature protection
Protection latched reset by input
5 V logic compatible input level
Control of output stage and
supply of overload protection
circuits derived from input
Low operating input current
permits direct drive by
O / V
CLAMP
POWER
INPUT
MOSFET
RIG
micro-controller
ESD protection on all pins
Overvoltage clamping for turn
off of inductive loads
LOGIC AND
PROTECTION
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT78B
PIN CONFIGURATION
SYMBOL
mb
mb
PIN
1
DESCRIPTION
D
S
TOPFET
input
drain
2
I
P
3
source
tab drain
1
2
3
Front view
MBL292
May 2001
1
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
PIP3104-P
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
ID
Continuous drain source voltage1
Continuous drain current
-
-
-
50
self -
limited
8
5
10
40
175
150
V
A
VIS = 5 V; Tmb = 25 ˚C
ID
II
IIRM
PD
Tstg
Tj
Continuous drain current
Continuous input current
Non-repetitive peak input current
Total power dissipation
VIS = 5 V; Tmb ≤ 110 ˚C
-
tp ≤ 1 ms
-
-5
-10
-
-55
-
A
mA
mA
W
˚C
˚C
Tmb ≤ 25 ˚C
Storage temperature
-
Continuous junction temperature2
normal operation
Tsold
Lead temperature
during soldering
-
260
˚C
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VC
Electrostatic discharge capacitor
voltage
Human body model;
C = 250 pF; R = 1.5 kΩ
-
2
kV
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Inductive load turn-off
IDM = 8 A; VDD ≤ 20 V
EDSM
EDRM
Non-repetitive clamping energy
Repetitive clamping energy
T
mb ≤ 25 ˚C
-
-
100
20
mJ
mJ
Tmb ≤ 95 ˚C; f = 250 Hz
OVERLOAD PROTECTION LIMITING VALUE
With an adequate protection supply provided via the input pin, TOPFET can protect itself from two types of overload
- overtemperature and short circuit load.
SYMBOL PARAMETER
REQUIRED CONDITION
MIN.
MAX.
UNIT
VDS
Drain source voltage3
4 V ≤ VIS ≤ 5.5 V
0
35
V
THERMAL CHARACTERISTIC
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
2.5 3.1 K/W
Thermal resistance
Rth j-mb
Junction to mounting base
-
-
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch.
3 All control logic and protection functions are disabled during conduction of the source drain diode.
May 2001
2
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
PIP3104-P
OUTPUT CHARACTERISTICS
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
Off-state
CONDITIONS
MIN. TYP. MAX. UNIT
VIS = 0 V
V(CL)DSS
Drain-source clamping voltage ID = 10 mA
IDM = 1 A; tp ≤ 300 µs; δ ≤ 0.01
VDS = 40 V
50
50
-
-
V
V
60
70
IDSS
Drain source leakage current
-
-
-
100
10
µA
µA
Tmb = 25 ˚C
0.1
On-state
IDM = 3 A; tp ≤ 300 µs; δ ≤ 0.01
VIS ≥ 4.4 V
RDS(ON)
Drain-source resistance
-
-
-
68
190
100
mΩ
mΩ
Tmb = 25 ˚C
VIS ≥ 4 V
-
-
-
72
200
105
mΩ
mΩ
Tmb = 25 ˚C
OVERLOAD CHARACTERISTICS
-40˚C ≤ Tmb ≤ 150˚C unless otherwise specified.
SYMBOL PARAMETER
Short circuit load
CONDITIONS
MIN. TYP. MAX. UNIT
VDS = 13 V
ID
Drain current limiting
VIS = 5 V;
Tmb = 25˚C
Tmb = 25˚C
8
6
12
-
16
18
A
A
4.4 V ≤ VIS ≤ 5.5 V
4 V ≤ VIS ≤ 5.5 V
5
-
18
A
Overload protection
VIS = 5 V;
PD(TO)
TDSC
Overload power threshold
device trips if PD > PD(TO)
20
55
80
W
Characteristic time
which determines trip time1
200
350
600
µs
Overtemperature protection
Tj(TO)
Threshold junction
temperature2
150
170
-
˚C
1 Trip time td sc varies with overload dissipation PD according to the formula td sc ≈ TDSC / ln[ PD / PD(TO) ].
2 This is independent of the dV/dt of input voltage VIS.
May 2001
3
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
PIP3104-P
INPUT CHARACTERISTICS
The supply for the logic and overload protection is taken from the input.
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER
VIS(TO) Input threshold voltage
CONDITIONS
MIN. TYP. MAX. UNIT
VDS = 5 V; ID = 1 mA
0.6
1.1
-
2.4
2.1
V
V
Tmb = 25˚C
1.6
IIS
Input supply current
Input supply current
normal operation;
protection latched;
VIS = 5 V
VIS = 4 V
100
80
220
195
400
330
µA
µA
IISL
VIS = 5 V
VIS = 3 V
200
130
400
250
650
430
µA
µA
VISR
tlr
Protection reset voltage1
Latch reset time
reset time tr ≥ 100 µs
VIS1 = 5 V, VIS2 < 1 V
II = 1.5 mA
1.5
10
5.5
-
2
40
-
2.9
100
8.5
-
V
µs
V
V(CL)IS
RIG
Input clamping voltage
Input series resistance2
Tmb = 25˚C
33
kΩ
to gate of power MOSFET
SWITCHING CHARACTERISTICS
Tmb = 25 ˚C; VDD = 13 V; resistive load RL = 4 Ω. Refer to waveform figure and test circuit.
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
td on
tr
td off
tf
Turn-on delay time
Rise time
VIS = 5 V
-
-
-
-
10
20
30
20
20
40
60
40
µs
µs
µs
µs
Turn-off delay time
Fall time
VIS = 0 V
1 The input voltage below which the overload protection circuits will be reset.
2 Not directly measureable from device terminals.
May 2001
4
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
PIP3104-P
MECHANICAL DATA
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-leads
SOT78B
E
p
A
1
A
p
1
q
mounting
base
(2)
D
1
D
L
L
2
1
Q
b
1
L
1
2
3
(1)
b
w
M
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
L
max.
b
e
A
b
D
E
L
2
D
L
p
1
A
c
UNIT
p
q
Q
w
1
1
1
1
4.5
4.1
1.39
1.27
0.85
0.60
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
15.0
13.5
3.30
2.79
3.8
3.6
4.3
4.1
3.0
2.7
2.6
2.2
mm
0.4
3.0
2.54
Notes
1. The positional accuracy of the terminals is controlled within zone L max.
1
2. Mounting base configuration is not defined within the dimensions E and D
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
01-02-22
SOT78B
Fig.2. SOT78B (TO220AB) package1, pin 2 connected to mounting base.
1 Refer to mounting instructions for SOT78 (TO220) envelopes. Epoxy meets UL94 V0 at 1/8". Net mass: 2 g
May 2001
5
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
PIP3104-P
DEFINITIONS
DATA SHEET STATUS
DATA SHEET
STATUS1
PRODUCT
DEFINITIONS
STATUS2
Objective data
Development
This data sheet contains data from the objective specification for
product development. Philips Semiconductors reserves the right to
change the specification in any manner without notice
Preliminary data
Qualification
Production
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in ordere to improve the design and supply the best possible
product
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in
order to improve the design, manufacturing and supply. Changes will
be communicated according to the Customer Product/Process
Change Notification (CPCN) procedure SNW-SQ-650A
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 2001
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
1 Please consult the most recently issued datasheet before initiating or completing a design.
2 The product status of the device(s) described in this datasheet may have changed since this datasheet was published. The latest information is
available on the Internet at URL http://www.semiconductors.philips.com.
May 2001
6
Rev 1.000
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