PHN205-T [NXP]
TRANSISTOR 6400 mA, 30 V, 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, MS-012AA, FET General Purpose Small Signal;
| 型号： | PHN205-T |
| 厂家： | 
NXP |
| 描述： | TRANSISTOR 6400 mA, 30 V, 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, MS-012AA, FET General Purpose Small Signal 晶体 小信号场效应晶体管 开关 光电二极管 |
| 文件： | 总12页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
PHN205
Dual N-channel enhancement
mode
MOS transistor
1997 Oct 22
Product specification
Supersedes data of 1997 Jun 18
File under Discrete Semiconductors, SC13b
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
MOS transistor
PHN205
FEATURES
PINNING - SOT96-1 (SO8)
• High-speed switching
PIN
SYMBOL
DESCRIPTION
• No secondary breakdown
• Very low on-state resistance.
1
2
3
4
5
6
7
8
s1
g1
s2
g2
d2
d2
d1
d1
source 1
gate 1
source 2
gate 2
APPLICATIONS
drain 2
drain 2
drain 1
drain 1
• Motor and actuator driver
• Power management
• Synchronized rectification.
DESCRIPTION
Two N-channel enhancement mode MOS transistors in an
8-pin plastic SOT96-1 (SO8) package.
d
d
d
d
2
2
1
1
handbook, halfpage
8
5
4
CAUTION
The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.
1
s
g
s
g
1
2
1
2
MAM117
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Per N-channel
VDS
VSD
VGS
VGSth
ID
drain-source voltage (DC)
source-drain diode forward voltage
gate-source voltage (DC)
gate-source threshold voltage
drain current (DC)
−
−
−
1
−
−
−
30
V
IS = 1.25 A
1
V
V
V
A
±20
2.8
6.4
50
ID = 1 mA; VDS = VGS
Ts = 80 °C
RDSon
Ptot
drain-source on-state resistance
total power dissipation
ID = 3.2 A; VGS = 10 V
Ts = 80 °C
mΩ
3.5
W
1997 Oct 22
2
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
MOS transistor
PHN205
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Per N-channel
VDS
VGS
ID
drain-source voltage (DC)
gate-source voltage (DC)
−
−
−
−
−
−
−
−
30
V
V
A
A
±20
6.4
drain current (DC)
peak drain current
total power dissipation
Ts = 80 °C; note 1
note 2
IDM
Ptot
25
Ts = 80 °C; note 3
3.5
W
W
W
W
°C
°C
T
amb = 25 °C; note 4
amb = 25 °C; note 5
2.6
T
1.1
Tamb = 25 °C; note 6
1.5
Tstg
Tj
storage temperature
−65
−65
+150
+150
operating junction temperature
Source-drain diode
IS
source current (DC)
peak pulsed source current
Ts = 80 °C
−
−
3.5
14
A
A
ISM
note 2
Notes
1. Ts is the temperature at the soldering point of the drain lead.
2. Pulse width and duty cycle limited by maximum junction temperature.
3. Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 3.5 W at the same time.
4. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an Rth a-tp
(ambient to tie-point) of 27.5 K/W.
5. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an Rth a-tp
(ambient to tie-point) of 90 K/W.
6. Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on printed-circuit board with
an Rth a-tp (ambient to tie-point) of 90 K/W.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
Rth j-s
thermal resistance from junction to soldering point
20
K/W
1997 Oct 22
3
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
MOS transistor
PHN205
MGG340
MGG341
2
10
8
handbook, halfpage
handbook, halfpage
P
tot
I
D
(W)
(A)
6
t
=
p
10
10 µs
(1)
100 µs
4
2
0
1 ms
t
p
P
1
δ =
T
10 ms
t
t
100 ms
DC
p
T
−1
10
−1
2
10
1
10
10
0
50
100
150
V (V)
DS
T
(°C)
s
δ = 0.01; Ts = 80 °C.
(1) RDSon limitation.
Fig.2 Power derating curve.
Fig.3 SOAR.
1997 Oct 22
4
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
MOS transistor
PHN205
CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Per N-channel
V(BR)DSS
VGSth
IDSS
drain-source breakdown voltage VGS = 0; ID = 10 µA
30
1
−
−
−
−
−
−
−
−
−
−
−
−
−
V
gate-source threshold voltage
drain-source leakage current
gate leakage current
VGS = VDS; ID = 1 mA
VGS = 0; VDS = 24 V
VGS = ±20 V; VDS = 0
−
2.8
100
V
−
nA
IGSS
−
±100 nA
RDSon
drain-source on-state resistance VGS = 4.5 V; ID = 1.6 A
GS = 10 V; ID = 3.2 A
−
0.1
0.05
−
Ω
V
−
Ω
Ciss
Coss
Crss
QG
input capacitance
VGS = 0; VDS = 24 V; f = 1 MHz
VGS = 0; VDS = 24 V; f = 1 MHz
VGS = 0; VDS = 24 V; f = 1 MHz
VGS = 10 V; VDD = 15 V; ID = 3.2 A
VGS = 10 V; VDD = 15 V; ID = 3.2 A
VGS = 10 V; VDD = 15 V; ID = 3.2 A
450
200
100
15
1
pF
pF
pF
nC
nC
nC
ns
output capacitance
reverse transfer capacitance
total gate charge
−
−
−
QGS
QGD
td(on)
gate-source charge
gate-drain charge
−
5
−
turn-on delay time
VGS = 0 to 10 V; VDD = 15 V;
7
−
ID = 1 A; Rgen = 6 Ω; see Fig.4
tf
fall time
VGS = 0 to 10 V; VDD = 15 V;
ID = 1 A; Rgen = 6 Ω; see Fig.4
−
−
−
−
−
8
−
−
−
−
−
ns
ns
ns
ns
ns
ton
td(off)
tr
turn-on switching time
turn-off delay time
rise time
VGS = 0 to 10 V; VDD = 15 V;
ID = 1 A; Rgen = 6 Ω; see Fig.4
15
20
12
32
VGS = 10 to 0 V; VDD = 15 V;
ID = 1 A; Rgen = 6 Ω; see Fig.4
VGS = 10 to 0 V; VDD = 15 V;
ID = 1 A; Rgen = 6 Ω; see Fig.4
toff
turn-off switching time
VGS = 10 to 0 V; VDD = 15 V;
ID = 1 A; Rgen = 6 Ω; see Fig.4
Source-drain diode
VSD source-drain diode forward
VGD = 0; IS = 1.25 A
−
−
−
1
V
voltage
trr
reverse recovery time
IS = 1.25 A; di/dt = −100 A/µs
45
−
ns
1997 Oct 22
5
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
MOS transistor
PHN205
V
90 %
DD
V
in
R
L
10 %
0
V
out
90 %
V
out
V
in
10 %
0
t
t
d(on)
t
d(off)
t
t
t
r
f
MAM274
on
off
Fig.4 Switching time test circuit; input and output waveforms.
MGG342
2
10
R
th js
(K/W)
(1)
(2)
10
(3)
(4)
(5)
(6)
t
1
p
P
δ =
T
(7)
(8)
t
t
p
(9)
10
T
−1
10
−6
−5
−4
−3
−2
−1
10
10
10
10
10
1
t
(s)
p
(1) δ = 0.75.
(5) δ = 0.1.
(2) δ = 0.5.
(6) δ = 0.05.
(3) δ = 0.33.
(7) δ = 0.02.
(4) δ = 0.2.
(8) δ = 0.01.
(9) δ = 0.
Fig.5 Transient thermal resistance from junction to soldering point as a function of pulse time; typical values.
1997 Oct 22
6
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
MOS transistor
PHN205
MGG343
MGG344
1250
30
handbook, halfpage
handbook, halfpage
C
I
(pF)
(1)
D
(A)
1000
750
(2)
(3)
20
(1)
500
10
(4)
(5)
(2)
250
(3)
(6)
0
0
0
4
8
12
16
V
20
0
4
8
12
V
(V)
DS
(V)
DS
VGS = 0; f = 1 MHz; Tj = 25 °C.
(1) Ciss
(2) Coss
(3) Crss
.
Tamb = 25 °C; tp = 80 µs; δ = 0.
(1) VGS = 10 V.
.
(4) VGS = 4 V.
.
(2) VGS = 5 V.
(5) VGS = 3.5 V.
(6) VGS = 3 V.
(3)
VGS = 4.5 V.
Fig.6 Capacitance as a function of drain-source
voltage; typical values.
Fig.7 Output characteristics; typical values.
MGG345
MGG346
30
16
handbook, halfpage
handbook, halfpage
V
(V)
I
D
(A)
12
8
20
(1)
(2)
10
4
0
0
0
0
2
4
6
4
8
12
16
V
(V)
GS
Q
(nC)
G
VDD = 12.5 V; ID = 3.2 A; Tamb = 25 °C.
(1) VDS
(2) VGS
.
.
VDS = 10 V; Tamb = 25 °C; tp = 80 µs; δ = 0.
Fig.9 Gate-source voltage and drain-source
voltage as a function of total gate charge;
typical values.
Fig.8 Transfer characteristics; typical values.
1997 Oct 22
7
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
MOS transistor
PHN205
MGG347
MGG348
3
16
10
handbook, halfpage
handbook, halfpage
I
S
(A)
R
DSon
(mΩ)
(1)
(2)
(3)
(4)
(5)
12
(1)
(2)
(3)
2
8
4
0
10
10
0
0
0.4
0.8
1.2
2
4
6
8
10
(V)
V
(V)
SD
V
GS
VGD = 0.
Tamb = 25 °C; tp = 300 µs; δ = 0.
DS ≥ ID × RDSon
(1) ID = 0.5 A.
V
.
(1) Tamb = 150 °C; tp = 300 µs; δ = 0.
(2) Tamb= 25 °C; tp = 300 µs; δ = 0.
(3) Tamb= −65 °C; tp = 300 µs; δ = 0.
(2) ID = 1.6 A.
(3) ID = 3.2A.
(4) ID = 6.4 A.
(5) ID = 10 A.
Fig.11 Drain-source on-state resistance as a
function of gate-source voltage;
typical values.
Fig.10 Source current as a function of source-drain
diode forward voltage; typical values.
MGG359
MGG349
2
1.3
handbook, halfpage
handbook, halfpage
k
k
(1)
1.2
1.5
(2)
1.1
1
1
0.5
0
0.9
0.8
0.7
−100
−50
0
50
100
150
T (°C)
−100
−50
0
50
100
150
T (°C)
j
j
RDSon at Tj
k =
-----------------------------------------
VGSth at Tj
RDSon at 25 °C
k =
--------------------------------------
VGSth at 25°C
(1) RDSon at VGS = 10 V; ID = 3.2 A.
(2) RDSon at VGS = 4.5 V; ID = 1.6 A.
VGSth at VDS = VGS; ID = 1 mA.
Fig.12 Temperature coefficient of gate-source
threshold voltage as a function of junction
temperature; typical values.
Fig.13 Temperature coefficient of drain-source
on-resistance as a function of junction
temperature; typical values.
1997 Oct 22
8
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
MOS transistor
PHN205
PACKAGE OUTLINE
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-05-22
SOT96-1
076E03S
MS-012AA
1997 Oct 22
9
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
MOS transistor
PHN205
DEFINITIONS
Data Sheet Status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Oct 22
10
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
MOS transistor
PHN205
NOTES
1997 Oct 22
11
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© Philips Electronics N.V. 1997
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
137107/00/03/pp12
Date of release: 1997 Oct 22
Document order number: 9397 750 02978
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