PHN210 [NXP]
Dual N-channel enhancement mode TrenchMOS transistor; 双N沟道增强模式的TrenchMOS晶体管
| 型号： | PHN210 |
| 厂家： | 
NXP |
| 描述： | Dual N-channel enhancement mode TrenchMOS transistor |
| 文件： | 总7页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOSTM transistor
PHN210
FEATURES
SYMBOL
QUICK REFERENCE DATA
• Dual device
VDS = 30 V
d1 d1
d2 d2
• Low threshold voltage
• Fast switching
ID = 3.4 A
• Logic level compatible
• Surface mount package
RDS(ON) ≤ 100 mΩ (VGS = 10 V)
RDS(ON) ≤ 200 mΩ (VGS = 4.5 V)
s1
g1
s2
g2
GENERAL DESCRIPTION
PINNING
SOT96-1
8
7
6
5
Dual N-channel enhancement
mode field-effect transistor in a
plastic envelope using ’trench’
technology.
PIN
DESCRIPTION
source 1
gate 1
1
2
Applications:-
• Motor and relay drivers
• d.c. to d.c. converters
• Logic level translator
3
source 2
gate 2
pin 1 index
4
1
2
3
4
The PHN210 is supplied in the
SOT96-1 (SO8) surface mounting
package.
5,6
7,8
drain 2
drain 1
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
Repetitive peak drain-source
voltage
Tj = 25 ˚C to 150˚C
-
30
V
VDS
VDGR
VGS
ID
Continuous drain-source voltage
Drain-gate voltage
-
-
-
-
-
-
-
-
30
30
V
V
V
A
A
A
A
A
RGS = 20 kΩ
Gate-source voltage
± 20
3.4
2.8
2.4
1.9
14
Drain current per MOSFET1
Ta = 25 ˚C
Ta = 70 ˚C
Ta = 25 ˚C
Ta = 70 ˚C
Ta = 25 ˚C
ID
Drain current per MOSFET (both
MOSFETs conducting)1
Drain current per MOSFET (pulse
peak value)
IDM
Ptot
Total power dissipation (either or
both MOSFETs conducting)1
Storage & operating temperature
Ta = 25 ˚C
Ta = 70 ˚C
-
-
2
1.3
150
W
W
˚C
Tstg, Tj
- 65
1 Surface mounted on FR4 board, t ≤ 10 sec
February 1999
1
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOSTM transistor
PHN210
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-a
Thermal resistance junction Surface mounted, FR4 board, t ≤ 10 sec
to ambient
-
62.5
K/W
Rth j-a
Thermal resistance junction Surface mounted, FR4 board
to ambient
150
-
K/W
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
EAS Non-repetitive avalanche
CONDITIONS
MIN.
MAX.
UNIT
Unclamped inductive load, IAS = 3.4 A;
tp = 0.2 ms; Tj prior to avalanche = 25˚C;
-
13
mJ
energy (per MOSFET)
VDD ≤ 15 V; RGS = 50 Ω; VGS = 10 V
IAS
Non-repetitive avalanche
current (per MOSFET)
-
3.4
A
ELECTRICAL CHARACTERISTICS
Tj= 25˚C, per MOSFET unless otherwise specified
SYMBOL PARAMETER CONDITIONS
V(BR)DSS Drain-source breakdown
MIN. TYP. MAX. UNIT
VGS = 0 V; ID = 10 µA;
30
27
1
0.4
-
-
-
-
2
3.5
2
-
-
2
-
-
-
V
V
V
V
V
mΩ
mΩ
mΩ
S
voltage
Gate threshold voltage
Tj = -55˚C
VGS(TO)
VDS = VGS; ID = 1 mA
2.8
-
3.2
100
200
170
-
Tj = 150˚C
Tj = -55˚C
RDS(ON)
Drain-source on-state
resistance
VGS = 10 V; ID = 2.2 A
VGS = 4.5 V; ID = 1 A
80
120
-
4.5
-
VGS = 10 V; ID = 2.2 A; Tj = 150˚C
VDS = 20 V; ID = 2.2 A
VGS = 10 V; VDS = 1 V;
gfs
ID(ON)
Forward transconductance
On-state drain current
-
A
VGS = 4.5 V; VDS = 5 V
-
-
A
IDSS
IGSS
Zero gate voltage drain
current
Gate source leakage current VGS = ±20 V; VDS = 0 V
VDS = 24 V; VGS = 0 V;
VDS = 24 V; VGS = 0 V; Tj = 150˚C
-
-
-
10
0.6
10
100
10
100
nA
µA
nA
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 2.3 A; VDD = 15 V; VGS = 10 V
-
-
-
6
0.7
0.7
-
-
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 20 V; RD = 18 Ω;
VGS = 10 V; RG = 6 Ω
Resistive load
-
-
-
-
6
8
21
15
-
-
-
-
ns
ns
ns
ns
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from drain lead to centre of die
Measured from source lead to source
bond pad
-
-
2.5
5
-
-
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 20 V; f = 1 MHz
-
-
-
250
88
54
-
-
-
pF
pF
pF
February 1999
2
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOSTM transistor
PHN210
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C, per MOSFET unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source diode
Ta = 25 ˚C
-
-
-
-
-
2.2
14
A
A
V
current (per MOSFET)
Pulsed source diode current
(per MOSFET)
ISM
VSD
Diode forward voltage
IF = 1.25 A; VGS = 0 V
0.82
1.2
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 1.25 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 25 V
-
-
69
55
-
-
ns
nC
Normalised Power Derating
PD%
120
110
100
90
80
70
60
50
40
30
20
10
0
PHN210
Peak Pulsed Drain Current, IDM (A)
RDS(on) = VDS/ ID
100
10
tp = 10 us
100 us
1 ms
1
10 ms
100 ms
0.1
0.01
10 s
0
20
40
60
80
100
120
140
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Tamb /
C
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Ta)
Fig.3. Safe operating area. Ta = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Normalised Current Derating
ID%
120
110
100
90
80
70
60
50
40
30
20
10
0
PHN210
Peak Pulsed Drain Current, IDM (A)
100
D = 0.5
0.2
10
1
0.1
0.05
0.02
P
D = tp/T
D
tp
0.1
single pulse
T
0.01
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
Pulse width, tp (s)
0
20
40
60
80
100
120
140
Ambient temperature, Tamb (C)
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Ta); conditions: VGS ≥ 10 V
Fig.4. Transient thermal impedance.
Zth j-a = f(t); parameter D = tp/T
February 1999
3
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOSTM transistor
PHN210
Transconductance, gfs (S)
6
5
4
3
2
1
0
Drain Current, ID (A)
10
5V
VGS = 20 V
10 V
9
8
7
6
5
4
3
2
1
0
Tj = 25 C
150 C
Tj = 25 C
4.2 V
4 V
3.8 V
3.6 V
3.4 V
3.2 V
0
1
2
3
4
5
6
7
8
9
10
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Drain-Source Voltage, VDS (V)
Drain current, ID (A)
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID) ; parameter Tj
a
Normalised RDS(ON) = f(Tj)
Drain-Source On Resistance, RDS(on) (Ohms)
0.5
2
3.6 V
3.8V 4 V
3.2 V
3.4 V
4.2 V
Tj = 25 C
0.4
0.3
0.2
0.1
0
1.5
1
VGS =5 V
10V
0.5
20V
0
-50
0
50
Tj / C
100
150
0
1
2
3
4
5
6
7
8
9
10
Drain Current, ID (A)
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj)
VGS(TO) / V
4
Drain current, ID (A)
10
VDS > ID X RDS(ON)
9
8
7
6
5
4
3
2
1
0
3
2
1
0
max.
typ.
Tj = 25 C
150 C
min.
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
-60 -40 -20
0
20 40 60 80 100 120 140
Gate-source voltage, VGS (V)
Tj /
C
Fig.7. Typical transfer characteristics.
ID = f(VGS); parameter Tj
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
February 1999
4
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOSTM transistor
PHN210
Sub-Threshold Conduction
1E-01
Source-Drain Diode Current, IF (A)
VGS = 0 V
10
9
8
7
6
5
4
3
2
1
0
1E-02
min
typ
max
150 C
1E-03
1E-04
1E-05
1E-06
Tj = 25 C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
Drain-Source Voltage, VSDS (V)
0
1
2
3
4
5
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Non-repetitive Avalanche current, IAS (A)
PHN210
25 C
10
Capacitances, Ciss, Coss, Crss (pF)
1000
Ciss
Tj prior to avalanche =125 C
VDS
1
100
10
Coss
Crss
tp
ID
0.1
1E-06
1E-05
1E-04
1E-03
1E-02
0.1
1
10
100
Avalanche time, tp (s)
Drain-Source Voltage, VDS (V)
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tp);
unclamped inductive load
Gate-source voltage, VGS (V)
15
14 ID = 2.3A
13
12
Tj = 25 C
VDD = 15 V
11
10
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10
Gate charge, QG (nC)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
February 1999
5
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOSTM transistor
PHN210
MECHANICAL DATA
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A
)
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
0.25
0.01
0.25
0.1
1.75
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-05-22
SOT96-1
076E03S
MS-012AA
Fig.16. SOT96 surface mounting package.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to Integrated Circuit Packages, Data Handbook IC26.
3. Epoxy meets UL94 V0 at 1/8".
February 1999
6
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOSTM transistor
PHN210
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
February 1999
7
Rev 1.000
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