PHD14NQ20T [NXP]
TrenchMOS standard level FET; 的TrenchMOS标准水平FET
| 型号： | PHD14NQ20T |
| 厂家： | 
NXP |
| 描述： | TrenchMOS standard level FET |
| 文件： | 总14页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PHP/PHB/PHD14NQ20T
TrenchMOS™ standard level FET
Rev. 03 — 11 March 2002
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHP14NQ20T in SOT78 (TO-220AB)
PHB14NQ20T in SOT404 (D2-PAK)
PHD14NQ20T in SOT428 (D-PAK).
1.2 Features
■ Low on-state resistance
■ Fast switching
1.3 Applications
■ DC to DC converters
■ General purpose switching
1.4 Quick reference data
■ VDS = 200 V
■ ID = 14 A
■ RDSon ≤ 230 mΩ
■ PD = 125 W
2. Pinning information
Table 1:
Pinning - SOT78, SOT404, SOT428, simplified outline and symbol
Pin
1
Description
gate (g)
Simplified outline
Symbol
d
s
mb
mb
mb
[1]
2
drain (d)
3
source (s)
g
mb
mounting base,
connected to
drain (d)
MBB076
2
2
1
3
1
3
Top view
MBK091
MBK116
MBK106
1
2 3
SOT404 (D2-PAK)
SOT428 (D-PAK)
SOT78 (TO-220AB)
[1] It is not possible to make connection to pin 2 of the SOT404 or SOT428 packages.
PHP/PHB/PHD14NQ20T
Philips Semiconductors
TrenchMOS™ standard level FET
3. Limiting values
Table 2:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Tj = 25 to 175 oC
Tj = 25 to 175 oC; RGS = 20 kΩ
Min
Max
200
200
±20
Unit
V
VDS
VDGR
VGS
ID
drain-source voltage (DC)
-
-
-
drain-gate voltage (DC)
gate-source voltage
drain current (DC)
V
V
VGS = 10 V; Figure 2 and 3
Tmb = 25 °C
-
-
-
14
10
56
A
A
A
Tmb = 100 °C
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs;
Figure 3
Ptot
Tstg
Tj
total power dissipation
storage temperature
Tmb = 25 °C; Figure 1
-
125
W
−55
−55
+175
+175
°C
°C
operating junction temperature
Source-drain diode
IS
source (diode forward) current (DC)
peak source (diode forward) current
Tmb = 25 °C
-
-
14
56
A
A
ISM
Tmb = 25 °C; pulsed; tp ≤ 10 µs
Avalanche ruggedness
EDS(ALS) non-repetitive avalanche energy
IDS(ALM) peak non-repetitive avalanche current
unclamped inductive load; ID = 14 A;
tp = 20 µs; VDD ≤ 25 V; RGS = 50 Ω;
VGS = 10 V; starting Tj = 25 °C;
Figure 15
-
-
70
14
mJ
A
9397 750 09535
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 11 March 2002
2 of 14
PHP/PHB/PHD14NQ20T
Philips Semiconductors
TrenchMOS™ standard level FET
03aa16
03aa24
120
120
P
I
der
der
(%)
(%)
80
80
40
40
0
0
0
50
100
150
200
(oC)
0
50
100
150
200
(oC)
T
mb
T
mb
V
GS ≥ 10 V
Ptot
Pder
=
× 100%
-----------------------
ID
P
°
tot(25 C)
Ider
=
× 100%
-------------------
I
°
D(25 C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
003aaa219
3
10
I
D
(A)
R
= V / I
DS D
DSon
2
10
t
=
p
1 µs
10 µs
10
100 µs
1 ms
DC
10 ms
100 ms
1
-1
10
3
10
2
1
10
10
V
(V)
DS
Tmb = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 09535
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 11 March 2002
3 of 14
PHP/PHB/PHD14NQ20T
Philips Semiconductors
TrenchMOS™ standard level FET
4. Thermal characteristics
Table 3:
Thermal characteristics
Symbol Parameter
Conditions
Min Typ Max Unit
Rth(j-mb) thermal resistance from junction to mounting Figure 4
base
-
-
1.2 K/W
Rth(j-a)
thermal resistance from junction to ambient
vertical in still air; SOT78 package
-
-
60
50
-
-
K/W
K/W
SOT404 and SOT428 packages;
SOT404 minimum footprint; mounted on
a PCB
4.1 Transient thermal impedance
003aaa220
10
Z
th (j-mb)
(K/W)
1
δ = 0.5
δ = 0.2
δ = 0.1
-1
t
p
T
δ = 0.05
δ = 0.02
10
P
δ
=
single pulse
t
t
p
T
1
-2
10
-6
10
-5
10
-4
-3
10
-2
10
-1
10
10
10
t
(s)
p
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 09535
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 11 March 2002
4 of 14
PHP/PHB/PHD14NQ20T
Philips Semiconductors
TrenchMOS™ standard level FET
5. Characteristics
Table 4:
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Static characteristics
V(BR)DSS drain-source breakdown voltage
Characteristics
Conditions
Min
Typ
Max
Unit
ID = 250 µA; VGS = 0 V
Tj = 25 °C
200
178
-
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage
drain-source leakage current
ID = 1 mA; VDS = VGS
Figure 9
;
Tj = 25 °C
Tj = 175 °C
Tj = −55 °C
2
1
-
3
-
4
-
V
V
V
-
6
IDSS
VDS = 200 V; VGS = 0 V
Tj = 25 °C
-
-
-
0.05
-
10
µA
µA
nA
Tj = 175 °C
500
100
IGSS
gate-source leakage current
VGS = ±10 V; VDS = 0 V
10
RDSon
drain-source on-state resistance
VGS = 10 V; ID = 7 A;
Figure 7 and 8
Tj = 25 °C
-
-
150
-
230
633
mΩ
mΩ
Tj = 175 °C
Dynamic characteristics
gfs
forward transconductance
VDS = 25 V; ID = 7 A;
Figure 14
6
12.1
-
S
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
ID = 14 A; VDD = 160 V;
VGS = 10 V; Figure 13
-
-
-
-
-
-
-
-
-
-
38
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
4
13.3
1500
128
60
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Figure 11
VDD = 30 V; RD = 10 Ω;
VGS = 10 V; RGS = 50 Ω;
Rgen = 50 Ω
25
40
td(off)
tf
turn-off delay time
fall time
83
31
Source-drain diode
VSD
source-drain (diode forward)
voltage
IS = 14 A; VGS = 0 V;
Figure 12
-
1.0
1.5
V
trr
reverse recovery time
recovered charge
IS = 14 A;
dIS/dt = −100 A/µs;
VGS = 0 V; VR = 30 V
-
-
135
690
-
-
ns
Qr
nC
9397 750 09535
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 11 March 2002
5 of 14
PHP/PHB/PHD14NQ20T
Philips Semiconductors
TrenchMOS™ standard level FET
003aaa221
003aaa223
30
30
V
= 10 V
GS
I
I
D
D
(A)
(A)
24
6 V
20
16
5.5 V
10
ο
T = 175
j
C
8
0
ο
T = 25 C
j
5 V
4.5 V
0
6
8
4
0
2
4
6
8
10
(V)
2
0
V
(V)
GS
V
DS
Tj = 25 °C
Tj = 25 °C and 175 °C; VDS > ID × RDSon
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
003aaa222
003aaa225
0.8
3
5.5 V
5 V
4.5 V
R
a
DSon
(Ω)
2.5
0.6
2
0.4
6 V
1.5
1
V
= 10 V
GS
0.2
0
0.5
0
5
10
15
20
-60
20
100
180
ο
( C)
I
(A)
T
D
j
Tj = 25 °C
RDSon
-----------------------------
RDSon(25°C)
a =
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain source on-state resistance
factor as a function of junction temperature.
9397 750 09535
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 11 March 2002
6 of 14
PHP/PHB/PHD14NQ20T
Philips Semiconductors
TrenchMOS™ standard level FET
03aa35
003aaa226
-1
10
5
I
D
V
GS(th)
(A)
(V)
4
-2
-3
-4
-5
-6
10
max
min
typ
max
10
10
10
10
3
2
1
0
typ
min
-100
0
100
200
ο
T ( C)
0
2
4
6
j
V
GS
(V)
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
003aaa229
003aaa227
30
4
10
I
S
C
(pF)
(A)
C
iss
3
20
10
ο
T = 175
C
j
C
oss
10
2
10
C
rss
ο
T = 25
C
j
0
10
0
0.4
0.8
1.2
0
10
20
30
40
V
(V)
SD
V
(V)
DS
VGS = 0 V; f = 1 MHz
Tj = 25 °C and 175 °C; VGS = 0 V
Fig 11. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
Fig 12. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
9397 750 09535
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 11 March 2002
7 of 14
PHP/PHB/PHD14NQ20T
Philips Semiconductors
TrenchMOS™ standard level FET
003aaa224
003aaa228
12
20
g
fs
V
GS
(S)
(V)
16
V
= 40 V
DD
8
12
V
= 160 V
DD
8
4
4
0
0
0
10
20
30
0
10
20
30
40
I
(A)
D
Q
(nC)
G
ID = 15 A; VDD = 40 V and 160 V
VDS = 25 V
Fig 13. Gate-source voltage as a function of gate
charge; typical values.
Fig 14. Forward transconductance as a function of
drain current; typical values.
003aaa230
2
10
I
AS
(A)
10
ο
25
C
ο
T prior to avalanche = 150
C
j
1
-1
10
-3
-2
10
-1
10
10
1
10
t
(ms)
p
Unclamped inductive load; VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; starting Tj = 25 °C and 150 °C
Fig 15. Non-repetitive avalanche ruggedness current as a function of pulse duration; typical values.
9397 750 09535
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 11 March 2002
8 of 14
PHP/PHB/PHD14NQ20T
Philips Semiconductors
TrenchMOS™ standard level FET
6. Package outline
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB
SOT78
E
p
A
A
1
q
mounting
base
D
1
D
(1)
L
L
2
1
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
b
L
max.
(1)
2
e
A
b
D
E
L
D
L
1
A
c
UNIT
p
q
Q
1
1
1
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
15.0
13.5
3.30
2.79
3.8
3.6
3.0
2.7
2.6
2.2
mm
3.0
2.54
Note
1. Terminals in this zone are not tinned.
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SC-46
00-09-07
01-02-16
SOT78
3-lead TO-220AB
Fig 16. SOT78 (TO-220AB).
9397 750 09535
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 11 March 2002
9 of 14
PHP/PHB/PHD14NQ20T
Philips Semiconductors
TrenchMOS™ standard level FET
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads
(one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
99-06-25
01-02-12
SOT404
Fig 17. SOT404 (D2-PAK).
9397 750 09535
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 11 March 2002
10 of 14
PHP/PHB/PHD14NQ20T
Philips Semiconductors
TrenchMOS™ standard level FET
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
y
A
A
E
A
2
A
b
E
1
1
2
mounting
base
D
1
D
H
E
L
2
2
L
1
L
1
3
b
b
w
M
A
c
1
e
e
1
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
L
y
1
1
A
A
A
b
D
E
E
H
UNIT
b
b
c
e
e
1
L
L
w
2
1
2
1
E
1
2
max.
min.
min.
0.65
0.45
0.89
0.71
0.9
0.5
2.38
2.22
0.93
0.73
1.1
0.9
5.46
5.26
0.4 6.22
0.2 5.98
6.73
6.47
10.4 2.95
9.6
2.55
4.81
4.45
mm
4.57
0.2
0.2
4.0
2.285
0.5
Note
1. Measured from heatsink back to lead.
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
JEITA
99-09-13
01-12-11
SOT428
TO-252
SC-63
Fig 18. SOT428 (D-PAK).
9397 750 09535
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 11 March 2002
11 of 14
PHP/PHB/PHD14NQ20T
Philips Semiconductors
TrenchMOS™ standard level FET
7. Revision history
Table 5:
Revision history
CPCN
Rev Date
Description
03 20020311
02 20020306
01 19991001
Product data; third version. Supersedes data of 6 March 2002.
Modifications:
• Correction to product title: PHD14NQ20T.
Product data; second version.Supersedes initial version of 1 October 1999.
Modifications:
• PHD14NQ20T added.
Product data; initial version
9397 750 09535
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 11 March 2002
12 of 14
PHP/PHB/PHD14NQ20T
Philips Semiconductors
TrenchMOS™ standard level FET
8. Data sheet status
Data sheet status[1]
Product status[2]
Definition
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips Semiconductors
reserves the right to change the specification in any manner without notice.
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published at a
later date. Philips Semiconductors reserves the right to change the specification without notice, in order to
improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the right to
make changes at any time in order to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change Notification (CPCN) procedure
SNW-SQ-650A.
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
9. Definitions
10. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
11. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
13 of 14
9397 750 09535
Product data
Rev. 03 — 11 March 2002
PHP/PHB/PHD14NQ20T
Philips Semiconductors
TrenchMOS™ standard level FET
Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
4
4.1
5
6
7
8
9
10
11
© Koninklijke Philips Electronics N.V. 2002.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 11 March 2002
Document order number: 9397 750 09535
相关型号：
PHD16D-H
Board Connector, 16 Contact(s), 2 Row(s), Male, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Natural Insulator, Receptacle
AUK
PHD18D-H
Board Connector, 18 Contact(s), 2 Row(s), Male, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Natural Insulator, Receptacle
AUK
PHD18H-H
Board Connector, 18 Contact(s), 2 Row(s), Female, 0.079 inch Pitch, Wire Terminal, Locking, Plug
AUK
©2020 ICPDF网 联系我们和版权申明