PHD101NQ03LT [NXP]
TrenchMOS⑩ logic level FET; 的TrenchMOS ™逻辑电平FET
| 型号： | PHD101NQ03LT |
| 厂家： | 
NXP |
| 描述： | TrenchMOS⑩ logic level FET |
| 文件： | 总13页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PHB/PHD101NQ03LT
TrenchMOS™ logic level FET
Rev. 02 — 25 February 2003
Product data
1. Description
N-channel logic level field-effect power transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHB101NQ03LT in SOT404 (D2-PAK)
PHD101NQ03LT in SOT428 (D-PAK).
2. Features
■ Low gate charge
■ Low on-state resistance.
3. Applications
■ Optimized as a control FET in DC to DC convertors
4. Pinning information
Table 1: Pinning - SOT404, SOT428 simplified outline and symbol
Pin Description
Simplified outline
Symbol
1
2
3
gate (g)
d
s
mb
mb
[1]
drain (d)
source (s)
g
mb mounting base,
connected to drain (d)
MBB076
2
2
1
3
1
3
Top view
MBK091
MBK116
SOT404 (D2-PAK)
SOT428 (D-PAK)
[1] It is not possible to make connection to pin 2 of the SOT404 and SOT428 packages.
PHB/PHD101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
5. Quick reference data
Table 2: Quick reference data
Symbol Parameter
Conditions
Typ
Max
30
Unit
V
VDS
ID
drain-source voltage (DC)
drain current (DC)
25 ≤ Tj ≤ 175 °C
Tmb = 25 °C; VGS = 5 V
Tmb = 25 °C
-
-
75
A
Ptot
Tj
total power dissipation
junction temperature
-
166
175
5.5
7.0
W
-
°C
mΩ
mΩ
RDSon
drain-source on-state resistance
Tj = 25 °C; VGS = 10 V; ID = 25 A
Tj = 25 °C; VGS = 5 V; ID = 25 A
4.5
5.8
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
30
Unit
V
VDS
drain-source voltage (DC)
25 ≤ Tj ≤ 175 °C
-
-
-
-
VDGR
VGS
drain-gate voltage (DC)
gate-source voltage (DC)
gate-source voltage
25 ≤ Tj ≤ 175 °C; RGS = 20 kΩ
30
V
±20
±25
V
VGSM
tp ≤ 50 µs; pulsed;
V
duty cycle 25%; Tj ≤ 150 °C
ID
drain current (DC)
Tmb = 25 °C; VGS = 5 V; Figure 2 and 3
Tmb = 100 °C; VGS = 5 V; Figure 2
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
Tmb = 25 °C; Figure 1
-
75
A
-
75
A
IDM
Ptot
Tstg
Tj
peak drain current
-
240
166
+175
+175
A
total power dissipation
storage temperature
junction temperature
-
W
°C
°C
−55
−55
Source-drain diode
IS
source (diode forward) current (DC) Tmb = 25 °C
-
-
75
A
A
ISM
peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs
240
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 43 A;
tp = 0.19 ms; VDD ≤ 15 V; RGS = 50 Ω;
VGS = 10 V; starting Tj = 25 °C
-
185
mJ
9397 750 10929
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 25 February 2003
2 of 13
PHB/PHD101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03aa16
03ai19
120
120
P
I
der
der
(%)
(%)
80
80
40
40
0
0
0
50
100
150
200
( C)
0
50
100
150
200
( C)
T
°
T
mb
°
mb
Ptot
ID
Pder
=
× 100%
Ider
=
× 100%
----------------------
------------------
P
I
°
°
tot(25 C)
D(25 C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
03ai21
3
10
I
D
Limit R
DSon
= V
/ I
DS D
(A)
t
p
= 10 s
µ
100
s
µ
2
10
DC
1 ms
10
10 ms
1
2
10
1
10
V
(V)
DS
Tmb = 25 °C; IDM is single pulse; VGS = 10V.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 10929
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 25 February 2003
3 of 13
PHB/PHD101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
7. Thermal characteristics
Table 4: Thermal characteristics
Symbol Parameter
Conditions
Min Typ Max Unit
Rth(j-mb) thermal resistance from junction to mounting base Figure 4
-
-
0.9 K/W
Rth(j-a)
thermal resistance from junction to ambient
SOT428
mounted on a PCB;
SOT428 minimum footprint;
vertical in still air
-
75
-
-
K/W
K/W
SOT404 and SOT428
mounted on a PCB;
SOT404 minimum footprint;
vertical in still air
-
50
7.1 Transient thermal impedance
03ai20
10
Z
th(j-mb)
(K/W)
1
= 0.5
δ
0.2
0.1
-1
-2
-3
10
10
10
0.05
0.02
t
p
P
δ =
T
single pulse
t
t
p
T
-5
10
-4
10
-3
10
-2
-1
10
10
1
t
p
(s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 10929
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 25 February 2003
4 of 13
PHB/PHD101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
8. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified
Symbol Parameter
Conditions
Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 0.25 mA; VGS = 0 V
Tj = 25 °C
30
27
-
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage
drain-source leakage current
ID = 1 mA; VDS = VGS; Figure 9
Tj = 25 °C
1
1.9
2.5
-
V
V
V
Tj = 175 °C
0.6
-
-
-
Tj = −55 °C
2.9
IDSS
VDS = 30 V; VGS = 0 V
Tj = 25 °C
-
-
-
0.05
-
1
µA
Tj = 175 °C
500 µA
IGSS
gate-source leakage current
VGS = ±20 V; VDS = 0 V
VGS = 5 V; ID = 25 A; Figure 7 and 8
Tj = 25 °C
10
100 nA
RDSon
drain-source on-state resistance
-
-
5.8
7
mΩ
Tj = 175 °C
10.5 12.6 mΩ
VGS = 10 V; ID = 25 A; Figure 7
Tj = 25 °C
-
4.5
5.5
mΩ
Dynamic characteristics
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
ID = 50 A; VDD = 15 V; VGS = 5 V; Figure 13
VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11
-
-
-
-
-
-
-
-
-
-
23
10.5
8
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
2180 -
600
225
23
-
-
-
-
-
-
VDD = 15 V; ID = 25 A; VGS = 4.5 V;
RG = 5.6 Ω; resistive load
90
td(off)
tf
turn-off delay time
fall time
37
33
Source-drain diode
VSD
trr
source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12
-
-
-
0.85 1.2
V
reverse recovery time
recovered charge
IS = 10 A; dIS/dt = −100 A/µs; VGS = 0 V
37
33
-
-
ns
nC
Qr
9397 750 10929
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 25 February 2003
5 of 13
PHB/PHD101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03ai22
03ai24
80
80
10 V 5 V 4.5 V
4 V
T = 25 C
°
V
> I x R
D
j
DS
DSon
I
I
D
D
(A)
(A)
3.8 V
3.6 V
60
60
40
20
0
40
20
0
3.4 V
3.2 V
175 C
3 V
T = 25 C
°
°
j
V
= 2.8 V
GS
0.8
0
0.2
0.4
0.6
1
0
1
2
3
4
(V)
V
V
(V)
GS
DS
Tj = 25 °C
Tj = 25 °C and 175 °C; VDS > ID x RDSon
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
03ai23
03af18
16
2
T = 25 C
°
j
R
DSon
(m
V
= 3.8 V
GS
a
)
Ω
12
1.5
4 V
8
1
0.5
0
4.5 V
5V
10 V
4
0
0
20
40
60
80
(A)
-60
0
60
120
180
I
D
°
T ( C)
j
Tj = 25 °C
RDSon
a =
---------------------------
RDSon(25 C)
°
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
9397 750 10929
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 25 February 2003
6 of 13
PHB/PHD101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03ai29
03ai28
-1
-2
-3
-4
-5
-6
3.2
10
I
D
V
GS(th)
(V)
(A)
10
10
10
10
10
max
typ
2.4
1.6
0.8
0
min
typ
max
min
-60
0
60
120
180
0
0.8
1.6
2.4
3.2
T ( C)
°
V
(V)
j
GS
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
03ai26
4
10
C
(pF)
C
iss
3
10
C
C
oss
rss
2
10
-1
2
10
10
1
10
V
(V)
DS
VGS = 0 V; f = 1 MHz
Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.
9397 750 10929
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 25 February 2003
7 of 13
PHB/PHD101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03ai25
03ai27
80
10
I
= 50 A
V
D
V
= 0 V
GS
(V)
GS
I
S
T = 25 C
°
(A)
j
8
6
4
2
0
V
= 15 V
60
DD
40
20
0
T = 25 C
175 C
°
°
j
0
0.3
0.6
0.9
1.2
(V)
0
10
20
30
40
50
(nC)
V
SD
Q
G
Tj = 25 °C and 175 °C; VGS = 0 V
ID = 50 A; VDD = 15 V
Fig 12. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
Fig 13. Gate-source voltage as a function of gate
charge; typical values.
9397 750 10929
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 25 February 2003
8 of 13
PHB/PHD101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
9. Package outline
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads
(one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
99-06-25
01-02-12
SOT404
Fig 14. SOT404 (D2-PAK)
9397 750 10929
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 25 February 2003
9 of 13
PHB/PHD101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
y
A
A
E
A
2
A
b
E
1
1
2
mounting
base
D
1
D
H
E
L
2
2
L
1
L
1
3
b
b
w
M
A
c
1
e
e
1
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
L
y
1
1
A
A
A
b
D
E
E
H
UNIT
b
b
c
e
e
1
L
L
w
2
1
2
1
E
1
2
max.
min.
min.
0.65
0.45
0.89
0.71
0.9
0.5
2.38
2.22
0.93
0.73
1.1
0.9
5.46
5.26
0.4 6.22
0.2 5.98
6.73
6.47
10.4 2.95
9.6
2.55
4.81
4.45
mm
4.57
0.2
0.2
4.0
2.285
0.5
Note
1. Measured from heatsink back to lead.
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
JEITA
99-09-13
01-12-11
SOT428
TO-252
SC-63
Fig 15. SOT428 (D-PAK).
9397 750 10929
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 25 February 2003
10 of 13
PHB/PHD101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
10. Revision history
Table 6: Revision history
Rev Date
CPCN
-
Description
02 20030225
Product data (9397 750 10929)
Modifications:
Removal of PHP101NQ03LT (Now in separate data sheet).
Section 7 “Thermal characteristics” Clarification of thermal resistance table.
Graphics updated to latest standard.
•
•
•
01 20020220
-
Product data (9397 750 09307); initial version
9397 750 10929
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 25 February 2003
11 of 13
PHB/PHD101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
11. Data sheet status
[1]
[2][3]
Level Data sheet status
Product status
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
12. Definitions
13. Disclaimers
Short-form specification — The data in
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
a
short-form specification is
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
14. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
12 of 13
9397 750 10929
Product data
Rev. 02 — 25 February 2003
PHB/PHD101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
3
4
5
6
7
7.1
8
9
10
11
12
13
14
© Koninklijke Philips Electronics N.V. 2003.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 25 February 2003
Document order number: 9397 750 10929
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