PHD11N06LT [NXP]
TrenchMOS transistor Logic level FET; 的TrenchMOS晶体管逻辑电平场效应管
| 型号： | PHD11N06LT |
| 厂家： | 
NXP |
| 描述： | TrenchMOS transistor Logic level FET |
| 文件： | 总9页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHB11N06LT, PHD11N06LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
VDSS = 55 V
d
s
ID = 11 A
R
DS(ON) ≤ 150 mΩ (VGS = 5 V)
g
R
DS(ON) ≤ 130 mΩ (VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHB11N06LT is supplied in the SOT404 surface mounting package.
The PHD11N06LT is supplied in the SOT428 surface mounting package.
PINNING
SOT428
SOT404
PIN
DESCRIPTION
tab
tab
1
2
gate
drain 1
3
source
drain
2
2
tab
1
3
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
-
-
-
-
-
-
-
55
55
± 13
11
7.6
44
V
V
V
A
A
A
W
˚C
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
36
175
- 55
1 It is not possible to make contact to pin 2 of the SOT404 or SOT428 package
September 1998
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHB11N06LT, PHD11N06LT
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VC
Electrostatic discharge
capacitor voltage, all pins
Human body model (100 pF, 1.5 kΩ)
-
2
kV
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-mb
Thermal resistance junction
to mounting base
-
4.17
K/W
Rth j-a
Thermal resistance junction SOT78 package, in free air
60
50
-
-
K/W
K/W
to ambient
SOT428 and SOT404 package, pcb
mounted, minimum footprint
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
V(BR)GSS
VGS(TO)
Drain-source breakdown
voltage
Gate-source breakdown
voltage
VGS = 0 V; ID = 0.25 mA;
55
50
10
-
-
-
-
-
-
V
V
V
Tj = -55˚C
IG = ±1 mA;
Gate threshold voltage
VDS = VGS; ID = 1 mA
1.0
0.5
-
-
-
-
4
-
-
-
1.5
-
-
100
120
250
10
0.02
-
2.0
-
2.3
130
150
315
-
V
V
V
Tj = 175˚C
Tj = -55˚C
RDS(ON)
Drain-source on-state
resistance
VGS = 10 V; ID = 5.5 A
VGS = 5 V; ID = 5.5 A
mΩ
mΩ
mΩ
S
µA
µA
µA
µA
Tj = 175˚C
gfs
IGSS
Forward transconductance
Gate source leakage current VGS = ±5 V; VDS = 0 V
VDS = 25 V; ID = 5.5 A
1
Tj = 175˚C
Tj = 175˚C
20
10
500
IDSS
Zero gate voltage drain
current
VDS = 55 V; VGS = 0 V;
0.05
-
-
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 11 A; VDD = 44 V; VGS = 5 V
-
-
-
6.1
1.3
3.2
-
-
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 5 A;
VGS = 5 V; RG = 10 Ω
Resistive load
-
-
-
-
6
16
35
30
30
ns
ns
ns
ns
23
18
18
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from tab to centre of die
Measured from source lead to source
bond pad
-
-
3.5
7.5
-
-
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
250
34
35
330
50
50
pF
pF
pF
September 1998
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHB11N06LT, PHD11N06LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
-
-
-
-
-
11
44
A
A
V
ISM
VSD
IF = 11 A; VGS = 0 V
0.95
1.2
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 11 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 30 V
-
-
34
57
-
-
ns
nC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
10
UNIT
WDSS
Drain-source non-repetitive ID ≤ 10 A; VDD ≤ 25 V; VGS = 5 V;
unclamped inductive turn-off RGS = 50 Ω; Tmb = 25 ˚C
energy
-
mJ
September 1998
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHB11N06LT, PHD11N06LT
Normalised Power Derating
PD%
Transient thermal impedance, Zth j-mb (K/W)
120
110
100
90
80
70
60
50
40
30
20
10
0
10
1
0.1
p
t
t
p
P
0.01
D
D =
T
t
T
0.001
1us
10us 100us 1ms
10ms
0.1s
1s
10s
0
20
40
60
80
Tmb /
100 120 140 160 180
C
pulse width, tp (s)
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
ID, Drain current (Amps)
Tj = 25 C
120
110
100
90
80
70
60
50
40
30
20
10
0
10
8
10 V
5 V
3.6 V
3.4 V
6
3.2 V
4
3 V
2.8 V
2
VGS = 2.6 V
0
0
20
40
60
80
100 120 140 160 180
0
2
4
6
8
10
Tmb /
C
VDS, Drain-Source voltage (Volts)
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
RDS(on), Drain-Source on resistance (Ohms)
tp =
ID, Drain current (Amps)
0.5
100
10
1
2.6V
Tj = 25 C
0.4
3.2V
2.8V
3V
3.4V
3.6V
10 us
0.3
0.2
0.1
0
100 us
DC
1 ms
VGS = 5 V
10 V
10 ms
0.1
0
2
4
6
8
10
1
10
VDS, Drain-source voltage (Volts)
100
ID, Drain current (Amps)
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
September 1998
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHB11N06LT, PHD11N06LT
VGS(TO) / V
max.
Drain current, ID (A)
10
2.5
2
VDS > ID x RDS(on)
8
typ.
1.5
1
6
4
min.
175 C
2
0.5
Tj = 25 C
0
0
0
1
2
3
4
5
-100
-50
0
50
Tj / C
100
150
200
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.10. Gate threshold voltage.
GS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
V
Sub-Threshold Conduction
Transconductance, gfs (S)
VDS > ID x RDS(on)
1E-01
1E-02
1E-03
1E-04
1E-05
1E-05
8
7
6
5
4
3
2
1
0
Tj = 25 C
2%
typ
98%
Tj = 175 C
0
2
4
6
8
10
Drain current, ID (A)
0
0.5
1
1.5
2
2.5
3
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Capacitances, Ciss, Coss, Crss (pF)
Rds(on) normlised to 25degC
a
1000
100
10
2.5
2
Ciss
Coss
Crss
1.5
1
0.5
0.1
1
10
100
-100
-50
0
50
100
150
200
Drain-source voltage, VDS (V)
Tmb / degC
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 5.5 A; VGS = 5 V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
September 1998
5
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHB11N06LT, PHD11N06LT
WDSS%
VGS, Gate-Source voltage (Volts)
15
120
110
100
90
80
70
60
50
40
30
20
10
0
VDD = 44 V
ID = 11 A
Tj = 25 C
10
5
0
20
40
60
80
100
120
140
160
180
0
2
4
6
8
10
12
Qg, Gate charge (nC)
Tmb / C
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb)
Source-drain diode current, IF (A)
VGS = 0V
20
15
10
5
VDD
+
L
VDS
-
175 C
VGS
-ID/100
Tj = 25 C
T.U.T.
0
R 01
RGS
shunt
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Source-drain voltage, VSDS (V)
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 LID2 BVDSS/(BVDSS − VDD
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
)
September 1998
6
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHB11N06LT, PHD11N06LT
MECHANICAL DATA
Dimensions in mm
Net Mass: 1.4 g
4.5 max
1.4 max
10.3 max
11 max
15.4
2.5
0.85 max
(x2)
0.5
2.54 (x2)
Fig.17. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.18. SOT404 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
September 1998
7
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHB11N06LT, PHD11N06LT
MECHANICAL DATA
Dimensions in mm : Net Mass: 1.4 g
seating plane
1.1
2.38 max
0.93 max
5.4
6.73 max
tab
4 min
6.22 max
0.5 min
10.4 max
4.6
0.5
2
0.3
0.5
3
1
0.8 max
(x2)
2.285 (x2)
Fig.19. SOT428 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
7.0
2.15
2.5
1.5
4.57
Fig.20. SOT428 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
September 1998
8
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHB11N06LT, PHD11N06LT
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
September 1998
9
Rev 1.000
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