PHB8ND50E [NXP]

PowerMOS transistors FREDFET, Avalanche energy rated; 功率MOS晶体管FREDFET ，额定雪崩能量


型号：	PHB8ND50E
厂家：	NXP
描述：	PowerMOS transistors FREDFET, Avalanche energy rated 功率MOS晶体管FREDFET ，额定雪崩能量晶体晶体管功率场效应晶体管开关脉冲
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Philips Semiconductors

Product specification

PowerMOS transistors

FREDFET, Avalanche energy rated

PHP8ND50E, PHB8ND50E, PHW8ND50E

FEATURES

SYMBOL

QUICK REFERENCE DATA

• Repetitive Avalanche Rated

• Fast switching

V_DSS= 500 V

• Stable off-state characteristics

• High thermal cycling performance

• Low thermal resistance

I_D= 8.5 A

_DS(ON)≤ 0.85 Ω

• Fast reverse recovery diode

t_rr= 180 ns

GENERAL DESCRIPTION

N-channel, enhancement mode field-effect power transistor, incorporating a Fast Recovery Epitaxial Diode (FRED).

This gives improved switching performance in half bridge and full bridge converters making this device particularly

suitable for inverters, lighting ballasts and motor control circuits.

The PHP8ND50E is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHW8ND50E is supplied in the SOT429 (TO247) conventional leaded package.

The PHB8ND50E is supplied in the SOT404 surface mounting package.

PINNING

SOT78 (TO220AB)

SOT404

SOT429 (TO247)

DESCRIPTION

tab

gate

drain¹

source

tab drain

1 2 3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DSS

V_DGR

V_GS

I_D

Drain-source voltage

T_j= 25 ˚C to 150˚C

500

± 30

8.5

Drain-gate voltage

T_j= 25 ˚C to 150˚C; R_GS= 20 kΩ

Gate-source voltage

Continuous drain current

T_mb= 25 ˚C; V_GS= 10 V

T_mb= 100 ˚C; V_GS= 10 V

T_mb= 25 ˚C

5.4

I_DM

P_D

T_j, T_stg

Pulsed drain current

Total dissipation

Operating junction and

storage temperature range

147

150

T_mb= 25 ˚C

˚C

- 55

1 It is not possible to make connection to pin 2 of the SOT404 package.

August 1998

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistors

FREDFET, Avalanche energy rated

PHP8ND50E, PHB8ND50E, PHW8ND50E

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

E_AS

Non-repetitive avalanche

energy

Unclamped inductive load, I_AS= 6.2 A;

t_p= 0.18 ms; T_jprior to avalanche = 25˚C;

510

_DD≤ 50 V; R_GS= 50 Ω; V_GS= 10 V; refer

to fig:17

E_AR

Repetitive avalanche energy²I_AR= 8.5 A; t_p= 1 µs; T_jprior to

avalanche = 25˚C; R_GS= 50 Ω; V_GS= 10 V;

refer to fig:18

I_AS, I_AR

Repetitive and non-repetitive

avalanche current

8.5

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

R_{th j-mb}

Thermal resistance junction

to mounting base

0.85 K/W

R_{th j-a}

Thermal resistance junction SOT78 package, in free air

K/W

to ambient

SOT429 package, in free air

SOT404 package, pcb mounted, minimum

footprint

2 pulse width and repetition rate limited by T_jmax.

August 1998

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistors

FREDFET, Avalanche energy rated

PHP8ND50E, PHB8ND50E, PHW8ND50E

ELECTRICAL CHARACTERISTICS

T_j= 25 ˚C unless otherwise specified

SYMBOL PARAMETER

V_(BR)DSSDrain-source breakdown

CONDITIONS

MIN. TYP. MAX. UNIT

V_GS= 0 V; I_D= 0.25 mA

V_DS= V_GS; I_D= 0.25 mA

500

voltage

∆V_(BR)DSS/ Drain-source breakdown

0.1

%/K

∆T_j

voltage temperature

coefficient

R_DS(ON)

V_GS(TO)

g_fs

Drain-source on resistance

Gate threshold voltage

Forward transconductance

Drain-source leakage current V_DS= 500 V; V_GS= 0 V

V_DS= 400 V; V_GS= 0 V; T_j= 125 ˚C

Gate-source leakage current V_GS= ±30 V; V_DS= 0 V

V_GS= 10 V; I_D= 4.8 A

V_DS= V_GS; I_D= 0.25 mA

V_DS= 30 V; I_D= 4.8 A

2.0

3.5

0.7

3.0

0.85

4.0

Ω

I_DSS

µA

250

200

I_GSS

Q_g(tot)

Q_gs

Q_gd

Total gate charge

Gate-source charge

Gate-drain (Miller) charge

I_D= 8.5 A; V_DD= 400 V; V_GS= 10 V

110

t_d(on)

t_r

t_d(off)

t_f

Turn-on delay time

Turn-on rise time

Turn-off delay time

Turn-off fall time

V_DD= 250 V; R_D= 30 Ω;

R_G= 9.1 Ω

104

L_d

Internal drain inductance

Measured from tab to centre of die

Measured from drain lead to centre of die

(SOT78 and SOT429 packages only)

Measured from source lead to source

bond pad

3.5

4.5

L_s

Internal source inductance

7.5

C_iss

C_oss

C_rss

Input capacitance

Output capacitance

Feedback capacitance

V_GS= 0 V; V_DS= 25 V; f = 1 MHz

1060

160

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS

T_j= 25 ˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

I_S

Continuous source current

(body diode)

T_mb= 25˚C

8.5

I_SM

Pulsed source current (body T_mb= 25˚C

diode)

V_SD

t_rr

Diode forward voltage

I_S= 8.5 A; V_GS= 0 V

1.5

Reverse recovery time

I_S= 8.5 A; V_GS= 0 V; dI/dt = 100 A/µs

I_S= 8.5 A; V_GS= 0 V; dI/dt = 100 A/µs;

125˚C

I_S= 8.5 A; V_GS= 0 V; dI/dt = 100 A/µs

I_S= 8.5 A; V_GS= 0 V; dI/dt = 100 A/µs;

125˚C

I_S= 8.5 A; V_GS= 0 V; dI/dt = 100 A/µs;

125˚C

180

220

Q_rr

I_rrm

Reverse recovery charge

0.65

2.6

µC

Peak reverse recovery

current

August 1998

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistors

FREDFET, Avalanche energy rated

PHP8ND50E, PHB8ND50E, PHW8ND50E

Normalised Power Derating

PD%

PHP6N60

Zth j-mb, Transient thermal impedance (K/W)

D = 0.5

120

110

100

0.1

0.2

0.1

0.05

0.02

0.01

0.001

t_p

D =

single pulse

10us

1us

100us

1ms

10ms

100ms

Tmb /

100

120

140

tp, pulse width (s)

Fig.1. Normalised power dissipation.

PD% = 100 P_D/P_{D 25 ˚C}= f(T_mb)

Fig.4. Transient thermal impedance.

Z_{th j-mb}= f(t); parameter D = t_p/T

Normalised Current Derating

ID%

PHP8N50

10 V

ID, Drain current (Amps)

Tj = 25 C

120

110

100

7 V

6.5 V

6 V

5.5 V

5 V

VGS = 4.5 V

Tmb /

100

120

140

25 30

VDS, Drain-Source voltage (Volts)

Fig.2. Normalised continuous drain current.

ID% = 100 I_D/I_{D 25 ˚C}= f(T_mb); conditions: V_GS≥ 10 V

Fig.5. Typical output characteristics.

I_D= f(V_DS); parameter V_GS

ID / A

PHP8N50

Tj = 25 C

BUK457-500B

RDS(on), Drain-Source on resistance (Ohms)

100

4.5 V

5 V

5.5 V

VGS = 6 V

1.5

tp = 10 us

6.5 V

7 V

RDS(ON) = VDS/ID

100 us

1 ms

10 V

10 ms

0.5

100 ms

0.1

100

VDS / V

1000

ID, Drain current (Amps)

Fig.3. Safe operating area. T_mb= 25 ˚C

I_D& I_DM= f(V_DS); I_DMsingle pulse; parameter t_p

Fig.6. Typical on-state resistance.

R_DS(ON)= f(I_D); parameter V_GS

August 1998

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistors

FREDFET, Avalanche energy rated

PHP8ND50E, PHB8ND50E, PHW8ND50E

VGS(TO) / V

ID, Drain current (Amps)

VDS > ID x RDS(on)max

PHP8N50

max.

typ.

min.

Tj = 150 C

Tj = 25 C

-60 -40 -20

80 100 120 140

VGS, Gate-Source voltage (Volts)

Tj /

Fig.7. Typical transfer characteristics.

I_D= f(V_GS); parameter T_j

Fig.10. Gate threshold voltage.

V_GS(TO)= f(T_j); conditions: I_D= 0.25 mA; V_DS= V_GS

SUB-THRESHOLD CONDUCTION

ID / A

gfs, Transconductance (S)

PHP8N50

1E-01

1E-02

1E-03

1E-04

1E-05

1E-06

VDS > ID x RDS(on)max

Tj = 25 C

150 C

2 %

typ

98 %

ID, Drain current (A)

VGS / V

Fig.8. Typical transconductance.

g_fs= f(I_D); parameter T_j

Fig.11. Sub-threshold drain current.

I_D= f(V_GS); conditions: T_j= 25 ˚C; V_DS= V_GS

Normalised RDS(ON) = f(Tj)

PHP8N50

Junction capacitances (pF)

10000

1000

100

Ciss

Coss

Crss

-60 -40 -20

20 40 60 80 100 120 140

Tj /

100

1000

VDS, Drain-Source voltage (Volts)

Fig.9. Normalised drain-source on-state resistance.

a = R_DS(ON)/R_{DS(ON)25 ˚C}= f(T_j); I_D= 4.25 A; V_GS= 10 V

Fig.12. Typical capacitances, C_iss, C_oss, C_rss.

C = f(V_DS); conditions: V_GS= 0 V; f = 1 MHz

August 1998

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistors

FREDFET, Avalanche energy rated

PHP8ND50E, PHB8ND50E, PHW8ND50E

PHP8N50

VGS, Gate-Source voltage (Volts)

IF, Source-Drain diode current (Amps)

ID = 8.5 A

250 V

VGS = 0 V

Tj = 25 C

100 V

VDD = 400 V

150 C

Tj = 25 C

0.2

0.4

0.6

0.8

1.2

1.4

100

150

Qg, Gate charge (nC)

VSDS, Source-Drain voltage (Volts)

Fig.13. Typical turn-on gate-charge characteristics.

V_GS= f(Q_G); parameter V_DS

Fig.16. Source-Drain diode characteristic.

I_F= f(V_SDS); parameter T_j

Switching times (ns)

PHP8N50

1000

100

VDD = 250 V

VGS = 10 V

RD = 30 Ohms

Non-repetitive Avalanche current, IAS (A)

Tj = 25 C

25 C

Tj prior to avalanche = 125 C

td(off)

VDS

PHP8N50E

td(on)

0.1

1E-06

1E-05

1E-04

1E-03

1E-02

Avalanche time, tp (s)

RG, Gate resistance (Ohms)

Fig.14. Typical switching times; t_d(on), t_r, t_d(off), t_f= f(R_G)

Fig.17. Maximum permissible non-repetitive

avalanche current (I_AS) versus avalanche time (t_p);

unclamped inductive load

Normalised Drain-source breakdown voltage

V(BR)DSS @ Tj

1.15

Maximum Repetitive Avalanche Current, IAR (A)

V(BR)DSS @ 25 C

1.1

Tj prior to avalanche = 25 C

1.05

125 C

0.1

0.95

0.9

PHP8N50E

0.01

1E-06

1E-05

1E-04

1E-03

1E-02

0.85

-100

-50

100

150

Avalanche time, tp (s)

Tj, Junction temperature (C)

Fig.15. Normalised drain-source breakdown voltage;

V_(BR)DSS/V_{(BR)DSS 25 ˚C}= f(T_j)

Fig.18. Maximum permissible repetitive avalanche

current (I_AR) versus avalanche time (t_p)

August 1998

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistors

FREDFET, Avalanche energy rated

PHP8ND50E, PHB8ND50E, PHW8ND50E

MECHANICAL DATA

Dimensions in mm

Net Mass: 2 g

4,5

max

10,3

max

1,3

3,7

2,8

5,9

min

15,8

max

3,0 max

not tinned

3,0

13,5

min

1,3

1 2 3

max

(2x)

0,9 max (3x)

0,6

2,4

2,54 2,54

Fig.19. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent

damage to MOS gate oxide.

2. Refer to mounting instructions for SOT78 (TO220) envelopes.

3. Epoxy meets UL94 V0 at 1/8".

August 1998

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistors

FREDFET, Avalanche energy rated

PHP8ND50E, PHB8ND50E, PHW8ND50E

MECHANICAL DATA

Dimensions in mm

10.3 max

4.5 max

1.4 max

Net Mass: 1.4 g

11 max

15.4

2.5

0.85 max

(x2)

0.5

2.54 (x2)

Fig.20. SOT404 : centre pin connected to mounting base.

MOUNTING INSTRUCTIONS

Dimensions in mm

11.5

9.0

17.5

2.0

3.8

5.08

Fig.21. SOT404 : soldering pattern for surface mounting.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent

damage to MOS gate oxide.

2. Epoxy meets UL94 V0 at 1/8".

August 1998

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistors

FREDFET, Avalanche energy rated

PHP8ND50E, PHB8ND50E, PHW8ND50E

MECHANICAL DATA

Dimensions in mm

16 max

5.3 max

1.8

Net Mass: 5 g

3.5

max

5.3

7.3

3.5

max

seating

plane

15.5

max

2.5

4.0

max

15.5

min

0.9 max

2.2 max

3.2 max

1.1

0.4 M

5.45 5.45

Fig.22. SOT429; pin 2 connected to mounting base.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent

damage to MOS gate oxide.

2. Refer to mounting instructions for SOT429 envelope.

3. Epoxy meets UL94 V0 at 1/8".

August 1998

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistors

FREDFET, Avalanche energy rated

PHP8ND50E, PHB8ND50E, PHW8ND50E

DEFINITIONS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Electronics N.V. 1998

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

August 1998

Rev 1.100

PHB8ND50E [NXP]

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