PHB95N03LT/T3 [NXP]
75A, 25V, 0.009ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, SMD, D2PAK-3;
| 型号： | PHB95N03LT/T3 |
| 厂家： | 
NXP |
| 描述： | 75A, 25V, 0.009ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, SMD, D2PAK-3 开关 脉冲 晶体管 |
| 文件： | 总14页 (文件大小：298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PHP/PHB/PHE95N03LT
TrenchMOS™ logic level FET
Rev. 02 — 01 February 2002
Product data
1. Description
N-channel logic level field-effect power transistor in a plastic package using
TrenchMOS™1 technology.
Product availability:
PHP95N03LT in SOT78 (TO-220AB)
PHB95N03LT in SOT404 (D2-PAK)
PHE95N03LT in SOT226 (I2-PAK).
2. Features
■ Low on-state resistance
■ Fast switching.
3. Applications
■ High frequency computer motherboard DC to DC converters
4. Pinning information
Table 1: Pinning - SOT78, SOT404, SOT226 simplified outline and symbol
Pin
1
Description
gate (g)
Simplified outline
Symbol
mb
mb
mb
[1]
2
drain (d)
d
s
3
source (s)
mb
mounting base,
connected to
drain (d)
g
1
2 3
MBK112
2
MBB076
1
3
MBK116
MBK106
1
2 3
SOT78 (TO-220AB) SOT404 (D2-PAK)
SOT226 (I2-PAK)
[1] It is not possible to make connection to pin 2 of the SOT404 package.
1. TrenchMOS - is a trademark of Koninklijke Philips Electronics N.V.
PHP/PHB/PHE95N03LT
Philips Semiconductors
TrenchMOS™ logic level FET
5. Quick reference data
Table 2: Quick reference data
Symbol Parameter
Conditions
Typ
Max
25
Unit
V
VDS
ID
drain-source voltage (DC)
drain current (DC)
Tj = 25 to 175 °C
Tmb = 25 °C; VGS = 5 V
Tmb = 25 °C
-
-
75
A
Ptot
Tj
total power dissipation
junction temperature
-
125
175
7
W
-
°C
mΩ
mΩ
RDSon
drain-source on-state resistance
VGS = 10 V; ID = 25 A
VGS = 5 V; ID = 25 A
5
7.5
9
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
25
Unit
V
VDS
VDGR
ID
drain-source voltage (DC)
Tj = 25 to 175 °C
-
drain-gate voltage (DC)
drain current (DC)
Tj = 25 to 175 °C; RGS = 20 kΩ
Tmb = 25 °C; VGS = 5 V; Figure 2 and 3
Tmb = 100 °C; VGS = 5 V; Figure 2
-
25
V
-
75
A
-
61
A
VGS
IDM
Ptot
Tstg
Tj
gate-source voltage
-
±20
240
125
+175
+175
V
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
Tmb = 25 °C; Figure 1
-
A
total power dissipation
storage temperature
operating junction temperature
-
W
°C
°C
−55
−55
Source-drain diode
IS
source (diode forward) current (DC) Tmb = 25 °C
-
-
75
A
A
ISM
peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs
240
Avalanche ruggedness
EDS(AL)S non-repetitive avalanche energy
unclamped inductive load;
ID = 75 A; tp = 0.1 ms; VDD = 15 V;
RGS = 50 Ω; VGS = 5V; starting Tj = 25 °C;
-
-
120
75
mJ
A
IDS(AL)S non-repetitive avalanche current
unclamped inductive load;
VDD = 15 V; RGS = 50 Ω; VGS = 5V;
starting Tj = 25 °C
9397 750 09285
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 01 February 2002
2 of 14
PHP/PHB/PHE95N03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03aa16
03ad94
120
120
P
der
I
der
(%)
(%)
80
80
40
40
0
0
0
50
100
150
200
(oC)
0
50
100
150
T
200
(ºC)
T
mb
mb
Ptot
ID
Pder
=
× 100%
Ider
=
× 100%
----------------------
------------------
P
I
°
°
tot(25 C)
D(25 C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
03ad77
3
10
I
D
(A)
R
= V
/ I
DS D
DSon
t
= 10 µs
p
100 µs
2
10
1 ms
DC
10
10 ms
100 ms
1
2
10
1
10
V
(V)
DS
Tmb = 25 °C; IDM is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 09285
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 01 February 2002
3 of 14
PHP/PHB/PHE95N03LT
Philips Semiconductors
TrenchMOS™ logic level FET
7. Thermal characteristics
Table 4: Thermal characteristics
Symbol Parameter
Conditions
Min Typ Max Unit
Rth(j-mb) thermal resistance from junction to mounting base Figure 4
-
-
-
-
-
1.2 K/W
Rth(j-a)
thermal resistance from junction to ambient
SOT78 package; vertical in still air
SOT226 package; vertical in still air
60
65
50
-
-
-
K/W
K/W
K/W
mounted on a printed circuit board;
SOT404 minimum footprint;
SOT404 packages
7.1 Transient thermal impedance
03ad76
10
Z
th(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
-1
10
10
10
0.05
0.02
t
p
P
δ =
T
-2
-3
single pulse
t
t
p
T
-5
10
-4
10
-3
10
-2
10
-1
10
1
10
t
(s)
p
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 09285
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 01 February 2002
4 of 14
PHP/PHB/PHE95N03LT
Philips Semiconductors
TrenchMOS™ logic level FET
8. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 0.25 mA; VGS = 0 V
Tj = 25 °C
25
22
-
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage
drain-source leakage current
ID = 1 mA; VDS = VGS; Figure 9
Tj = 25 °C
1
1.5
2
V
V
V
Tj = 175 °C
0.5
-
-
-
-
Tj = −55 °C
2.3
IDSS
VDS = 25 V; VGS = 0 V
Tj = 25 °C
-
-
-
0.05 10
µA
Tj = 175 °C
-
500 µA
IGSS
gate-source leakage current
VGS = ±5 V; VDS = 0 V
VGS = 5 V; ID = 25 A; Figure 7 and 8
Tj = 25 °C
10
100 nA
RDSon
drain-source on-state resistance
-
-
7.5
13
9
mΩ
Tj = 175 °C
15.5 mΩ
VGS = 10 V; ID = 25 A;
Tj = 25 °C
-
5
7
mΩ
Dynamic characteristics
gfs
forward transconductance
VDS = 25 V; ID = 50 A Figure 11
-
-
-
-
-
-
-
-
-
-
-
50
43
12
16
-
-
-
-
S
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
ID = 50 A; VDD = 12 V; VGS = 4.5 V;
Figure 14
nC
nC
nC
pF
pF
pF
ns
ns
gate-source charge
gate-drain (Miller) charge
input capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 12
2200 -
output capacitance
reverse transfer capacitance
turn-on delay time
turn-on rise time
770
500
10
-
-
VDD = 15 V; ID = 15 A; VGS = 10 V;
RG = 6 Ω; resistive load
20
50
30
td(off)
tf
turn-off delay time
turn-off fall time
110 140 ns
80 100 ns
Source-drain diode
VSD
source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 13
-
-
0.85 1.2
0.9
V
V
IS = 40 A; VGS = 0 V
-
9397 750 09285
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 01 February 2002
5 of 14
PHP/PHB/PHE95N03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03ad78
03ad80
75
75
10 V 5 V
3.5 V
I
I
D
T = 25 ºC
D
V
> I x R
D DSon
j
DS
(A)
60
(A)
60
45
30
15
0
45
30
15
0
3 V
T = 25 ºC
j
175 ºC
V
= 2.5 V
GS
0
0.4
0.8
1.2
1.6
2
(V)
0
1
2
3
4
V
(V)
GS
V
DS
Tj = 25 °C
Tj = 25 °C and 175 °C; VDS > ID x RDSon
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
03ad57
03ad79
2
0.05
DSon
R
2.5 V
T = 25 ºC
j
V
= 3 V
a
GS
(Ω)
1.6
0.04
0.03
0.02
0.01
0
1.2
0.8
0.4
0
3.5 V
5V
10 V
0
15
30
45
60
75
-60
0
60
120
180
I
(A)
Tj (ºC)
D
Tj = 25 °C
RDSon
a =
---------------------------
RDSon(25 C)
°
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
9397 750 09285
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 01 February 2002
6 of 14
PHP/PHB/PHE95N03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03aa33
2.5
03aa36
-1
10
V
GS(th)
I
D
(V)
max
(A)
2
-2
10
typ
1.5
-3
10
min
typ
max
min
-4
-5
-6
1
10
10
10
0.5
0
0
0.5
1
1.5
2
2.5
V
3
(V)
-60
0
60
120
180
T (oC)
GS
j
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
03aa81
03ad83
4
90
10
V
> I x R
D
DS
DSon
gfs
C
(S)
(pF)
C
60
30
0
iss
T = 25 ºC
j
3
10
C
oss
175 ºC
C
rss
2
10
-1
10
2
10
0
15
30
45
60
75
1
10
I
(A)
D
V
(V)
DS
Tj = 25 °C and 175 °C; VDS > ID × RDSon
VGS = 0 V; f = 1 MHz
Fig 11. Forward transconductance as a function of
drain current; typical values.
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
9397 750 09285
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 01 February 2002
7 of 14
PHP/PHB/PHE95N03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03ad82
03ad84
75
I
10
V
T = 25 ºC
V
= 0 V
S
GS
j
GS
(A)
60
(V)
8
I
= 50 A
D
V
= 6 V
12 V 24 V
DD
45
30
15
0
6
4
2
0
T = 25 ºC
175 ºC
j
0
0.3
0.6
0.9
1.2
(V)
0
30
60
90
Q
(nC)
V
G
SD
Tj = 25 °C and 175 °C; VGS = 0 V
ID = 50 A; VDD = 6 V, 12 V and 24 V
Fig 13. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
Fig 14. Gate-source voltage as a function of gate
charge; typical values.
9397 750 09285
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 01 February 2002
8 of 14
PHP/PHB/PHE95N03LT
Philips Semiconductors
TrenchMOS™ logic level FET
9. Package outline
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB
SOT78
E
p
A
A
1
q
mounting
base
D
1
D
(1)
L
L
2
1
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
b
L
max.
(1)
2
e
A
b
D
E
L
D
L
1
A
c
UNIT
p
q
Q
1
1
1
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
15.0
13.5
3.30
2.79
3.8
3.6
3.0
2.7
2.6
2.2
mm
3.0
2.54
Note
1. Terminals in this zone are not tinned.
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SC-46
00-09-07
01-02-16
SOT78
3-lead TO-220AB
Fig 15. SOT78 (TO-220AB).
9397 750 09285
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 01 February 2002
9 of 14
PHP/PHB/PHE95N03LT
Philips Semiconductors
TrenchMOS™ logic level FET
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads
(one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
99-06-25
01-02-12
SOT404
Fig 16. SOT404 (D2-PAK)
9397 750 09285
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 01 February 2002
10 of 14
PHP/PHB/PHE95N03LT
Philips Semiconductors
TrenchMOS™ logic level FET
Plastic single-ended package; low-profile 3 lead TO-220AB
SOT226
A
A
1
E
D
1
mounting
base
D
L
1
L
2
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
2
max
L
L
D
D
1
A
1
b
c
E
UNIT
A
b
e
L
Q
1
1
4.5
4.1
1.40
1.27
0.9
0.7
1.3
1.0
0.7
0.4
9.65
8.65
1.5
1.1
10.3
9.7
15.0
13.5
3.30
2.79
2.6
2.2
mm
2.54
3.0
Note
1. Terminals in this zone are not tinned.
REFERENCES
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
JEDEC
EIAJ
low-profile
3-lead TO-220AB
99-05-27
99-09-13
SOT226
Fig 17. SOT226 (I2-PAK)
9397 750 09285
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 01 February 2002
11 of 14
PHP/PHB/PHE95N03LT
Philips Semiconductors
TrenchMOS™ logic level FET
10. Revision history
Table 6: Revision history
Rev Date
CPCN
-
Description
02 20020201
Product data; second version. Supersedes PHP95N03LT-01 02 Feb 01 (9397 750
07814). Modifications:
Datasheet title changed to comply with TDS standards.
•
Changes toTable 3 “Limiting values”:
•
– VGSM entry removed
– Symbol “EAS “changed to→ “EDS(AL)S
– Symbol “IAS“changed to→ “IDS(AL)S
“
“
Figure 14 “Gate-source voltage as a function of gate charge; typical values.”
Standardized VGS rating
•
Table 4 “Thermal characteristics” Clarification of table
•
•
All figures modified to comply with TDS Graphic standards. No data has been changed.
01 20010202
-
Product specification; initial version
9397 750 09285
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 01 February 2002
12 of 14
PHP/PHB/PHE95N03LT
Philips Semiconductors
TrenchMOS™ logic level FET
11. Data sheet status
[1]
[2]
Data sheet status
Product status
Definition
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips Semiconductors
reserves the right to change the specification in any manner without notice.
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published at a
later date. Philips Semiconductors reserves the right to change the specification without notice, in order to
improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the right to
make changes at any time in order to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change Notification (CPCN) procedure
SNW-SQ-650A.
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
12. Definitions
13. Disclaimers
Short-form specification — The data in
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
a
short-form specification is
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
13 of 14
9397 750 09285
Product data
Rev. 02 — 01 February 2002
PHP/PHB/PHE95N03LT
Philips Semiconductors
TrenchMOS™ logic level FET
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2
3
4
5
6
7
7.1
8
9
10
11
12
13
© Koninklijke Philips Electronics N.V. 2002.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 01 February 2002
Document order number: 9397 750 09285
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NXP
PHB9NQ20T/T3
TRANSISTOR 8.7 A, 200 V, 0.4 ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, SMD, D2PAK-3, FET General Purpose Power
NXP
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