PCK2002PLDP-T_技术文档

INTEGRATED CIRCUITS

PCK2002

0–300 MHz I²C 1:18 clock buffer

Product data

2001 Jul 19

File under Integrated Circuits ICL03

Philips

Semiconductors

Philips Semiconductors

Product data

0–300 MHz I²C 1:18 clock buffer

PCK2002

FEATURES

• Spread spectrum compliant

• HIGH speed, LOW noise non-inverting 1–18 buffer

• Typically used to support four SDRAM DIMMs

• Multiple V , V pins for noise reduction

• 3.3 V operation

• Separate 3-State pin for testing

• ESD protection exceeds 2000 V per Standard 801.2

• Optimized for 66 MHz, 100 MHz and 133 MHz operation

• Typical 175 ps skew outputs

2

• Individual clock output enable/disable via I C

DESCRIPTION

DD

SS

The PCK2002 is a 1–18 fanout buffer used for 133/100 MHz CPU,

66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM

clock distribution. 18 outputs are typically used to support up to

4 SDRAM DIMMS commonly found in desktop, workstation or

server applications.

All clock outputs meet Intel’s drive, rise/fall time, accuracy, and skew

requirements. An I C interface is included to allow each output to be

enabled/disabled individually. An output disabled via the I C

2

• Available in 48-pin SSOP and TSSOP packages

interface will be held in the LOW state. In addition, there is an OE

input which 3-States all outputs.

• See PCK2002M for mobile (reduced pincount) 28-pin 1-10 buffer

version

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

= 3.3 V, CL = 30 pF

TYPICAL

UNIT

t

Propagation delay

2.7

2.9

PLH

PHL

V

ns

CC

BUF_IN to BUF_OUT

Rise time

n

t

r

V

CC

V

CC

V

CC

= 3.3 V, CL = 30 pF

= 3.465 V

1.1

1.0

35

ns

µA

t

f

Fall time

I

Total supply current

CC

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

0 to +70 °C

ORDER CODE

DRAWING NUMBER

SOT362-1

48-Pin Plastic TSSOP

48-Pin Plastic SSOP

PCK2002DGG

PCK2002DL

0 to +70 °C

SOT370-1

PIN CONFIGURATION

PIN DESCRIPTION

NUMBER

I/O

TYPE

SYMBOL

FUNCTION

RESERVED

1

2

3

4

5

6

7

8

9

48

47

46

RESERVED

4, 5, 8, 9

Output BUF_OUT (0–3) Buffered clock outputs

V

DD9

DD0

13, 14, 17, 18 Output BUF_OUT (4–7) Buffered clock outputs

45

BUF_OUT0

BUF_OUT1

BUF_OUT15

31, 32, 35,

36

BUF_OUT

(8–11)

44 BUF_OUT14

V

Output

Buffered clock outputs

V

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

SS0

SS9

DD8

40, 41, 44,

45

BUF_OUT

(12–15)

V

DD1

BUF_OUT2

BUF_OUT13

BUF_OUT12

BUF_OUT

(16–17)

BUF_OUT3

V

21, 28

11

Output

Input

Buffered clock outputs

Buffered clock input

V

SS1 10

SS8

BUF_IN

OE

BUF_IN 11

V

DD2 12

DD7

Active high output

enable

38

Input

OE

BUF_OUT4 13

BUF_OUT11

BUF_OUT10

2

BUF_OUT5 14

V

24

25

I/O

SDA

SCL

I C serial data

V

SS2

DD3

15

16

17

18

19

20

21

22

23

24

SS7

2

Input

I C serial clock

V

DD6

3, 7, 12, 16,

20, 29, 33,

37, 42, 46

BUF_OUT6

BUF_OUT7

BUF_OUT9

BUF_OUT8

Input

V

3.3 V Power supply

Ground

DD (0–9)

V

SS3

SS6

6, 10, 15,

19, 22,

27, 30, 34,

39, 43

V

DD4

DD5

BUF_OUT17

Input

V

SS (0–9)

BUF_OUT16

V

27

SS4

SS5

V

DDI2C

SDA

26 SSI2C

25

2

3.3 V I C Power

23

V

DDI2C

SCL

supply

2

26

Input

n/a

V

I C Ground

SW00731

SSI2C

2

1, 2, 47, 48

RESERVED

Undefined

I C is a trademark of Philips Semiconductors Corporation.

2

2001 Jul 19

853-2267 26745

Philips Semiconductors

Product data

0–300 MHz I²C 1:18 clock buffer

PCK2002

FUNCTION TABLE

2

OE

L

BUF_IN

I CEN

BUF_OUTn

X

L

X

H

L

Z

L

H

L

H

1, 2

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134)

Voltages are referenced to V (V = 0V)

SS

LIMITS

SYMBOL

PARAMETER

CONDITION

UNIT

MIN

MAX

+4.6

–50

V

I

DC 3.3 V supply voltage

DC input diode current

DC input voltage

–0.5

V

mA

V

DD

V < 0

I

IK

V

I

Note 2

–0.5

–65

+4.6

±50

I

DC output diode current

DC output voltage

V

O

> V or V < 0

mA

V

OK

DD

O

V

O

Note 2

V

CC

+ 0.5

I

O

DC output source or sink current

Storage temperature range

V

O

>= 0 to V

DD

±50

mA

°C

T

STG

+150

Power dissipation per package

plastic medium-shrink SO (SSOP)

For temperature range: 0 to +70°C

above +55°C derate linearly with 11.3mW/K

P

TOT

850

mW

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

CONDITIONS

UNIT

MIN

3.135

20

MAX

3.465

30

V

DD

DC 3.3 V supply voltage

Capacitive load

V

pF

V

C

L

V

I

DC input voltage range

0

V

DD

V

DD

V

O

DC output voltage range

0

V

T

amb

Operating ambient temperature range in free air

0

+70

°C

3

2001 Jul 19

Philips Semiconductors

Product data

0–300 MHz I²C 1:18 clock buffer

PCK2002

DC CHARACTERISTICS

LIMITS

TEST CONDITIONS

OTHER

T

= 0 to +70 °C

UNIT

SYMBOL

PARAMETER

amb

V

DD

(V)

MIN

MAX

V

HIGH level input voltage

LOW level input voltage

3.135 to 3.465

3.135

2.0

V

DD

+ 0.3

V

IH

V

– 0.3

0.8

IL

SS

CC

I

= –1 mA

V

– 0.1

—

OH

V

OH

3.3V output HIGH voltage

3.3V output LOW voltage

Output HIGH current

V

I

= –36 mA

2.4

OH

3.135 to 3.465

3.135

I

= 1 mA

—

0.1

0.4

–126

–46

118

53

OL

V

OL

V

I

= 24 mA

OL

3.135

V

= 2.0 V

= 3.135 V

= 1.0 V

–54

–21

49

24

—

OUT

I

mA

OH

3.465

V

OUT

3.135 to 3.465

3.465

V

OUT

I

OL

Output LOW current

= 0.4 V

±I

Input leakage current

3-State output OFF-State current

Quiescent supply current

±5

µA

I

±I

3.465

V

= V or GND

I

= 0

—

10

OZ

CC

OUT

DD

O

I

3.465

V = V or GND

—

100

I

DD

O

Additional quiescent supply

current given per control pin

∆I

CC

3.135 to 3.465

V = V – 0.6V

I

O

= 0

—

500

µA

I

DD

AC CHARACTERISTICS

LIMITS

= 0 to +70 °C

TEST CONDITIONS

NOTES

T

amb

SYMBOL

PARAMETER

UNIT

6

MIN

1.5

1.2

1.0

45

TYP

MAX

4.0

3.5

5.0

55

T

SDRAM rise time

SDRAM fall time

2, 4

2.0

2.9

2.7

2.9

2.6

2.7

52

V/ns

ns

SDRISE

SDFALL

T

SDRAM buffer LH propagation delay

SDRAM buffer HL propagation delay

SDRAM buffer enable time

SDRAM buffer disable time

Output Duty Cycle

4, 5

PLH

4, 5

ns

PHL

T

, T

4, 5

ns

PZL PZH

, T

4, 5

ns

PLZ PHZ

DUTY CYCLE

Measured at 1.5 V

3, 4, 5

1, 4

%

T

SDRAM Bus CLK skew

—

150

—

250

500

ps

SDSKW

Device to device skew

—

ps

DDSKW

NOTES:

1. Skew is measured on the rising edge at 1.5 V.

2. T and T are measured as a transition through the threshold region V = 0.4 V and V = 2.4 V (1mA) JEDEC specification.

SDRISE

SDFALL

OL

OH

3. Duty cycle should be tested with a 50/50% input.

4. Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature.

5. Input edge rate for these tests must be faster than 1 V/ns.

6. All typical values are at V = 3.3 V and T

= 25 °C.

CC

amb

4

2001 Jul 19

Philips Semiconductors

Product data

0–300 MHz I²C 1:18 clock buffer

PCK2002

2

I C CONSIDERATIONS

2

I C has been chosen as the serial bus interface to control the PCK2002. I C was chosen to support the JEDEC proposal JC-42.5 168 Pin

2

Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I C devices.

1) Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only

2

one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I C clock driver is used in

the system.

The following address was confirmed by Philips on 09/04/96.

A6

A5

A4

A3

A2

A1

A0

R/W

0

1

0

1

0

1

2

NOTE: The R/W bit is used by the I C controller as a data direction bit. A ‘zero’ indicates a transmission (WRITE) to the clock device. A ‘one’

indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE data; the

R/W bit of the address will always be seen as ‘zero’. Optimal address decoding of this bit is left to the vendor.

2) Options: It is our understanding that metal mask options and other pinouts of this type of clock driver will be allowed to use the same address

2

as the original CKBF device. I C addresses are defined in terms of function (master clock driver) rather than form (pinout, and option).

3) Slave/Receiver: The clock driver is assumed to require only slave/receiver functionality. Slave/transmitter functionality is optional.

4) Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional.

2

5) Logic Levels: I C logic levels are based on a percentage of V for the controller and other devices on the bus. Assume all devices are

DD

based on a 3.3 Volt supply.

6) Data Byte Format: Byte format is 8 Bits as described in the following appendices.

2

7) Data Protocol: To simplify the clock I C interface, the clock driver serial protocol was specified to use only block writes from the controller.

The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been

2

transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I C protocol.

2

The clock driver must meet this protocol which is more rigorous than previously stated I C protocol. Treat the description from the viewpoint of

controller. The controller “writes” to the clock driver and if possible would “read” from the clock driver (the clock driver is a slave/receiver only

and is incapable of this transaction.)

“The block write begins with a slave address and a write condition. After the command code the host (controller) issues a byte count which

describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h),

followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transfer a maximum of 32 data bytes.”

1 bit

7 bits

1

8 bits

1

Start bit

Slave Address

R/W

Ack

Command Code Ack

Byte Count = N

...

Ack

1 bit

Data Byte 1

8 bits

Ack

1

Data Byte 2

8 bits

Ack

1

Data Byte 2

8 bits

Ack

1

Stop

1

SW00279

NOTE: The acknowledgement bit is returned by the slave/receiver (the clock driver).

5

2001 Jul 19

Philips Semiconductors

Product data

0–300 MHz I²C 1:18 clock buffer

PCK2002

Consider the command code and the byte count bytes required as the first two bytes of any transfer. The command code is software

programmable via the controller, but will be specified as 0000 0000 in the clock specification. The byte count byte is the number of additional

bytes required to transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to be a minimum of

1 byte and a maximum of 32 bytes to satisfy the above requirement.

For example:

Byte count byte

Notes:

MSB

0000

0010

LSB

0000 Not allowed. Must have at least one byte.

0001 Data for functional and frequency select register (currently byte 0 in spec)

0010 Reads first two bytes of data. (byte 0 then byte 1)

0011 Reads first three bytes (byte 0, 1, 2 in order)

0100 Reads first four bytes (byte 0, 1, 2, 3 in order)

0101 Reads first five bytes (byte 0, 1, 2, 3, 4 in order)

0110 Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)

0111 Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)

0000 Max byte count supported = 32

A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The serial controller interface

can be simplified by discarding the information in both the command code and the byte count bytes and simply reading all the bytes that are

sent to the clock driver after being addressed by the controller. It is expected that the controller will not provide more bytes than the clock driver

can handle. A clock vendor may choose to discard any number of bytes that exceed the defined byte count.

8) Clock stretching: The clock device must not hold/stretch the SCLOCK or SDATA lines low for more than 10 ms. Clock stretching is

discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than this time puts the device in an error/time-out

mode and may not be supported in all platforms. It is assumed that all data transfers can be completed as specified without the use of

clock/data stretching.

9) General Call: It is assumed that the clock driver will not have to respond to the “general call.”

2

10) Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15 of the I C

specification.

a) Pull-Up Resistors: Any internal resistors pull-ups on the SDATA and SCLOCK inputs must be stated in the individual datasheet. The use of

internal pull-ups on these pins of below 100 k Ω is discouraged. Assume that the board designer will use a single external pull-up resistor for

2

each line and that these values are in the 5–6 k Ω range. Assume one I C device per DIMM (serial presence detect), one I C controller, one

2

clock driver plus one/two more I C devices on the platform for capacitive loading purposes.

2

(b) Input Glitch Filters: Only fast mode I C devices require input glitch filters to suppress bus noise. The clock driver is specified as a standard

mode device and is not required to support this feature.

11) PWR DWN: If a clock driver is placed in PWR DWN mode, the SDATA and SCLK inputs must be Tri-Stated and the device must retain all

2

programming information. I current due to the I C circuitry must be characterized and in the data sheet.

dd

2

For specific I C information consult the Philips I C Peripherals Data Handbook IC12 (1997).

6

2001 Jul 19

Philips Semiconductors

Product data

0–300 MHz I²C 1:18 clock buffer

PCK2002

SERIAL CONFIGURATION MAP

The serial bits will be read by the clock buffer in the following order:

Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 2 – Bits 7, 6, 5, 4, 3, 2, 1, 0

All unused register bits (Reserved and N/A) should be desined as “Don’t Care”. It is expected that the controller will force all of these bits to a

“0” level.

All register bits labeled “Initialize to 0” must be written to zero during intialization. Failure to do so may result in a higher than normal operating

current. The controller will read back the last written value.

Byte 0: SDRAM Output active/inactive register

1 = enable; 0 = disable

AFFECTED PIN

PIN NO.

BIT CONTROL

BIT(S)

CONTROL FUNCTION

PIN NAME

BUF_OUT7

BUF_OUT6

BUF_OUT5

BUF_OUT4

BUF_OUT3

BUF_OUT2

BUF_OUT1

BUF_OUT0

0

1

7

6

5

4

3

2

1

0

18

17

14

13

9

Clock Output Disable

Low

Active

8

5

4

NOTE:

1. At power up all SDRAM outputs are enabled and active. Program all reserved bits to “0”.

Byte 1: SDRAM Output active/inactive register

1 = enable; 0 = disable

AFFECTED PIN

BIT CONTROL

BIT(S)

CONTROL FUNCTION

PIN NO.

45

PIN NAME

BUF_OUT15

BUF_OUT14

BUF_OUT13

BUF_OUT12

BUF_OUT11

BUF_OUT10

BUF_OUT9

BUF_OUT8

0

1

7

6

5

4

3

2

1

0

Clock Output Disable

Low

Active

44

41

40

36

35

32

31

NOTE:

1. At power up all SDRAM outputs are enabled and active. Program all reserved bits to “0”.

7

2001 Jul 19

Philips Semiconductors

Product data

0–300 MHz I²C 1:18 clock buffer

PCK2002

Byte 2: SDRAM Output active/inactive register

1 = enable; 0 = disable

AFFECTED PIN

BIT CONTROL

BIT(S)

CONTROL FUNCTION

PIN NO.

N/A

12

PIN NAME

BUF_OUT17

BUF_OUT16

Reserved

0

Low

—

1

Active

—

7

6

5

4

3

2

1

0

Clock Output Disable

(Reserved)

N/A

Reserved

(Reserved)

—

Reserved

(Reserved)

—

Reserved

(Reserved)

—

Reserved

(Reserved)

—

Reserved

(Reserved)

—

NOTE:

1. At power up all SDRAM outputs are enabled and active. Program all reserved bits to “0”.

8

2001 Jul 19

Philips Semiconductors

Product data

0–300 MHz I²C 1:18 clock buffer

PCK2002

AC WAVEFORMS

TEST CIRCUIT

V

= 1.5 V

M

X

Y

= V + 0.3 V

OL

= V –0.3 V

OH

S

1

and V are the typical output voltage drop that occur with the

V

OL

OH

DD

2<V

DD

output load.

Open

V

SS

V

DD

500Ω

V

I

O

BUF_IN

INPUT

V

M

t

PULSE

GENERATOR

M

D.U.T.

t

R

C

PLH

PHL

L

T

V

M

BUF_OUT

TEST

S

1

t

/t

Open

SW00246

PLH PHL

t

/t

2<V

Figure 1. Load circuitry for switching times.

PLZ PZL

DD

t

/t

V

SS

PHZ PZH

V

I

V

SW00251

DD

V

nOE INPUT

GND

Figure 4. Load circuitry for switching times

M

t

PZL

PLZ

V

DD

OUTPUT

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PZH

PHZ

V

OH

OUTPUT

V

Y

HIGH-to-OFF

OFF-to-HIGH

V

M

V

SS

outputs

enabled

outputs

enabled

outputs

disabled

SW00245

Figure 2. 3-State enable and disable times

T

SDKP

T

SDKH

DUTY CYCLE

2.4

1.5

0.4

T

SDKL

T

SDFALL

SDRISE

SW00247

Figure 3. Buffer Output clock

9

2001 Jul 19

Philips Semiconductors

Product data

0–300 MHz I²C 1:18 clock buffer

PCK2002

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT362-1

10

2001 Jul 19

Philips Semiconductors

Product data

0–300 MHz I²C 1:18 clock buffer

PCK2002

SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm

SOT370-1

11

2001 Jul 19

Philips Semiconductors

Product data

0–300 MHz I²C 1:18 clock buffer

PCK2002

Data sheet status

Product

status

Definitions

[1]

Data sheet status

[2]

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Product data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be

published at a later date. Philips Semiconductors reserves the right to change the specification

without notice, in order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply.

Changes will be communicated according to the Customer Product/Process Change Notification

(CPCN) procedure SNW-SQ-650A.

[1] Please consult the most recently issued datasheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on

the Internet at URL http://www.semiconductors.philips.com.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Copyright Philips Electronics North America Corporation 2001

Sunnyvale, California 94088–3409

Telephone 800-234-7381

Date of release: 07-01

Document order number:

9397 750 08585

Philips

Semiconductors

12

2001 Jul 19


型号：	PCK2002PLDP-T
厂家：	NXP
描述：	IC LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 3 X 4.40 MM, PLASTIC, SOT-530-1, TSSOP-8, Clock Driver 时钟
文件：	总12页 (文件大小：97K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCK2002PLDP-T [NXP]

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