HEF4014BTD-T [NXP]
暂无描述;型号: | HEF4014BTD-T |
厂家: | NXP |
描述: | 暂无描述 移位寄存器 |
文件: | 总14页 (文件大小:105K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HEF4014B
8-bit static shift register
Rev. 8 — 21 November 2011
Product data sheet
1. General description
The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight
synchronous parallel inputs (D0 to D7), a synchronous serial data input (DS), a
synchronous parallel enable input (PE), a LOW-to-HIGH edge-triggered clock input (CP)
and buffered parallel outputs from the last three stages (Q5 to Q7).
Operation is synchronous and the device is edge-triggered on the LOW-to-HIGH
transition of CP. Each register stage is of a D-type master-slave flip-flop type. When PE is
HIGH, data is loaded into the register from D0 to D7 on the LOW-to-HIGH transition of CP.
When PE is LOW, data is shifted to the first position from DS, and all the data in the
register is shifted one position to the right on the LOW-to-HIGH transition of CP. The clock
input’s Schmitt trigger action makes it highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Parallel-to-serial converter
Serial data queueing
General purpose register
4. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +85 C
Type number
Package
Name
Description
Version
HEF4014BP
HEF4014BT
DIP16
SO16
plastic dual in-line package; 16-leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
SOT38-4
SOT109-1
HEF4014B
NXP Semiconductors
8-bit static shift register
5. Functional diagram
7
6
5
4
13 14 15
1
D0 D1 D2 D3 D4 D5 D6 D7
9
PE
11 DS
10 CP
0D 1D 2D 3D 4D 5D 6D 7D
CP
SHIFT REGISTER
8 BITS
Q5 Q6 Q7
12
2
3
001aae556
Fig 1. Functional diagram
PE
D0
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
FF 0
CP
FF 5
CP
FF 6
CP
FF 7
CP
DS
CP
Q5
Q6
Q7
001aae558
Fig 2. Logic diagram
HEF4014B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
2 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
6. Pinning information
6.1 Pinning
HEF4014B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D7
Q5
Q7
D3
D2
D1
D0
V
DD
D6
D5
D4
Q6
DS
CP
PE
V
SS
001aae557
Fig 3. Pin configuration DIP16 and SO16
6.2 Pin description
Table 2.
Symbol
Q5 to Q7
D0 to D7
VSS
Pin description
Pin
Description
2, 12, 3
output
7, 6, 5, 4, 13, 14, 15, 1
parallel data input
8
ground supply voltage
parallel enable input
PE
9
CP
10
11
16
clock input (LOW-to-HIGH edge-triggered)
serial data input
DS
VDD
supply voltage
HEF4014B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
3 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
7. Functional description
Table 3.
Function table[1]
Number of clock
transitions
Inputs
CP
Outputs
Q5
DS
PE
Q6
Q7
Serial operation
1
2
3
6
7
8
1D
2D
3D
X
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
1D
X
X
X
2D
1D
2D
X
X
3D
1D
X
no change
no change
no change
Parallel operation
1
X
X
H
X
D5
D6
D7
no change
no change
no change
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; nD = HIGH or LOW;
= LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition;
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
0.5
-
Max
+18
10
Unit
V
supply voltage
input clamping current
input voltage
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
mA
V
VI
0.5
-
VDD + 0.5
IOK
output clamping current
input/output current
supply current
10
10
50
mA
mA
mA
C
II/O
-
IDD
-
Tstg
Tamb
Ptot
storage temperature
ambient temperature
total power dissipation
65
40
+150
+85
C
Tamb = 40 C to +85 C
DIP16 package
SO16 package
per output
[1]
[2]
-
-
-
750
500
100
mW
mW
mW
P
power dissipation
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
HEF4014B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
4 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
9. Recommended operating conditions
Table 5.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
15
Unit
V
supply voltage
3
-
-
-
-
-
-
VI
input voltage
0
VDD
+85
3.75
0.5
V
Tamb
ambient temperature
input transition rise and fall rate
in free air
40
C
t/V
VDD = 5 V
VDD = 10 V
VDD = 15 V
-
-
-
s/V
s/V
s/V
0.08
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = 40 C Tamb = +25 C Tamb = +85 C Unit
Min
Max
-
Min
Max
-
Min
Max
VIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
HIGH-level output current
IO < 1 A
5 V
10 V
15 V
5 V
3.5
3.5
3.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
7.0
-
7.0
-
7.0
11.0
-
11.0
-
11.0
-
VIL
IO < 1 A
IO < 1 A
|IO < 1 A
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
10 V
15 V
5 V
-
-
-
-
-
-
VOH
VOL
IOH
4.95
4.95
4.95
10 V
15 V
5 V
9.95
-
9.95
-
9.95
-
14.95
-
14.95
-
14.95
-
-
0.05
0.05
0.05
1.7
0.52
1.3
3.6
-
-
0.05
0.05
0.05
1.4
0.44
1.1
3.0
-
-
0.05
0.05
0.05
10 V
15 V
5 V
-
-
-
-
-
-
VO = 2.5 V
VO = 4.6 V
VO = 9.5 V
VO = 13.5 V
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
-
-
-
1.1 mA
0.36 mA
0.9 mA
2.4 mA
5 V
-
-
-
10 V
15 V
5 V
-
-
-
-
-
-
IOL
LOW-level output current
0.52
0.44
0.36
-
-
-
mA
mA
mA
10 V
15 V
15 V
5 V
1.3
-
1.1
-
0.9
3.6
-
3.0
-
2.4
II
input leakage current
supply current
-
-
-
-
-
0.3
20
40
80
-
-
-
-
-
-
0.3
20
40
80
7.5
-
-
-
-
-
1.0 A
150 A
300 A
600 A
IDD
IO = 0 A
10 V
15 V
-
CI
input capacitance
-
pF
HEF4014B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
5 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Tamb = 25 C; VSS = 0 V.
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula[1]
103 ns + (0.55 ns/pF)CL
44 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
88 ns + (0.55 ns/pF)CL
39 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
Min
-
Typ
130
55
40
115
50
40
60
30
20
35
15
12
10
5
Max
Unit
ns
tPHL
tPLH
tt
HIGH to LOW
propagation delay
CP to Qn;
see Figure 4
260
10 V
15 V
5 V
-
110
ns
-
80
ns
LOW to HIGH
propagation delay
CP to Qn;
see Figure 4
-
230
ns
10 V
15 V
5 V
-
100
ns
-
80
ns
[2]
transition time
pulse width
set-up time
Qn output;
see Figure 4
-
120
ns
10 V
15 V
5 V
-
60
40
-
ns
-
ns
tW
CP input;
minimum width;
see Figure 5
70
30
24
40
25
15
+35
+25
25
+35
+25
25
+25
20
15
30
20
15
30
20
15
6
ns
10 V
15 V
5 V
-
ns
-
ns
tsu
PE CP;
see Figure 5
-
ns
10 V
15 V
5 V
-
ns
0
-
ns
DS CP;
see Figure 5
5
5
0
-
ns
10 V
15 V
5 V
-
ns
-
ns
Dn CP;
see Figure 5
5
5
0
-
ns
10 V
15 V
5 V
-
ns
-
ns
th
hold time
PE CP;
see Figure 5
5
0
-
ns
10 V
15 V
5 V
-
ns
0
-
ns
DS CP;
see Figure 5
15
10
7
-
ns
10 V
15 V
5 V
-
ns
-
ns
Dn CP;
see Figure 5
15
10
7
-
ns
10 V
15 V
5 V
-
ns
-
ns
fclk(max)
maximum clock
frequency
see Figure 5
13
30
40
-
MHz
MHz
MHz
10 V
15 V
15
20
-
-
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2] tt is the same as tTHL and tTLH
.
HEF4014B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
6 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (W)
PD = 900 fi + (fo CL) VDD
Where:
2
PD
dynamic power
dissipation
fi = input frequency in MHz;
2
fo = output frequency in MHz;
CL = output load capacitance in pF;
10 V
15 V
PD = 4300 fi + (fo CL) VDD
2
PD = 12000 fi + (fo CL) VDD
VDD = supply voltage in V;
(CL fo) = sum of the outputs.
12. Waveforms
V
I
V
CP input
M
V
SS
t
t
PLH
PHL
V
OH
90 %
V
M
Qn output
10 %
V
OL
t
t
t
t
001aaj456
Measurement points are given in Table 9.
Fig 4. CP to Qn propagation delays and output transition times
V
I
50 %
50 %
50 %
50 %
CP input
V
SS
t
f
clk(max)
W
t
t
h
su
t
r
V
I
D input
50 % 50 %
V
SS
t
f
t
t
h
su
t
t
h
su
V
I
50 % 50 %
50 %
50 %
PE input
V
SS
t
t
h
su
V
I
DS input
50 % 50 %
V
SS
001aae559
The shaded areas indicate where change is permitted for predictable output performance.
Set-up and hold times are shown as positive values but may be specified as negative values.
Measurement points are given in Table 9.
Fig 5. Minimum clock pulse width, and set-up and hold times for PE to CP, DS to CP, and D to CP
HEF4014B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
7 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
Table 9.
Measurement points
Supply voltage
VDD
Input
VM
Output
VM
5 V to 15 V
0.5VDD
0.5VDD
V
DD
V
V
O
I
G
DUT
C
L
R
T
001aag182
Test data is given in Table 10;
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 6. Test circuit
Table 10. Test data
Supply voltage
VDD
Input
Load
VI
tr, tf
CL
5 V to 15 V
VSS or VDD
20 ns
50 pF
HEF4014B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
8 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 7. Package outline SOT38-4 (DIP16)
HEF4014B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
9 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 8. Package outline SOT109-1 (SO16)
HEF4014B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
10 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
14. Revision history
Table 11. Revision history
Document ID
HEF4014B v.8
Modifications:
Release date
20111121
Data sheet status
Change notice
Supersedes
Product data sheet
-
HEF4014B v.7
• Legal pages updated.
• Changes in “General description” and “Features and benefits”.
HEF4014B v.7
20110914
20091102
20090624
20090122
19950101
19950101
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product specification
Product specification
-
-
-
-
-
-
HEF4014B v.6
HEF4014B v.5
HEF4014B v.4
HEF4014B_CNV v.3
HEF4014B_CNV v.2
-
HEF4014B v.6
HEF4014B v.5
HEF4014B v.4
HEF4014B_CNV v.3
HEF4014B_CNV v.2
HEF4014B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
11 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
HEF4014B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
12 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4014B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
13 of 14
HEF4014B
NXP Semiconductors
8-bit static shift register
17. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 21 November 2011
Document identifier: HEF4014B
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