BUK100-50GL,127 [NXP]
BUK100-50GL - PowerMOS transistor Logic level TOPFET TO-220 3-Pin;型号: | BUK100-50GL,127 |
厂家: | NXP |
描述: | BUK100-50GL - PowerMOS transistor Logic level TOPFET TO-220 3-Pin 局域网 开关 脉冲 晶体管 |
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Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK100-50GL
DESCRIPTION
QUICK REFERENCE DATA
Monolithic temperature and
SYMBOL
PARAMETER
MAX.
UNIT
overload protected logic level power
MOSFET in a 3 pin plastic
VDS
ID
Continuous drain source voltage
Continuous drain current
50
13.5
40
150
125
V
A
W
˚C
mΩ
envelope, intended as a general
purpose switch for automotive
systems and other applications.
PD
Tj
Total power dissipation
Continuous junction temperature
Drain-source on-state resistance
RDS(ON)
APPLICATIONS
VIS = 5 V
General controller for driving
lamps
motors
solenoids
heaters
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Vertical power DMOS output
stage
Low on-state resistance
Overload protection against
over temperature
Overload protection against
short circuit load
Latched overload protection
reset by input
DRAIN
O/V
CLAMP
POWER
INPUT
MOSFET
5 V logic compatible input level
Control of power MOSFET
and supply of overload
protection circuits
RIG
LOGIC AND
derived from input
PROTECTION
Low operating input current
ESD protection on input pin
Overvoltage clamping for turn
off of inductive loads
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - TO220AB
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
D
S
tab
TOPFET
input
drain
2
I
P
3
source
tab drain
1 2 3
November 1996
1
Rev 1.300
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK100-50GL
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
Continuous off-state drain source
VIS = 0 V
-
50
V
voltage1
VIS
ID
ID
IDRM
PD
Tstg
Tj
Continuous input voltage
Continuous drain current
Continuous drain current
Repetitive peak on-state drain current
Total power dissipation
Storage temperature
-
0
-
-
-
-
6
V
A
A
Tmb ≤25 ˚C; VIS = 5 V
Tmb ≤100 ˚C; VIS = 5 V
Tmb ≤ 25 ˚C; VIS = 5 V
Tmb ≤ 25 ˚C
13.5
8.5
54
40
150
150
A
W
˚C
˚C
-
-55
-
Continuous junction temperature2
normal operation
Tsold
Lead temperature
during soldering
-
250
˚C
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload.
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VISP
Protection supply voltage3
for valid protection
4
-
V
Over temperature protection
VDDP(T)
Protected drain source supply voltage VIS = 5 V
-
50
V
Short circuit load protection
VDDP(P)
PDSM
Protected drain source supply voltage4 VIS = 5 V
-
-
35
0.6
V
kW
Instantaneous overload dissipation
Tmb = 25 ˚C
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
IDROM
EDSM
Repetitive peak clamping current
Non-repetitive clamping energy
VIS = 0 V
-
-
15
200
A
mJ
T
mb ≤ 25 ˚C; IDM = 15 A;
DD ≤ 20 V; inductive load
mb ≤ 95 ˚C; IDM = 4 A;
DD ≤ 20 V; f = 250 Hz
V
T
V
EDRM
Repetitive clamping energy
-
20
mJ
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VC
Electrostatic discharge capacitor
voltage
Human body model;
C = 250 pF; R = 1.5 kΩ
-
2
kV
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch.
3 The input voltage for which the overload protection circuits are functional.
4 The device is able to self-protect against a short circuit load providing the drain-source supply voltage does not exceed VDDP(P) maximum.
For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.
November 1996
2
Rev 1.300
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK100-50GL
THERMAL CHARACTERISTICS
SYMBOL PARAMETER
Thermal resistance
CONDITIONS
MIN. TYP. MAX. UNIT
Rth j-mb
Rth j-a
Junction to mounting base
Junction to ambient
-
-
-
2.5
60
3.1
-
K/W
K/W
in free air
STATIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(CL)DSS
V(CL)DSS
Drain-source clamping voltage VIS = 0 V; ID = 10 mA
50
-
-
-
-
V
V
Drain-source clamping voltage VIS = 0 V; IDM = 1 A; tp ≤ 300 µs;
δ ≤ 0.01
70
IDSS
IDSS
IDSS
RDS(ON)
Zero input voltage drain current VDS = 12 V; VIS = 0 V
Zero input voltage drain current VDS = 50 V; VIS = 0 V
Zero input voltage drain current VDS = 40 V; VIS = 0 V; Tj = 125 ˚C
-
-
-
-
0.5
1
10
85
10
20
100
125
µA
µA
µA
Drain-source on-state
resistance
VIS = 5 V; IDM = 7.5 A; tp ≤ 300 µs;
δ ≤ 0.01
mΩ
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Short circuit load protection1 Tmb = 25 ˚C; L ≤ 10 µH
EDS(TO)
td sc
Overload threshold energy
Response time
VDD = 13 V; VIS = 5 V
VDD = 13 V; VIS = 5 V
-
-
0.2
0.8
-
-
J
ms
Over temperature protection
Tj(TO)
Threshold junction temperature VIS = 5 V; from ID ≥ 1 A2
150
-
-
˚C
INPUT CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
SYMBOL PARAMETER
VIS(TO) Input threshold voltage
IIS
CONDITIONS
MIN. TYP. MAX. UNIT
VDS = 5 V; ID = 1 mA
VIS = 5 V; normal operation
1.0
-
1.5
0.2
2.6
2.0
0.35
3.5
V
mA
V
Input supply current
VISR
Protection reset voltage3
2.0
VISR
Protection reset voltage
Tj = 150 ˚C
1.0
-
-
IISL
V(BR)IS
RIG
Input supply current
Input clamp voltage
Input series resistance
VIS = 5 V; protection latched
II = 10 mA
to gate of power MOSFET
0.5
6
-
1.2
-
4
2.0
-
-
mA
V
kΩ
1 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for
PDSM, which is always the case when VDS is less than VDSP maximum. Refer to OVERLOAD PROTECTION LIMITING VALUES.
2 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID
ensures this condition.
3 The input voltage below which the overload protection circuits will be reset.
November 1996
3
Rev 1.300
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK100-50GL
TRANSFER CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
gfs
Forward transconductance
VDS = 10 V; IDM = 7.5 A tp ≤ 300 µs;
δ ≤ 0.01
5
9
-
S
ID(SC)
Drain current1
VDS = 13 V; VIS = 5 V
-
25
-
A
SWITCHING CHARACTERISTICS
Tmb = 25 ˚C. RI = 50 Ω . Refer to waveform figures and test circuits.
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
td on
tr
td off
tf
td on
tr
td off
tf
Turn-on delay time
Rise time
VDD = 13 V; VIS = 5 V
resistive load RL = 4 Ω
VDD = 13 V; VIS = 0 V
resistive load RL = 4 Ω
VDD = 13 V; VIS = 5 V
inductive load IDM = 3 A
VDD = 13 V; VIS = 0 V
inductive load IDM = 3 A
-
-
-
-
-
-
-
-
1.5
8
-
-
-
-
-
-
-
-
µs
µs
µs
µs
µs
µs
µs
µs
Turn-off delay time
Fall time
6
4.5
1.5
1
Turn-on delay time
Rise time
Turn-off delay time
Fall time
10
0.5
REVERSE DIODE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
13.5
UNIT
IS
Continuous forward current
Tmb ≤ 25 ˚C; VIS = 0 V
-
A
REVERSE DIODE CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
VSDS
trr
Forward voltage
IS = 15 A; VIS = 0 V; tp = 300 µs
not applicable2
-
-
1.0
-
1.5
-
V
-
Reverse recovery time
ENVELOPE CHARACTERISTICS
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Ld
Ld
Ls
Internal drain inductance
Internal drain inductance
Internal source inductance
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
-
-
3.5
4.5
7.5
-
-
-
nH
nH
nH
1 During overload before short circuit load protection operates.
2 The reverse diode of this type is not intended for applications requiring fast reverse recovery.
November 1996
4
Rev 1.300
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK100-50GL
Normalised Power Derating
Zth / (K/W)
BUK100-50GL
PD%
120
10
1
110
100
90
80
70
60
50
40
30
20
10
0
D =
0.5
0.2
0.1
0.05
0.1
0.02
t
T
p
p
t
P
D =
D
0
t
T
0.01
0
20
40
60
80
Tmb /
100
120
140
1E-07
1E-05
1E-03
t / s
1E-01
1E+01
C
Fig.2. Normalised limiting power dissipation.
PD% = 100 PD/PD(25 ˚C) = f(Tmb)
Fig.5. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
ID / A
BUK100-50GL
VIS / V =
120
110
100
90
80
70
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
6
5.5
5
4.5
4
3.5
3
2.5
0
0
20
40
60
80
Tmb /
100
120
140
0
4
8
12
16
VDS / V
20
24
28
32
C
Fig.3. Normalised continuous drain current.
ID% = 100 ID/ID(25 ˚C) = f(Tmb); conditions: VIS = 5 V
Fig.6. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VIS; tp = 250 µs & tp < td sc
ID & IDM / A
BUK100-50GL
ID / A
BUK100-50GL
100
10
1
40
35
30
25
20
15
10
5
VIS / V =
tp =
10 us
6
5.5
RDS(ON) = VDS/ID
5
100 us
1 ms
4.5
DC
4
10 ms
100 ms
3.5
3
Overload protection characteristics not shown
10 100
0.1
0
1
0
1
2
3
4
5
VDS / V
VDS / V
Fig.4. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.7. Typical on-state characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VIS; tp = 250 µs
November 1996
5
Rev 1.300
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK100-50GL
RDS(ON) / Ohm
0.20
BUK100-50GL
a
Normalised RDS(ON) = f(Tj)
VIS / V =
3.5
4
4.5
5
5.5
6
1.5
1.0
0.5
0
0.15
0.10
0.05
0
5
15
25
35
0
10
20
30
-60 -40 -20
0
20 40 60 80 100 120 140
ID / A
Tj /
C
Fig.8. Typical on-state resistance, Tj = 25 ˚C.
Fig.11. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 7.5 A; VIS = 5 V
RDS(ON) = f(ID); parameter VIS; tp = 250 µs
ID / A
BUK100-50GL
td sc / ms
BUK100-50GL
40
35
30
25
20
15
10
5
100
10
1
PDSM
0
0.1
0
2
4
6
8
0.01
0.1
1
VIS / V
PDS / kW
Fig.9. Typical transfer characteristics, Tj = 25 ˚C.
Fig.12. Typical overload protection characteristics.
ID = f(VIS) ; conditions: VDS = 10 V; tp = 250 µs
td sc = f(PDS); conditions: VIS ≥ 4 V; Tj = 25 ˚C.
gfs / S
PDSM%
120
BUK100-50GL
12
11
10
9
100
80
60
40
20
0
8
7
6
5
4
3
2
1
0
0
10
20
30
40
50
-60
-40
-20
0
20
40
60
80
100 120 140
Tmb / C
ID / A
Fig.10. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 10 V; tp = 250 µs
Fig.13. Normalised limiting overload dissipation.
PDSM% =100 PDSM/PDSM(25 ˚C) = f(Tmb)
November 1996
6
Rev 1.300
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK100-50GL
IIS / uA
BUK100-50GL
BUK100-50GL
Energy & Time
1
500
400
300
200
100
0
Time / ms
0.5
25 C
Tj(TO)
Energy / J
150 C
0
-60
-20
20
60
100
140
180
220
0
2
4
6
8
10
Tmb / C
VIS / V
Fig.14. Typical overload protection characteristics.
Conditions: VDD = 13 V; VIS = 5 V; SC load = 30 mΩ
Fig.17. Typical DC input characteristics.
IIS = f(VIS); normal operation, parameter: Tj
ID / A
BUK100-50GL
IISL / mA
BUK100-50GL
20
15
10
5
3
2
1
0
PROTECTION LATCHED
typ.
RESET
NORMAL
0
50
60
70
0
2
4
6
8
VDS / V
VIS / V
Fig.15. Typical clamping characteristics, 25 ˚C.
Fig.18. Typical DC input characteristics, Tj = 25 ˚C.
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 50 µs
IISL = f(VIS); overload protection operated
ID = 0 A
VIS(TO) / V
IS / A
60
BUK100-50GL
max.
2
50
40
30
20
10
0
typ.
min.
1
0
-60 -40 -20
0
20
40
Tj /
60
C
80 100 120 140
0
0.2
0.4
0.6
0.8
1
1.2
1.4
VSD / V
Fig.16. Input threshold voltage.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
Fig.19. Typical reverse diode current, Tj = 25 ˚C.
IS = f(VSDS); conditions: VIS = 0 V; tp = 250 µs
November 1996
7
Rev 1.300
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK100-50GL
VDD
VDD = VCL
RL
LD
t
: adjust for correct ID
p
D
D
TOPFET
TOPFET
I
I
P
P
D.U.T.
D.U.T.
R
I
R
I
VIS
VIS
S
S
ID measure
ID measure
0V
0V
0R1
0R1
Fig.20. Test circuit for resistive load switching times.
Fig.23. Test circuit for inductive load switching times.
RESISTIVE TURN-ON
VDS / V
BUK100-50GL
INDUCTIVE TURN-ON
VDS / V
BUK100-50GL
10
5
10
5
td on
tr
td on
tr
VIS / V
ID / A
VIS / V
ID / A
90%
90%
10%
10%
10%
10%
0
0
0
10
time / us
20
0
10
time / us
20
Fig.21. Typical switching waveforms, resistive load.
Fig.24. Typical switching waveforms, inductive load.
DD = 13 V; ID = 3 A; RI = 50 Ω, Tj = 25 ˚C.
VDD = 13 V; RL = 4 Ω; RI = 50 Ω, Tj = 25 ˚C.
V
RESISTIVE TURN-OFF
td off
BUK100-50GL
VDS / V
INDUCTIVE TURN-OFF
BUK100-50GL
VDS / V
15
10
5
10
5
td off
tf
tf
VIS / V
90%
VIS / V
90%
ID / A
90%
90%
ID / A
10%
10%
0
0
0
10
time / us
20
0
10
time / us
20
Fig.22. Typical switching waveforms, resistive load.
Fig.25. Typical switching waveforms, inductive load.
VDD = 13 V; RL = 4 Ω; RI = 50 Ω, Tj = 25 ˚C.
VDD = 13 V; ID = 3 A; RI = 50 Ω, Tj = 25 ˚C.
November 1996
8
Rev 1.300
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK100-50GL
EDSM%
120
Iiso normalised to 25 C
110
100
90
80
70
60
50
40
30
20
10
0
1.5
1
0.5
0
20
40
60
80
Tmb / C
100
120
140
-60
-20
20
60
Tj / C
100
140
180
Fig.26. Normalised limiting clamping energy.
EDSM% = f(Tmb); conditions: ID = 15 A; VIS = 5 V
Fig.29. Normalised input current (normal operation).
IIS/IIS25 ˚C = f(Tj); VIS = 5 V
V(CL)DSS
VDS
Iisl normalised to 25 C
VDD
VDD
+
-
0
1.5
L
ID
VDS
0
D
S
VIS
TOPFET
-ID/100
1
D.U.T.
0
I
P
Schottky
R 01
shunt
RIS
0.5
-60
-20
20
60
Tj / C
100
140
180
Fig.27. Clamping energy test circuit, RIS = 50 Ω.
Fig.30. Normalised input current (protection latched).
IISL/IISL25 ˚C = f(Tj); VIS = 5 V
EDSM = 0.5 LID2 V(CL)DSS/(V(CL)DSS − VDD
)
Idss
1 mA
100 uA
10 uA
1 uA
typ.
100 nA
0
20
40
60
80
Tj / C
100
120
140
Fig.28. Typical off-state leakage current.
DSS = f(Tj); Conditions: VDS = 40 V; IIS = 0 V.
I
November 1996
9
Rev 1.300
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK100-50GL
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
4,5
max
10,3
max
1,3
3,7
2,8
5,9
min
15,8
max
3,0 max
not tinned
3,0
13,5
min
1,3
1 2 3
max
(2x)
0,9 max (3x)
0,6
2,4
2,54 2,54
Fig.31. TO220AB; pin 2 connected to mounting base.
Notes
1. Refer to mounting instructions for TO220 envelopes.
2. Epoxy meets UL94 V0 at 1/8".
November 1996
10
Rev 1.300
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK100-50GL
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
November 1996
11
Rev 1.300
相关型号:
BUK102-50DL127
TRANSISTOR 45 A, 50 V, 0.035 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB, FET General Purpose Power
NXP
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