BUK101-50_技术文档

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK101-50DL

DESCRIPTION

QUICK REFERENCE DATA

Monolithic temperature and

SYMBOL

PARAMETER

MAX.

UNIT

overload protected logic level power

MOSFET in a 3 pin plastic

V_DS

I_D

Continuous drain source voltage

Continuous drain current

50

26

75

150

60

V

A

W

˚C

mΩ

envelope, intended as a general

purpose switch for automotive

systems and other applications.

P_D

T_j

Total power dissipation

Continuous junction temperature

Drain-source on-state resistance

R_DS(ON)

APPLICATIONS

I_ISL

Input supply current

V_IS= 5 V

650

µA

General controller for driving

lamps

motors

solenoids

heaters

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Vertical power DMOS output

stage

Low on-state resistance

Overload protection against

over temperature

Overload protection against

short circuit load

Latched overload protection

reset by input

DRAIN

O/V

CLAMP

POWER

INPUT

MOSFET

5 V logic compatible input level

Control of power MOSFET

and supply of overload

protection circuits

RIG

LOGIC AND

derived from input

PROTECTION

Lower operating input current

permits direct drive by

micro-controller

ESD protection on input pin

Overvoltage clamping for turn

off of inductive loads

SOURCE

Fig.1. Elements of the TOPFET.

PINNING - TO220AB

PIN CONFIGURATION

SYMBOL

1

DESCRIPTION

D

S

tab

TOPFET

input

drain

2

I

P

3

source

tab drain

1 2 3

April 1993

1

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK101-50DL

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DS

V_IS

I_D

Continuous drain source voltage¹

-

0

-

50

6

26

16

100

75

V

A

W

˚C

Continuous input voltage

Continuous drain current

Repetitive peak on-state drain current

Total power dissipation

T_mb≤25 ˚C; V_IS= 5 V

T_mb≤100 ˚C; V_IS= 5 V

T_mb≤ 25 ˚C; V_IS= 5 V

T_mb≤ 25 ˚C

I_D

I_DRM

P_D

T_stg

T_j

Storage temperature

-

-55

-

150

Continuous junction temperature²

normal operation

T_sold

Lead temperature

during soldering

-

250

˚C

OVERLOAD PROTECTION LIMITING VALUES

With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload.

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_ISP

Protection supply voltage³

for valid protection

4

-

V

Over temperature protection

V_DDP(T)

Protected drain source supply voltage V_IS= 5 V

-

50

V

Short circuit load protection⁴

V_DDP(P)

P_DSM

Protected drain source supply voltage⁵V_IS= 5 V

-

20

1.3

V

kW

Instantaneous overload dissipation

T_mb= 25 ˚C

OVERVOLTAGE CLAMPING LIMITING VALUES

At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

I_DROM

E_DSM

Repetitive peak clamping current

Non-repetitive clamping energy

V_IS= 0 V

-

26

625

A

mJ

T

_mb≤ 25 ˚C; I_DM= 26 A;

_DD≤ 20 V; inductive load

_mb≤ 95 ˚C; I_DM= 8 A;

_DD≤ 20 V; f = 250 Hz

V

T

V

E_DRM

Repetitive clamping energy

-

40

mJ

ESD LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_C

Electrostatic discharge capacitor

voltage

Human body model;

C = 250 pF; R = 1.5 kΩ

-

2

kV

1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.

2 A higher T_jis allowed as an overload condition but at the threshold T_j(TO)the over temperature trip operates to protect the switch.

3 The input voltage for which the overload protection circuits are functional.

4 For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.

5 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for

P_DSM, which is always the case when V_DSis less than V_DDP(P)maximum.

April 1993

2

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK101-50DL

THERMAL CHARACTERISTICS

SYMBOL PARAMETER

Thermal resistance

CONDITIONS

MIN. TYP. MAX. UNIT

R_{th j-mb}

R_{th j-a}

Junction to mounting base

Junction to ambient

-

1.3

60

1.67

-

K/W

in free air

STATIC CHARACTERISTICS

T_mb= 25 ˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

V_(CL)DSS

Drain-source clamping voltage V_IS= 0 V; I_D= 10 mA

50

-

V

Drain-source clamping voltage V_IS= 0 V; I_DM= 2 A; t_p≤ 300 µs;

δ ≤ 0.01

70

I_DSS

R_DS(ON)

Zero input voltage drain current V_DS= 12 V; V_IS= 0 V

Zero input voltage drain current V_DS= 50 V; V_IS= 0 V

Zero input voltage drain current V_DS= 40 V; V_IS= 0 V; T_j= 125 ˚C

-

0.5

1

10

45

10

20

100

60

µA

Drain-source on-state

V_IS= 5 V; I_DM= 13 A; t_p≤ 300 µs;

δ ≤ 0.01

mΩ

resistance¹

OVERLOAD PROTECTION CHARACTERISTICS

TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Short circuit load protection²T_mb= 25 ˚C; L ≤ 10 µH; R_L= 10 mΩ

E_DS(TO)

Overload threshold energy

Response time

V_DD= 13 V; V_IS= 5 V

-

0.4

0.8

45

-

J

ms

A

t_{d sc}

I_D(SC)

Drain current³

I_DM(SC)

Peak drain current⁴

V_IS= 5 V; V_DD= 13 V

-

105

-

A

Over temperature protection

T_j(TO)

Threshold junction temperature V_IS= 5 V; from I_D≥ 1 A⁵

150

-

˚C

TRANSFER CHARACTERISTIC

T_mb= 25 ˚C

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

10 16

g_fs

Forward transconductance

V_DS= 10 V; I_DM= 13 A t_p≤ 300 µs;

δ ≤ 0.01

-

S

1 Continuous input voltage. The specified pulse width is for the drain current.

2 Refer to OVERLOAD PROTECTION LIMITING VALUES.

3 Continuous drain-source supply voltage. Pulsed input voltage.

4 Continuous input voltage. Momentary short circuit load connection. (The higher peak current is due to the effect of capacitance Cgd).

5 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum I_D

ensures this condition.

April 1993

3

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK101-50DL

INPUT CHARACTERISTICS

T_mb= 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.

SYMBOL PARAMETER

V_IS(TO)Input threshold voltage

I_IS

CONDITIONS

MIN. TYP. MAX. UNIT

V_DS= 5 V; I_D= 1 mA

normal operation;

1.0

100

-

2.0

1.0

1.5

200

160

2.6

-

2.0

350

270

3.5

-

V

µA

V

Input supply current

V_IS= 5 V

V_IS= 4 V

T_j= 25 ˚C

T_j= 150 ˚C

V_ISR

I_ISL

Protection reset voltage¹

Input supply current

protection latched;

I_I= 10 mA

V_IS= 5 V

V_IS= 3.5 V

-

6

-

330

240

-

33

50

650

430

-

µA

V

kΩ

V_(BR)IS

R_IG

Input breakdown voltage

Input series resistance

to gate of power MOSFET

T_j= 25 ˚C

T_j= 150 ˚C

-

SWITCHING CHARACTERISTICS

T_mb= 25 ˚C. R_I= 50 Ω . Refer to waveform figure and test circuit.

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

t_{d on}

t_r

t_{d off}

t_f

Turn-on delay time

Rise time

V_DD= 13 V; V_IS= 5 V

resistive load R_L= 2.1 Ω

V_DD= 13 V; V_IS= 0 V

resistive load R_L= 2.1 Ω

-

17

75

60

70

-

µs

Turn-off delay time

Fall time

REVERSE DIODE LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

26

UNIT

I_S

Continuous forward current

T_mb≤ 25 ˚C; V_IS= 0 V

-

A

REVERSE DIODE CHARACTERISTICS

T_mb= 25 ˚C

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

V_SDO

t_rr

Forward voltage

I_S= 26 A; V_IS= 0 V; t_p= 300 µs

not applicable²

-

1.0

-

1.5

-

V

-

Reverse recovery time

1 The input voltage below which the overload protection circuits will be reset.

2 The reverse diode of this type is not intended for applications requiring fast reverse recovery.

April 1993

4

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK101-50DL

ENVELOPE CHARACTERISTICS

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

L_d

L_s

Internal drain inductance

Internal source inductance

Measured from contact screw on

tab to centre of die

Measured from drain lead 6 mm

from package to centre of die

Measured from source lead 6 mm

from package to source bond pad

-

3.5

4.5

7.5

-

nH

Normalised Power Derating

PD%

BUK101-50DL

ID & IDM / A

120

110

100

90

80

70

60

50

40

30

20

10

0

1000

100

10

Overload protection characteristics not shown

tp =

RDS(ON) = VDS/ID

100 us

1 ms

DC

10 ms

100 ms

1

0

20

40

60

80

Tmb /

100

120

140

1

10

100

C

VDS / V

Fig.2. Normalised power dissipation.

P_D% = 100 P_D/P_D(25 ˚C) = f(T_mb)

Fig.4. Safe operating area. T_mb= 25 ˚C

I_D& I_DM= f(V_DS); I_DMsingle pulse; parameter t_p

Normalised Current Derating

Zth / (K/W)

BUK101-50DL

ID%

10

1

120

110

100

90

80

70

60

50

40

30

20

10

0

D =

0.5

0.2

0.1

0.01

0.05

p

t

tp

P

D =

D

0.02

T

t

T

0

20

40

60

80

Tmb /

100

120

140

1E-07

1E-05

1E-03

t / s

1E-01

1E+01

C

Fig.3. Normalised continuous drain current.

I_D% = 100 I_D/I_D(25 ˚C) = f(T_mb); conditions: V_IS= 5 V

Fig.5. Transient thermal impedance.

Z_{th j-mb}= f(t); parameter D = t_p/T

April 1993

5

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK101-50DL

ID / A

50

BUK101-50DL

td sc / ms

BUK101-50DL

100

10

1

VIS / V =

6

5.5

5

40

30

20

10

0

4.5

4

PDSM

3.5

3

0.1

1

3

5

0

2

4

0.1

1

10

VDS / V

PDS / kW

Fig.6. Typical on-state characteristics, T_j= 25 ˚C.

ID = f(V_DS); parameter V_IS; t_p= 2 ms

Fig.9. Typical overload protection characteristics.

t_{d sc}= f(P_DS); conditions: V_IS≥ 4 V; T_j= 25 ˚C.

PDSM%

120

RDS / mOhm

BUK101-50DL

120

100

80

60

40

20

0

VIS / V =

3.5

4.5

5

4

100

80

60

40

20

0

5.5

6

-60

-40

-20

0

20

40

60

80

100 120 140

0

20

40

Tmb / C

ID / A

Fig.7. Typical on-state resistance, T_j= 25 ˚C.

R_DS(ON)= f(I_D); parameter V_IS; t_p= 2 ms

Fig.10. Normalised limiting overload dissipation.

P_DSM% =100 P_DSM/P_DSM(25 ˚C) = f(T_mb)

Energy & Time

a

BUK101-50DL

Normalised RDS(ON) = f(Tj)

1

0.5

0

1.5

1.0

0.5

0

Time / ms

Energy / J

Tj(TO)

140

-60 -40 -20

0

20 40 60 80 100 120 140

-60

-20

20

60

100

Tmb / C

180

220

Tj /

C

Fig.8. Normalised drain-source on-state resistance.

a = R_DS(ON)/R_DS(ON)25 ˚C = f(T_j); I_D= 13 A; V_IS= 5 V

Fig.11. Typical overload protection characteristics.

Conditions: V_DD= 13 V; V_IS= 5 V; SC load = 30 mΩ

April 1993

6

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK101-50DL

IS / A

ID / A

30

BUK101-50DL

100

50

0

20

10

0

typ.

0

1

2

50

60

70

VSD / V

VIS / V

Fig.12. Typical clamping characteristics, 25 ˚C.

Fig.15. Typical reverse diode current, T_j= 25 ˚C.

I_S= f(V_SDS); conditions: V_IS= 0 V

I_D= f(V_DS); conditions: V_IS= 0 V; t_p≤ 50 µs

VIS(TO) / V

VDD

max.

2

RL

typ.

D

min.

TOPFET

1

I

P

D.U.T.

R

I

VIS

S

ID measure

0

0V

-60 -40 -20

0

20

40

Tj /

60

C

80 100 120 140

0R1

Fig.13. Input threshold voltage.

V_IS(TO)= f(T_j); conditions: I_D= 1 mA; V_DS= 5 V

Fig.16. Test circuit for resistive load switching times.

IISL & IIS / uA

BUK101-50DL

600

500

400

300

200

100

0

VIS / V & VDS / V

VDS

BUK101-50DL

15

10

5

PROTECTION LATCHED

IISL

RESET

VIS

IIS

NORMAL

0

2

4

6

0

200

400

time / us

600

VIS / V

Fig.14. Typical DC input characteristics, T_j= 25 ˚C.

I_ISL& I_IS= f(V_IS); protection latched & normal operation

Fig.17. Typical switching waveforms, resistive load.

_DD= 13 V; R_L= 2.1 Ω; R_I= 50 Ω, T_j= 25 ˚C.

V

April 1993

7

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK101-50DL

EDSM%

120

Idss

1 mA

100 uA

10 uA

1 uA

110

100

90

80

70

60

50

40

30

20

10

0

typ.

100 nA

0

20

40

60

80

100

120

140

0

20

40

60

80

Tj / C

100

120

140

Tmb / C

Fig.18. Normalised clamping energy rating.

E_DSM% = f(T_mb); conditions: I_D= 26 A; V_IS= 5 V

Fig.20. Typical off-state leakage current.

I_DSS= f(T_j); Conditions: V_DS= 40 V; I_IS= 0 V.

Iiso & Iisl normalised to 25 C

V(CL)DSS

VDS

VDD

+

-

1.5

0

L

ID

VDS

0

D

S

VIS

TOPFET

-ID/100

1

D.U.T.

0

I

P

Schottky

R 01

shunt

RIS

0.5

-60

-20

20

60

Tj / C

100

140

180

Fig.19. Clamping energy test circuit, R_IS= 50 Ω.

E_DSM= 0.5 LI_D²V_(CL)DSS/(V_(CL)DSS− V_DD

Fig.21. Normalised input currents (normal & latched).

I_ISO/I_ISO25˚C & I_ISL/I_ISL25˚C = f(T_j); V_IS= 5 V

)

April 1993

8

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK101-50DL

MECHANICAL DATA

Dimensions in mm

Net Mass: 2 g

4,5

max

10,3

max

1,3

3,7

2,8

5,9

min

15,8

max

3,0 max

not tinned

3,0

13,5

min

1,3

1 2 3

max

(2x)

0,9 max (3x)

0,6

2,4

2,54 2,54

Fig.22. TO220AB; pin 2 connected to mounting base.

Notes

1. Refer to mounting instructions for TO220 envelopes.

2. Epoxy meets UL94 V0 at 1/8".

April 1993

9

Rev 1.100

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK101-50DL

DEFINITIONS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Electronics N.V. 1996

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

April 1993

10

Rev 1.100


型号：	BUK101-50
厂家：	NXP
描述：	PowerMOS transistor Logic level TOPFET 功率MOS晶体管逻辑电平TOPFET 晶体晶体管
文件：	总10页 (文件大小：93K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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