935235170118 [NXP]
Bus Driver, LVC/LCX/Z Series, 16-Func, 1-Bit, True Output, CMOS, PDSO48;
| 型号： | 935235170118 |
| 厂家： | 
NXP |
| 描述： | Bus Driver, LVC/LCX/Z Series, 16-Func, 1-Bit, True Output, CMOS, PDSO48 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总20页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with
5 V tolerant inputs/outputs (3-state)
Product specification
2002 Oct 02
Supersedes data of 1998 Mar 17
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
FEATURES
DESCRIPTION
• 5 V tolerant inputs/outputs for interfacing with 5V logic
• Wide supply voltage range from 1.2 to 3.6 V
• Complies with JEDEC standard no. 8-1A
• CMOS low power consumption
• MULTIBYTETM flow-through standard pin-out
architecture
The 74LVC(H)16373A is a 16-bit D-type transparent latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. One Latch Enable
(LE) input and one Output Enable (OE) are provided for
each octal. Inputs can be driven from either 3.3 or 5 V
devices. In 3-state operation, outputs can handle 5 V.
These features allow the use of these devices in a mixed
3.3 and 5 V environment.
• Low inductance multiple power and ground pins for
minimum noise and ground bounce
The 74LVC(H)16373A consists of 2 sections of eight
D-type transparent latches with 3-state true outputs. When
LE is HIGH, data at the Dn inputs enter the latches. In this
condition the latches are transparent, i.e., a latch output
will change each time its corresponding D-input changes.
• Direct interface with TTL levels
• All data inputs have bus hold (74LVCH16373A only)
• High-impedance when VCC = 0 V.
When LE is LOW the latches store the information that was
present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the eight latches are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The 74LVCH16373A bus hold data inputs eliminates the
need for external pull up resistors to hold unused inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
propagation delay:
CONDITIONS
TYPICAL
UNIT
t
PHL/tPLH
CL = 50 pF; VCC = 3.3 V
Dn to Qn
3.0
3.4
5.0
26
ns
ns
LE to Qn
CI
input capacitance
power dissipation per latch
pF
pF
CPD
VCC = 3.3 V; note 1
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacity in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
2002 Oct 02
2
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74LVC16373ADL
−40 to +85 °C
−40 to +85 °C
−40 to +85 °C
−40 to +85 °C
48
48
48
48
TSSOP-48
TSSOP-48
TSSOP-48
TSSOP-48
plastic
plastic
plastic
plastic
SOT370-1
SOT362-1
SOT370-1
SOT362-1
74LVC16373ADGG
74LVCH16373ADL
74LVCH16373ADGG
PINNING
PIN
SYMBOL
1OE
DESCRIPTION
handbook, halfpage
1
output enable input (active
LOW)
1OE
1
1LE
48
47
46
1Q0
1Q1
1D0
1D1
2
3
4
5
6
7
8
9
2, 3, 5, 6, 8, 1Q0 to 1Q7 data inputs/outputs
9, 11, 12
4, 10, 15,
21, 28, 34,
39, 45
GND
ground (0 V)
GND
1Q2
1Q3
45 GND
1D2
1D3
44
43
42
41
40
7, 18, 31,
42
VCC
supply voltage
V
V
CC
CC
13, 14, 16, 2Q0 to 2Q7 data inputs/outputs
17, 19, 20,
22, 23
1Q4
1Q5
1D4
1D5
24
2OE
2LE
output enable input
(active LOW)
GND 10
39 GND
1Q6
1Q7
2Q0
2Q1
1D6
1D7
2D0
2D1
11
12
13
14
38
37
36
35
25
latch enable input
(active HIGH)
36, 35, 33, 2D0 to 2D7 data inputs
32, 30, 29,
27, 26
GND 15
34 GND
47, 46, 44, 1D0 to 1D7 data inputs
2Q2
16
2D2
33
43, 41, 40,
38, 37
2Q3
2D3
17
18
19
20
32
31
30
29
48
1LE
latch enable input (active
HIGH)
V
V
CC
CC
2Q4
2D4
2D5
2Q5
GND 21
28 GND
2Q6
2Q7
2D6
2D7
2LE
22
23
27
26
25
2OE 24
MGU767
Fig.1 Pin configuration.
2002 Oct 02
3
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
1D0
1Q0
2D0
2Q0
D
Q
D
Q
LATCH
1
LATCH
9
LE LE
LE LE
1LE
2LE
1OE
2OE
to 7 other channels
to 7 other channels
MGU769
Fig.2 Logic diagram.
1
48
24
25
handbook, halfpage
1
24
1EN
C3
1OE
handbook, halfpage
1LE
2OE
2LE
1OE
2OE
2EN
C4
2
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1Q
0
3
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2
3
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
3D
1
5
6
5
8
6
9
8
11
12
13
14
16
17
19
20
22
23
9
11
12
13
14
16
17
19
20
22
23
4D
2
1LE
48
2LE
25
MGU768
MGU770
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
2002 Oct 02
4
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
V
handbook, halfpage
CC
data input
to internal circuit
MGU771
Fig.5 Bus hold circuit.
FUNCTION TABLE
Per section of eight bits; note 1
INPUT
LE
INTERNAL OUTPUTS
OPERATING MODES
LATCHES
Q0 TO Q7
OE
Dn
Enable and read register (transparent mode)
L
L
H
H
L
L
H
l
L
H
L
L
H
L
Latch and read register
L
L
L
h
l
H
L
H
Z
Z
Latch register and disable outputs
H
H
L
L
h
H
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
2002 Oct 02
5
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
2.7
MAX.
3.6
UNIT
for maximum speed performance
for low voltage applications
V
1.2
0
3.6
5.5
VCC
5.5
+85
V
VI
input voltage
V
VO
output voltage
output HIGH or LOW state
output 3-state
0
V
0
V
Tamb
tr, tf
operating ambient
temperature
in free-air
−40
°C
input rise and fall times
VCC = 1.2 to 2.7 V
VCC = 2.7 to 3.6 V
0
0
20
10
ns/V
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V);
note 1.
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
TYP.
MAX.
+6.5
UNIT
−
V
IIK
input diode current
input voltage
VI < 0
note 2
−
−50
−
−
V
V
V
V
VI
−0.5
−
+6.5
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0
±50
−
−
output HIGH or LOW state; −0.5
VCC + 0.5
note 2
output 3-state; note 2
−0.5
−
−
+6.5
−
V
IO
output source or sink current VO = 0 to VCC
VCC or GND current
±50
±100
−
mA
mA
°C
ICC, IGND
−
−
Tstg
Ptot
storage temperature
−65
+150
power dissipation per package
SO
above 70 °C derates
linearly with 8 mW/K
−
−
500
500
−
−
mW
mW
SSOP and TSSOP
above 60 °C derates
linearly with 8 mW/K
Notes
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2002 Oct 02
6
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
−40 to +85
TYP.(1) MAX.
UNIT
OTHER
VCC (V)
MIN.
VCC
2.7 to 3.6 2.0
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
1.2
−
−
−
−
−
−
V
−
V
1.2
−
−
V
V
V
V
−
−
−
−
−
GND
0.8
−
V
2.7 to 3.6
V
VOH
HIGH-level output
voltage
VI = VIH or VIL; IO = −12 mA 2.7
VI = VIH or VIL; IO = −100 µA 3.0
VI = VIH or VIL; IO = −18 mA 3.0
VI = VIH or VIL; IO = −24 mA 3.0
CC − 0.5
V
CC − 0.2 VCC
−
V
CC − 0.6
CC − 0.8
−
−
V
−
−
V
VOL
LOW-level output voltage VI = VIH or VIL; IO = 12 mA
VI = VIH or VIL; IO = 100 µA
2.7
3.0
3.0
3.6
3.6
−
0.40
0.20
0.55
±5
±5
V
−
V
VI = VIH or VIL; IO = 24 mA
−
V
ILI
input leakage current
3-state output OFF-state VI = VIH or VIL;
current VO = 5.5 V or GND
VI = 5.5 V or GND; note 2
±0.1
0.1
µA
µA
IOZ
Ioff
power off leakage current Vi or VO = 5.5 V
0
−
−
−
−
±10
20
µA
µA
µA
ICC
∆ICC
quiescent supply current VI = VCC or GND; IO = 0
3.6
0.1
5
additional quiescent
supply current per input
pin
VI = VCC − 0.6 V; IO = 0
2.7 to 3.6
500
IBHL
bus hold LOW sustaining VI = 0.8 V; notes 3 and 4
current
3.0
3.0
3.6
3.6
75
−
−
−
−
−
−
−
−
µA
µA
µA
µA
IBHH
bus hold HIGH sustaining VI = 2.0 V; notes 3 and 4
current
−75
500
−500
IBHLO
IBHHO
bus hold LOW overdrive notes 3 and 5
current
bus hold HIGH overdrive notes 3 and 5
current
Notes
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2. For bus hold parts, the bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal.
3. Valid for data inputs of bus hold parts (LVCH16373A) only.
4. The specified sustaining current at the data input holds the input below the specified VI level.
5. The specified overdrive current at the data input forces the data input to the opposite logic input state.
2002 Oct 02
7
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
AC CHARACTERISTICS
GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 Ω.
Tamb (°C)
SYMBOL
PARAMETER
WAVEFORMS
−40 to +85
UNIT
MIN.
TYP.
MAX.
VCC = 1.2 V
tPHL/tPLH propagation delay Dn to Qn
see Figs 6 and 10
see Figs 7 and 10
−
−
−
−
−
−
−
12
14
18
11
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
t
t
t
PHL/tPLH propagation delay LE to Qn
PZH/tPZL
PHZ/tPLZ
3-state output enable time OE to Qn see Figs 9 and 10
3-state output enable time OE to Qn see Figs 9 and 10
tW
tsu
th
LE pulse width HIGH
set-up time Dn to LE
hold time Dn to LE
see Fig.7
see Fig.8
see Fig.8
−
−
VCC = 2.7 V
tPHL/tPLH propagation delay Dn to Qn
see Figs 6 and 10 1.5
see Figs 7 and 10 1.5
−
−
−
−
−
−
−
5.7
5.8
6.5
6.4
−
ns
ns
ns
ns
ns
ns
ns
tPHL/tPLH propagation delay LE to Qn
tPZH/tPZL
3-state output enable time OE to Qn see Figs 9 and 10 1.5
3-state output enable time OE to Qn see Figs 9 and 10 1.5
tPHZ/tPLZ
tW
tsu
th
LE pulse width HIGH
set-up time Dn to LE
hold time Dn to LE
see Fig.7
see Fig.8
see Fig.8
3
1.7
1.2
−
−
VCC = 3.3 ±0.3 V; note1
tPHL/tPLH propagation delay Dn to Qn
see Figs 6 and 10 1.5
see Figs 7 and 10 1.5
3.0
3.4
3.5
3.9
2.0
−0.1
0.1
4.7
4.8
5.5
5.4
−
ns
ns
ns
ns
ns
ns
ns
t
t
t
PHL/tPLH propagation delay LE to Qn
PZH/tPZL
PHZ/tPLZ
3-state output enable time OE to Qn see Figs 9 and 10 1.5
3-state output enable time OE to Qn see Figs 9 and 10 1.5
tW
tsu
th
LE pulse width HIGH
set-up time Dn to LE
hold time Dn to LE
see Fig.7
see Fig.8
see Fig.8
3
+1.7
1.2
−
−
Note
1. Typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2002 Oct 02
8
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
AC WAVEFORMS
V
handbook, halfpage
I
V
V
M
Dn input
M
GND
t
t
PLH
PHL
V
OH
V
Qn output
M
MGU772
V
OL
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig.6 Input (Dn) to output (Qn) propagation delays.
V
handbook, halfpage
I
LE input
GND
V
t
V
V
M
M
M
t
W
t
PHL
PLH
V
OH
V
V
M
Qn output
M
V
OL
MGU773
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig.7 Latch enable input (LE) pulse width, and the latch enable input to output (Qn) propagation delays.
2002 Oct 02
9
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
V
I
V
Dn input
M
GND
t
t
h
h
t
t
su
su
V
I
V
LE input
M
GND
MGU774
The shaded areas indicate when the input is permitted to change for predictable performance.
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig.8 Data set-up and hold times for the Dn input to the LE input.
V
I
OE input
V
V
M
M
t
GND
t
PLZ
PZL
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MGU775
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5VCC at VCC < 2.7 V.
VX = VOL + 0.3 V at VCC ≥ 2.7 V.
VX = VOL + 0.1VCC at VCC < 2.7 V.
VY = VOH − 0.3 V at VCC ≥ 2.7 V.
VY = VOH − 0.1VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig.9 3-state enable and disable times.
2002 Oct 02
10
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
S1
2 × V
open
GND
CC
V
CC
R
L
500 Ω
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
R
L
C
R
L
T
500 Ω
MGU776
VCC
VI
<2.7 V
VCC
2.7 to 3.6
2.7 V
TEST
S1
Definitions for test circuits:
RL = Load resistor.
tPLH/tPHL
open
tPLZ/tPZL
2 x VCC
GND
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
tPHZ/tPZH
Fig.10 Load circuitry for switching times.
2002 Oct 02
11
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
PACKAGE OUTLINES
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
H
v
M
A
E
Z
25
48
Q
A
2
A
A
(A )
3
1
θ
pin 1 index
L
p
L
24
1
detail X
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
8o
0o
0.4
0.2
2.35
2.20
0.3
0.2
0.22 16.00
0.13 15.75
7.6
7.4
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
mm
2.8
0.25
0.635
1.4
0.25
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
99-12-27
SOT370-1
MO-118
2002 Oct 02
12
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.25
0.5
1
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-10
99-12-27
SOT362-1
MO-153
2002 Oct 02
13
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical dwell time is 4 seconds at 250 °C.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 Oct 02
14
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
suitable
suitable
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, not suitable(3)
HVSON, SMS
PLCC(4), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
not recommended(4)(5) suitable
not recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Oct 02
15
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2002 Oct 02
16
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
NOTES
2002 Oct 02
17
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
NOTES
2002 Oct 02
18
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state)
74LVC16373A;
74LVCH16373A
NOTES
2002 Oct 02
19
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/05/pp20
Date of release: 2002 Oct 02
Document order number: 9397 750 10037
相关型号：
935235170512
LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48
NXP
935235170518
LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48
NXP
935235180112
IC LVC/LCX/Z SERIES, 16 1-BIT DRIVER, TRUE OUTPUT, PDSO48, 7.50 MM, PLASTIC, MO-118AA, SOT-370-1, SSOP3-48, Bus Driver/Transceiver
NXP
935235190118
IC LVC/LCX/Z SERIES, 16 1-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, SOT-362-1, TSSOP2-48, Bus Driver/Transceiver
NXP
935237440118
IC TELECOM, CORDLESS, BASEBAND CIRCUIT, PDSO16, PLASTIC, SOT-369, SSOP-16, Cordless Telephone IC
NXP
935237450518
IC TELECOM, CORDLESS, BASEBAND CIRCUIT, PDSO14, PLASTIC, SOT-108, SOP-14, Cordless Telephone IC
NXP
935237670112
IC LVC/LCX/Z SERIES, 16 1-BIT DRIVER, TRUE OUTPUT, PDSO48, PLASTIC, SOT-370, SSOP-48, Bus Driver/Transceiver
NXP
935237670118
IC LVC/LCX/Z SERIES, 16 1-BIT DRIVER, TRUE OUTPUT, PDSO48, PLASTIC, SOT-370, SSOP-48, Bus Driver/Transceiver
NXP
935237680112
IC LVC/LCX/Z SERIES, 16 1-BIT DRIVER, TRUE OUTPUT, PDSO48, PLASTIC, SOT-362, TSSOP-48, Bus Driver/Transceiver
NXP
©2020 ICPDF网 联系我们和版权申明