935237460112 [NXP]

IC HORIZ/VERT DEFLECTION IC, PDIP32, PLASTIC, SDIP-32, Deflection IC;


型号：	935237460112
厂家：	NXP
描述：	IC HORIZ/VERT DEFLECTION IC, PDIP32, PLASTIC, SDIP-32, Deflection IC 光电二极管
文件：	总63页 (文件大小：318K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

TDA4853; TDA4854

I²C-bus autosync deflection

controllers for PC/TV monitors

Product speciﬁcation

1999 Jul 13

Supersedes data of 1998 May 12

File under Integrated Circuits, IC02

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

FEATURES

Concept features

• Full horizontal plus vertical autosync capability; TV and

VCR mode included

• Extended horizontal frequency range from

15 to 130 kHz

Vertical section

• Comprehensive set of I²C-bus driven geometry

• I²C-bus controllable vertical picture size, picture

adjustments and functions, including standby mode

position, linearity (S-correction) and linearity balance

• Output for I²C-bus controllable vertical sawtooth and

parabola (for pin unbalance and parallelogram)

• Very good vertical linearity

• Moire cancellation

• Start-up and switch-off sequence for safe operation of

all power components

• Vertical picture size independent of frequency

• Differential current outputs for DC coupling to vertical

booster

• X-ray protection

• Flexible switched mode B+ supply function block for

feedback and feed forward converter

• 50 to 160 Hz vertical autosync range.

• Internally stabilized voltage reference

East-West (EW) section

• Drive signal for focus amplifiers with combined

horizontal and vertical parabola waveforms (TDA4854)

• I²C-bus controllable output for horizontal pincushion,

horizontal size, corner and trapezium correction

• DC controllable inputs for Extremely High Tension

(EHT) compensation

• Optional tracking of EW drive waveform with line

frequency selectable by I²C-bus.

• SDIP32 package.

Focus section of TDA4854

Synchronization

• I²C-bus controllable output for horizontal and vertical

parabolas

• Can handle all sync signals (horizontal, vertical,

composite and sync-on-video)

• Vertical parabola is independent of frequency and tracks

with vertical adjustments

• Output for video clamping (leading/trailing edge

selectable by I²C-bus), vertical blanking and protection

blanking

• Horizontal parabola independent of frequency

• Pre-correction of delay in focus output stage.

• Output for fast unlock status of horizontal

synchronization and blanking on grid 1 of picture tube.

Horizontal section

• I²C-bus controllable wide range linear picture position,

pin unbalance and parallelogram correction via

horizontal phase

• Frequency-locked loop for smooth catching of horizontal

frequency

• TV mode at 15.625 or 15.750 kHz selectable by I²C-bus

• Simple frequency preset of f_minand f_maxby external

resistors

• Low jitter

• Soft start for horizontal and B+ control drive signals.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

GENERAL DESCRIPTION

The TDA4854 provides extended functions e.g. as a

flexible B+ control, an extensive set of geometry control

facilities, and a combined output for horizontal and vertical

focus signals.

The TDA4854 is a high performance and efficient solution

for autosync monitors. All functions are controllable by

I²C-bus.

The TDA4853 is an economy version of the TDA4854,

especially designed for use in 14” and 15” monitors with

combined EHT generation. It provides the same features

as the TDA4854 except for the dynamic focus block.

The TDA4854 provides synchronization processing,

horizontal and vertical synchronization with full autosync

capability, a TV/VCR mode and very short settling times

after mode changes. External power components are

given a great deal of protection. The IC generates the drive

waveforms for DC-coupled vertical boosters such as the

TDA486x and TDA835x.

Together with the I²C-bus driven Philips TDA488x video

processor family, a very advanced system solution is

offered.

QUICK REFERENCE DATA

SYMBOL

V_CC

PARAMETER

MIN.

9.2

TYP. MAX. UNIT

supply voltage

supply current

−

I_CC

−

I_CC(stb)

VSIZE

VGA

supply current during standby mode

vertical size

−

100

−

VGA overscan for vertical size

vertical position

16.8

±11.5

−

VPOS

VLIN

−

vertical linearity (S-correction)

vertical linearity balance

−2

−

−46

−

VLINBAL

V_HSIZE

V_HPIN

±2.5

−

horizontal size voltage

0.13

0.04

0.02

−

3.6

1.42

0.69

−

horizontal pincushion voltage (EW parabola)

horizontal size modulation voltage

horizontal trapezium correction voltage

horizontal corner correction voltage

horizontal position

−

V_HEHT

V_HTRAP

V_HCOR

HPOS

HPARAL

HPINBAL

T_amb

−

±0.33

−

−0.64

−

+0.08

−

±13

±1

−

°C

horizontal parallelogram

−

EW pin unbalance

−

operating ambient temperature

−20

+70

ORDERING INFORMATION

TYPE

PACKAGE

NUMBER

NAME

DESCRIPTION

VERSION

TDA4853

TDA4854

SDIP32

plastic shrink dual in-line package; 32 leads (400 mil)

SOT232-1

1999 Jul 13

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EHT compensation

via vertical size

7 V

EHT compensation

via horizontal size

100

(5%)

150

kΩ

1.2 V

(1%)

VREF

VCAP

VAGC

VSMOD

HSMOD

EWDRV

VERTICAL

SYNC INPUT

AND POLARITY

CORRECTION

VERTICAL

SYNC

INTEGRATOR

VERTICAL

OSCILLATOR

AND AGC

EHT COMPENSATION

EW-OUTPUT

VERTICAL OUTPUT

VSYNC 14

(TTL level)

VOUT2

VOUT1

HORIZONTAL SIZE

AND

VERTICAL SIZE

HORIZONTAL PINCUSHION

HORIZONTAL CORNER

HORIZONTAL TRAPEZIUM

HORIZONTAL SIZE

VERTICAL LINEARITY

BALANCE

VIDEO CLAMPING

AND

VERTICAL BLANK

VERTICAL POSITION

VERTICAL SIZE, VOVSCN

CLBL 16

clamping

blanking

OUTPUT

ASYMMETRIC

EW-CORRECTION

20 ASCOR

HUNLOCK

OUTPUT

HUNLOCK

PROTECTION

AND SOFT START

TDA4853

SDA

SCL

I C-BUS

RECEIVER

X-RAY

I C-BUS REGISTERS

BDRV

BSENS

BOP

(2)

B+ CONTROL

APPLICATION

B+

CONTROL

9.2 to 16 V

SUPPLY

AND

REFERENCE

COINCIDENCE DETECTOR

FREQUENCY DETECTOR

TV MODE

PGND

SGND

X-RAY

PROTECTION

BIN

H/C SYNC INPUT

AND POLARITY

CORRECTION

PLL1 AND

HORIZONTAL

POSITION

PLL2, PARALLELOGRAM,

PIN UNBALANCE AND

SOFT START

HORIZONTAL

OUTPUT

STAGE

HSYNC

HDRV

HORIZONTAL

OSCILLATOR

(TTL level)

MGM101

(video)

HPLL1 HBUF

HREF

HCAP

HPLL2

HFLB

XSEL XRAY

i.c.

10 nF

(2%)

8.2 nF

HBUF

(1)

3.3 kΩ

8.2

HREF

(1%)

100 nF

(1) For the calculation of f_Hrange see Section “Calculation of line frequency range”.

(2) See Figs 23 and 24.

Fig.1 Block diagram and application circuit of TDA4853.

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EHT compensation

via vertical size

7 V

EHT compensation

via horizontal size

100

(5%)

150

kΩ

1.2 V

(1%)

VREF

VCAP

VAGC

VSMOD

HSMOD

EWDRV

VERTICAL

SYNC INPUT

AND POLARITY

CORRECTION

VERTICAL

SYNC

INTEGRATOR

VERTICAL

OSCILLATOR

AND AGC

EHT COMPENSATION

EW-OUTPUT

VERTICAL OUTPUT

VSYNC 14

(TTL level)

VOUT2

VOUT1

HORIZONTAL SIZE

AND

VERTICAL SIZE

HORIZONTAL PINCUSHION

HORIZONTAL CORNER

HORIZONTAL TRAPEZIUM

HORIZONTAL SIZE

VERTICAL LINEARITY

BALANCE

VIDEO CLAMPING

AND

VERTICAL BLANK

VERTICAL POSITION

VERTICAL SIZE, VOVSCN

CLBL 16

clamping

blanking

OUTPUT

ASYMMETRIC

EW-CORRECTION

20 ASCOR

32 FOCUS

HUNLOCK

OUTPUT

HUNLOCK

PROTECTION

AND SOFT START

FOCUS

TDA4854

HORIZONTAL

AND VERTICAL

SDA

SCL

I C-BUS

RECEIVER

X-RAY

I C-BUS REGISTERS

BDRV

BSENS

BOP

(2)

B+ CONTROL

APPLICATION

B+

CONTROL

9.2 to 16 V

SUPPLY

AND

REFERENCE

PGND

SGND

COINCIDENCE DETECTOR

FREQUENCY DETECTOR

TV MODE

X-RAY

PROTECTION

BIN

H/C SYNC INPUT

AND POLARITY

CORRECTION

PLL1 AND

HORIZONTAL

POSITION

PLL2, PARALLELOGRAM,

PIN UNBALANCE AND

SOFT START

HORIZONTAL

OUTPUT

STAGE

HSYNC

HDRV

HORIZONTAL

OSCILLATOR

(TTL level)

MGM065

(video)

HPLL1 HBUF

HREF

HCAP

HPLL2

HFLB

XSEL XRAY

10 nF

(2%)

8.2 nF

HBUF

(1)

3.3 kΩ

8.2

HREF

(1%)

100 nF

(1) For the calculation of f_Hrange see Section “Calculation of line frequency range”.

(2) See Figs 23 and 24.

Fig.2 Block diagram and application circuit of TDA4854.

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

PINNING

SYMBOL

HFLB

DESCRIPTION

horizontal ﬂyback input

X-ray protection input

B+ control OTA output

B+ control comparator input

B+ control OTA input

B+ control driver output

power ground

XRAY

BOP

BSENS

BIN

BDRV

PGND

HDRV

XSEL

horizontal driver output

select input for X-ray reset

supply voltage

V_CC

EWDRV

VOUT2

VOUT1

VSYNC

HSYNC

CLBL

EW waveform output

vertical output 2 (ascending sawtooth)

vertical output 1 (descending sawtooth)

vertical synchronization input

horizontal/composite synchronization input

video clamping pulse/vertical blanking output

HUNLOCK

SCL

horizontal synchronization unlock/protection/vertical blanking output

I²C-bus clock input

I²C-bus data input/output

SDA

ASCOR

VSMOD

VAGC

VREF

VCAP

SGND

HPLL1

HBUF

HREF

HCAP

HPLL2

HSMOD

i.c.

output for asymmetric EW corrections

input for EHT compensation (via vertical size)

external capacitor for vertical amplitude control

external resistor for vertical oscillator

external capacitor for vertical oscillator

signal ground

external ﬁlter for PLL1

buffered f/v voltage output

reference current for horizontal oscillator

external capacitor for horizontal oscillator

external ﬁlter for PLL2/soft start

input for EHT compensation (via horizontal size)

internally connected; note 1: TDA4853

output for horizontal and vertical focus: TDA4854

FOCUS

Note

1. External connections to this pin are not allowed.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

handbook, halfpage

HFLB

XRAY

BOP

i.c.

HFLB

XRAY

BOP

FOCUS

HSMOD

HPLL2

HCAP

HREF

HSMOD

HPLL2

HCAP

HREF

HBUF

HPLL1

SGND

VCAP

VREF

VAGC

VSMOD

ASCOR

SDA

BSENS

BIN

BSENS

BIN

BDRV

PGND

HDRV

XSEL

BDRV

PGND

HDRV

XSEL

HBUF

HPLL1

SGND

VCAP

TDA4853

TDA4854

VREF

EWDRV

VOUT2

VOUT1

VSYNC

HSYNC

CLBL

EWDRV

VOUT2

VOUT1

VSYNC

HSYNC

CLBL

VAGC

VSMOD

ASCOR

SDA

SCL

HUNLOCK

MGM066

MGM067

Fig.3 Pin configuration for TDA4853.

Fig.4 Pin configuration for TDA4854.

FUNCTIONAL DESCRIPTION

Vertical sync integrator

Horizontal sync separator and polarity correction

Normalized composite sync signals from HSYNC are

integrated on an internal capacitor in order to extract

vertical sync pulses. The integration time is dependent on

the horizontal oscillator reference current at HREF

(pin 28). The integrator output directly triggers the vertical

oscillator.

HSYNC (pin 15) is the input for horizontal synchronization

signals, which can be DC-coupled TTL signals (horizontal

or composite sync) and AC-coupled negative-going video

sync signals. Video syncs are clamped to 1.28 V and

sliced at 1.4 V. This results in a fixed absolute slicing level

of 120 mV related to top sync.

Vertical sync slicer and polarity correction

For DC-coupled TTL signals the input clamping current is

limited. The slicing level for TTL signals is 1.4 V.

Vertical sync signals (TTL) applied to VSYNC (pin 14) are

sliced at 1.4 V. The output signal of the sync slicer is

integrated on an internal capacitor to detect and normalize

the sync polarity. The output signals of vertical sync

integrator and sync normalizer are disjuncted before they

are fed to the vertical oscillator.

The separated sync signal (either video or TTL) is

integrated on an internal capacitor to detect and normalize

the sync polarity.

Normalized horizontal sync pulses are used as input

signals for the vertical sync integrator, the PLL1 phase

detector and the frequency-locked loop.

The presence of equalization pulses is allowed for correct

function of the PLL1 phase detector only in TV mode.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

Video clamping/vertical blanking generator

The internal frequency detector then starts tuning the

oscillator. Very small DC currents at HPLL1 (pin 26) are

used to perform this tuning with a well defined change rate.

When coincidence between horizontal sync and oscillator

frequency is detected, the search mode is first replaced by

a soft-lock mode which lasts for the first part of the next

vertical period. The soft-lock mode is then replaced by a

normal PLL operation. This operation ensures smooth

tuning and avoids fast changes of horizontal frequency

during catching.

The video clamping/vertical blanking signal at CLBL

(pin 16) is a two-level sandcastle pulse which is especially

suitable for video ICs such as the TDA488x family, but also

for direct applications in video output stages.

The upper level is the video clamping pulse, which is

triggered by the horizontal sync pulse. Either the leading or

trailing edge can be selected by setting control bit CLAMP

via the I²C-bus. The width of the video clamping pulse is

determined by an internal single-shot multivibrator.

In this concept it is not allowed to load HPLL1.

The lower level of the sandcastle pulse is the vertical

blanking pulse, which is derived directly from the internal

oscillator waveform. It is started by the vertical sync and

stopped with the start of the vertical scan. This results in

optimum vertical blanking. Two different vertical blanking

The frequency dependent voltage at this pin is fed

internally to HBUF (pin 27) via a sample-and-hold and

buffer stage. The sample-and-hold stage removes all

disturbances caused by horizontal sync or composite

vertical sync from the buffered voltage. An external

times are accessible, by control bit VBLK, via the I²C-bus. resistor connected between pins HBUF and HREF defines

the frequency range.

Blanking will be activated continuously if one of the

following conditions is true:

Out-of-lock indication (pin HUNLOCK)

Soft start of horizontal and B+ drive [voltage at HPLL2

Pin HUNLOCK is floating during search mode if no sync

(pin 30) pulled down externally or by the I²C-bus]

pulses are applied, or if a protection condition is true.

All this can be detected by the microcontroller if a pull-up

resistor is connected to its own supply voltage.

PLL1 is unlocked while frequency-locked loop is in

search mode or if horizontal sync pulses are absent

No horizontal flyback pulses at HFLB (pin 1)

For an additional fast vertical blanking at grid 1 of the

picture tube a 1 V signal referenced to ground is available

X-ray protection is activated

Supply voltage at V_CC(pin 10) is low (see Fig.25).

at this output. The continuous protection blanking

(see Section “Video clamping/vertical blanking generator”)

is also available at this pin. Horizontal unlock blanking can

be switched off, by control bit BLKDIS via the I²C-bus

while vertical blanking is maintained.

Horizontal unlock blanking can be switched off, by control

bit BLKDIS, via the I²C-bus while vertical blanking and

protection blanking is maintained.

Frequency-locked loop

TV mode

The frequency-locked loop can lock the horizontal

oscillator over a wide frequency range. This is achieved by

a combined search and PLL operation. The frequency

range is preset by two external resistors and the

In applications with TV signals the standard

frequency-to-voltage converter operation will be disturbed

by equalizing sync pulses and phase jumps occurring in

VCR signals. To avoid this, a TV mode has been

implemented. It can be accessed by choosing the

horizontal TV sync frequencies of 15.625 or 15.75 kHz as

the minimum frequency for the horizontal oscillator.

Applying TV signals will cause the frequency-to-voltage

converter to scan down to this frequency in normal

operation. If the control bit TVMOD is sent by the I²C-bus,

the HBUF output is clamped to 2.5 V and an internally

defined PLL1 control range of ±10% is established.

To return to standard operation of the

6.5

-------

--^m----^a--^x-

f_min

recommended maximum ratio is

This can, for instance, be a range from 15.625 to 90 kHz

with all tolerances included.

Without a horizontal sync signal the oscillator will be

free-running at f_min. Any change of sync conditions is

detected by the internal coincidence detector. A deviation

of more than 4% between horizontal sync and oscillator

frequency will switch the horizontal section into search

mode. This means that PLL1 control currents are switched

off immediately.

frequency-to-voltage converter the bit TVMOD has to be

reset. For an optimal operation with VCR signals the RC

combination at pin HPLL1 has to be switched externally.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

Horizontal oscillator

The resistor R_HBUFparis calculated as the value of R_HREF

and R_HBUFin parallel. The formulae for R_HBUFalso takes

into account the voltage swing across this resistor

The horizontal oscillator is of the relaxation type and

requires a capacitor of 10 nF to be connected at HCAP

(pin 29). For optimum jitter performance the value of 10 nF

must not be changed.

_HREF× R

R_HBUF

^HBUFpar× 0.8 = 805 Ω

---------------------------------------------

_HREF– R_HBUFpar

The minimum oscillator frequency is determined by a

resistor connected between pin HREF and ground.

A resistor connected between pins HREF and HBUF

defines the frequency range.

PLL1 phase detector

The phase detector is a standard type using switched

current sources, which are independent of the horizontal

frequency. It compares the middle of the horizontal sync

with a fixed point on the oscillator sawtooth voltage.

The PLL1 loop filter is connected to HPLL1 (pin 26).

The reference current at pin HREF also defines the

integration time constant of the vertical sync integration.

Calculation of line frequency range

See also Section “Horizontal position adjustment and

corrections”.

The oscillator frequencies f_minand f_maxmust first be

calculated. This is achieved by adding the spread of the

relevant components to the highest and lowest sync

frequencies f_sync(min)and f_sync(max). The oscillator is driven

Horizontal position adjustment and corrections

A linear adjustment of the relative phase between the

horizontal sync and the oscillator sawtooth (in PLL1 loop)

is achieved via register HPOS. Once adjusted, the relative

phase remains constant over the whole frequency range.

by the currents in R_HREFand R_HBUF

The following example is a 31.45 to 90 kHz application:

Table 1 Calculation of total spread

Correction of pin unbalance and parallelogram is achieved

by modulating the phase between the oscillator sawtooth

and horizontal flyback (in loop PLL2) via registers

HPARAL and HPINBAL. If those asymmetric EW

corrections are performed in the deflection stage, both

registers can be disconnected from the horizontal phase

via control bit ACD. This does not change the output at

pin ASCOR.

spread of

for f_max

for f_min

C_HCAP

±3%

±2%

±7%

±5%

±2%

±9%

R_HREF, R_HBUF

Total

Horizontal moire cancellation

Thus the typical frequency range of the oscillator in this

example is:

To achieve a cancellation of horizontal moire (also known

as ‘video moire’), the horizontal frequency is

f_max= f_sync(max)× 1.07 = 96.3 kHz

divided-by-two to achieve a modulation of the horizontal

phase via PLL2. The amplitude is controlled by

the polarity changes with half of the vertical frequency.

Control bit MOD disables the moire cancellation function.

f_sync(min)

f_min

= 28.9 kHz

----------------------

1.09

The TV mode is centred around f_minwith a control range of

±10%. Activation of the TV mode is only allowed between

15.625 and 35 kHz.

The resistors R_HREFand R_HBUFparcan be calculated using

the following formulae:

78 × kHz × kΩ

_min+ 0.0012 × f_m²_in[kHz]

R_HREF

= 2.61 kΩ

-----------------------------------------------------------------

78 × kHz × kΩ

_max+ 0.0012 × f_m²_ax[kHz]

R_HBUFpar

= 726 Ω

--------------------------------------------------------------------

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

PLL2 phase detector

Output stage for line drive pulses [HDRV (pin 8)]

The PLL2 phase detector is similar to the PLL1 detector

and compares the line flyback pulse at HFLB (pin 1) with

the oscillator sawtooth voltage. The control currents are

independent of the horizontal frequency. The PLL2

detector thus compensates for the delay in the external

horizontal deflection circuit by adjusting the phase of the

HDRV (pin 8) output pulse.

An open-collector output stage allows direct drive of an

inverting driver transistor because of a low saturation

voltage of 0.3 V at 20 mA. To protect the line deflection

transistor, the output stage is disabled (floating) for a low

supply voltage at V_CC(see Fig.25).

The duty cycle of line drive pulses is slightly dependent on

the actual horizontal frequency. This ensures optimum

drive conditions over the whole frequency range.

For the TDA4854 external modulation of the PLL2 phase

is not allowed, because this would disturb the start

advance of the horizontal focus parabola.

X-ray protection

The X-ray protection input XRAY (pin 2) provides a voltage

detector with a precise threshold. If the input voltage at

XRAY exceeds this threshold for a certain time then

control bit SOFTST is reset, which switches the IC into

protection mode. In this mode several pins are forced into

defined states:

Soft start and standby

If HPLL2 is pulled to ground by resetting the

output currents and B+ control driver pulses will be

inhibited. This means that HDRV (pin 8), BDRV (pin 6),

VOUT1 (pin 13) and VOUT2 (pin 12) are floating in this

state. If HPLL2 is pulled to ground by an external DC

current, vertical output currents stay active while HDRV

(pin 8) and BDRV (pin 6) are in floating state. In both cases

the PLL2 and the frequency-locked loop are disabled,

CLBL (pin 16) provides a continuous blanking signal and

HUNLOCK (pin 17) is floating.

HUNLOCK (pin 17) is floating

The capacitor connected to HPLL2 (pin 30) is

discharged

Horizontal output stage (HDRV) is floating

B+ control driver stage (BDRV) is floating

Vertical output stages (VOUT1 and VOUT2) are floating

CLBL provides a continuous blanking signal.

This option can be used for soft start, protection and

power-down modes. When the HPLL2 pin is released

again, an automatic soft start sequence on the horizontal

drive as well as on the B+ drive output will be performed

(see Figs 26 and 27).

There are two different methods of restarting the IC:

1. XSEL (pin 9) is open-circuit or connected to ground.

The control bit SOFTST must be set to logic 1 via the

I²C-bus. The IC then returns to normal operation via

soft start.

A soft start can only be performed if the supply voltage for

the IC is a minimum of 8.6 V.

2. XSEL (pin 9) is connected to V_CCvia an external

resistor. The supply voltage of the IC must be switched

off for a certain period of time before the IC can be

restarted again using the standard power-on

procedure.

The soft start timing is determined by the filter capacitor at

HPLL2 (pin 30), which is charged with a constant current

during soft start. If the voltage at pin 30 (HPLL2) reaches

1.1 V, the vertical output currents are enabled. At 1.7 V the

horizontal driver stage generates very small output pulses.

The width of these pulses increases with the voltage at

HPLL2 until the final duty cycle is reached. The voltage at

HPLL2 increases further and performs a soft start at BDRV

(pin 6) as well. The voltage at HPLL2 continues to rise until

HPLL2 enters its normal operating range. The internal

charge current is now disabled. Finally PLL2 and the

frequency-locked loop are activated. If both functions

reach normal operation, HUNLOCK (pin 17) switches from

the floating status to normal vertical blanking, and

continuous blanking at CLBL (pin 16) is removed.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

Vertical oscillator and amplitude control

Adjustment of vertical size, VGA overscan and EHT

compensation

This stage is designed for fast stabilization of vertical size

after changes in sync frequency conditions.

The amplitude of the differential output currents at VOUT1

and VOUT2 can be adjusted via register VSIZE.

size for the VGA350 mode.

The free-running frequency f_fr(V)is determined by the

resistor R_VREFconnected to pin 23 and the capacitor

C_VCAPconnected to pin 24. The value of R_VREFis not only

VSMOD (pin 21) can be used for a DC controlled EHT

compensation of vertical size by correcting the differential

output currents at VOUT1 and VOUT2. The EW

waveforms, (vertical focus), pin unbalance and

optimized for noise and linearity performance in the whole

vertical and EW section, but also influences several

internal references. Therefore the value of R_VREFmust not

be changed.

parallelogram corrections are not affected by VSMOD.

Capacitor C_VCAPshould be used to select the free-running

The adjustments for vertical size and vertical position also

affect the waveforms of the horizontal pincushion, vertical

linearity (S-correction), vertical linearity balance, focus

parabola, pin unbalance and parallelogram correction.

The result of this interaction is that no re-adjustment of

these parameters is necessary after an adjustment of

vertical picture size or position.

frequency of the vertical oscillator in accordance with the

following formula: f_fr(V)

-----------------------------------------------------------

10.8 × R_VREF× C_VCAP

To achieve a stabilized amplitude the free-running

frequency f_fr(V), without adjustment, should be at least 10%

lower than the minimum trigger frequency.

The contributions shown in Table 2 can be assumed.

Adjustment of vertical position, vertical linearity and

vertical linearity balance

Table 2 Calculation of f_fr(V)total spread

outputs VOUT1 and VOUT2 (pins 13 and 12) and the EW

drive output EWDRV (pin 11) in such a way that the whole

picture moves vertically while maintaining the correct

geometry.

Contributing elements

Minimum frequency offset between f_fr(V)and 10%

lowest trigger frequency

Spread of IC

Spread of R_VREF

Spread of C_VCAP

Total

±3%

±1%

±5%

19%

S-correction in the output signal. This function can be

switched off by control bit VSC.

vertical S-correction in the output signal. This function can

be switched off by control bit VLC.

Result for 50 to 160 Hz application:

50 Hz

f _fr(V)

= 42 Hz

---------------

1.19

Adjustment of vertical moire cancellation

The AGC of the vertical oscillator can be disabled by

setting control bit AGCDIS via the I²C-bus. A precise

external current has to be injected into VCAP (pin 24) to

obtain the correct vertical size. This special application

mode can be used when the vertical sync pulses are

serrated (shifted); this condition is found in some display

modes, e.g. when using a 100 Hz up converter for video

signals.

To achieve a cancellation of vertical moire (also known as

‘scan moire’) the vertical picture position can be modulated

by half the vertical frequency. The amplitude of the

modulation is controlled by register VMOIRE and can be

switched off via control bit MOD.

Application hint: VAGC (pin 22) has a high input

impedance during scan. Therefore, the pin must not be

loaded externally otherwise non-linearities in the vertical

output currents may occur due to the changing charge

current during scan.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

Horizontal pincushion (including horizontal size,

corner correction and trapezium correction)

V_HSIZE

_HSIZE+ V_HEHT1 –

----------------

14.4 V

--------------------------------------------------------------------------

14.4 V

g(HSIZE, HSMOD) = 1 –

EWDRV (pin 11) provides a complete EW drive waveform.

The components horizontal pincushion, horizontal size,

corner correction and trapezium correction are controlled

by the registers HPIN, HSIZE, HCOR and HTRAP.

HTRAP can be set to zero by control bit VPC.

I_HREF

h(I_HREF) =

-------------------------------

I_HREF

f = 70kHz

Two different modes of operation can be chosen for the

EW output waveform via control bit FHMULT:

The pincushion (EW parabola) amplitude, corner and

trapezium correction track with the vertical picture size

(VSIZE) and also with the adjustment for vertical picture

position (VPOS). The corner correction does not track with

the horizontal pincushion (HPIN).

1. Mode 1

Horizontal size is controlled via register HSIZE and

causes a DC shift at the EWDRV output. The complete

waveform is also multiplied internally by a signal

proportional to the line frequency [which is detected

via the current at HREF (pin 28)]. This mode is to be

used for driving EW diode modulator stages which

require a voltage proportional to the line frequency.

Further the horizontal pincushion amplitude, corner and

trapezium correction track with the horizontal picture size,

which is adjusted via register HSIZE and the analog

modulation input HSMOD.

If the DC component in the EWDRV output signal is

increased via HSIZE or I_HSMOD, the pincushion, corner and

trapezium component of the EWDRV output will be

2. Mode 2

The EW drive waveform does not track with the line

frequency. This mode is to be used for driving EW

modulators which require a voltage independent of the

line frequency.

V_HSIZE

_HSIZE+ V_HEHT1 –

----------------

14.4 V

-------------------------------------------------------------------------

14.4

reduced by a factor of 1 –

Output stage for asymmetric correction waveforms

[ASCOR (pin 20)]

The value 14.4 V is a virtual voltage for calculation only.

The output pin can not reach this value, but the gain (and

DC bias) of the external application should be such that the

horizontal deflection is reduced to zero when EWDRV

reaches 14.4 V.

This output is designed as a voltage output for

superimposed waveforms of vertical parabola and

sawtooth. The amplitude and polarity of both signals can

be changed via registers HPARAL and HPINBAL.

HSMOD can be used for a DC controlled EHT

compensation by correcting horizontal size, horizontal

pincushion, corner and trapezium. The control range at

this pin tracks with the actual value of HSIZE. For an

increasing DC component V_HSIZEin the EWDRV output

signal, the DC component V_HEHTcaused by I_HSMODwill be

Application hint: The TDA4854 offers two possibilities to

control registers HPINBAL and HPARAL.

1. Control bit ACD = 1

The two registers now control the horizontal phase by

means of internal modulation of the PLL2 horizontal

phase control. The ASCOR output (pin 20) can be left

unused, but it will always provide an output signal

because the ASCOR output stage is not influenced by

the control bit ACD.

V _HSIZE

reduced by a factor of 1 –

as shown in the equation

----------------

14.4 V

above.

The whole EWDRV voltage is calculated as follows:

2. Control bit ACD = 0

_EWDRV= 1.2 V + [V_HSIZE+ V_HEHT× f(HSIZE) + (V_HPIN

_HCOR+ V_HTRAP) × g(HSIZE, HSMOD)] × h(I_HREF

)

The internal modulation via PLL2 is disconnected.

In order to obtain the required effect on the screen,

pin ASCOR must now be fed to the DC amplifier which

controls the DC shift of the horizontal deflection. This

option is useful for applications which already use a

DC shift transformer.

Where:

V _HEHT

I_HSMOD

× 0.69

-------------------

120 µA

V_HSIZE

f(HSIZE) = 1 –

----------------

14.4 V

If the tube does not need HPINBAL and HPARAL, then pin

ASCOR can be used for other purposes, i.e. for a simple

dynamic convergence.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

TDA4854: dynamic focus section [FOCUS (pin 32)]

• Boost converter in feedback mode (see Fig.23)

In this application the OTA is used as an error amplifier

with a limited output voltage range. The flip-flop is set on

the rising edge of the signal at HDRV. A reset will be

generated when the voltage at BSENS, taken from the

current sense resistor, exceeds the voltage at BOP.

This section generates a complete drive signal for dynamic

focus applications. The amplitude of the horizontal

parabola is internally stabilized, thus it is independent of

the horizontal frequency. The amplitude can be adjusted

via register HFOCUS. Changing horizontal size may

require a correction of HFOCUS. To compensate for the

delay in external focus amplifiers a ‘pre-correction’ for the

phase of the horizontal parabola has been implemented.

The amplitude of the vertical parabola is independent of

frequency and tracks with all vertical adjustments.

The amplitude can be adjusted via register VFOCUS.

FOCUS (pin 32) is designed as a voltage output for the

superimposed vertical and horizontal parabolas.

If no reset is generated within a line period. The rising

edge of the next HDRV pulse forces the flip-flop to reset.

The flip-flop is set immediately after the voltage at

BSENS has dropped below the threshold voltage

V_{RESTART(BSENS)}

• Buck converter in feed forward mode (see Fig.24)

This application uses an external RC combination at

BSENS to provide a pulse width which is independent

from the horizontal frequency. The capacitor is charged

via an external resistor and discharged by the internal

discharge circuit. For normal operation the discharge

circuit is activated when the flip-flop is reset by the

internal voltage comparator. The capacitor will now be

discharged with a constant current until the internally

controlled stop level V_STOP(BSENS)is reached. This level

will be maintained until the rising edge of the next HDRV

pulse sets the flip-flop again and disables the discharge

circuit.

B+ control function block

The B+ control function block of the TDA4853; TDA4854

consists of an Operational Transconductance Amplifier

(OTA), a voltage comparator, a flip-flop and a discharge

circuit. This configuration allows easy applications for

different B+ control concepts. See also Application Note

AN96052: “B+ converter Topologies for Horizontal

Deflection and EHT with TDA4855/58”.

GENERAL DESCRIPTION

If no reset is generated within a line period, the rising

edge of the next HDRV pulse automatically starts the

discharge sequence and resets the flip-flop. When the

voltage at BSENS reaches the threshold voltage

The non-inverting input of the OTA is connected internally

to a high precision reference voltage. The inverting input is

connected to BIN (pin 5). An internal clamping circuit limits

the maximum positive output voltage of the OTA.

The output itself is connected to BOP (pin 3) and to the

inverting input of the voltage comparator.

V_{RESTART(BSENS)}, the discharge circuit will be disabled

automatically and the flip-flop will be set immediately.

This behaviour allows a definition of the maximum duty

cycle of the B+ control drive pulse by the relationship of

charge current to discharge current.

The non-inverting input of the voltage comparator can be

accessed via BSENS (pin 4).

B+ drive pulses are generated by an internal flip-flop and

fed to BDRV (pin 6) via an open-collector output stage.

This flip-flop is set at the rising edge of the signal at HDRV

(pin 8). The falling edge of the output signal at BDRV has

a defined delay of t_d(BDRV)to the rising edge of the HDRV

pulse (see Fig.23). When the voltage at BSENS exceeds

the voltage at BOP, the voltage comparator output resets

the flip-flop and, therefore, the open-collector stage at

BDRV is floating again.

Supply voltage stabilizer, references, start-up

procedures and protection functions

The TDA4853; TDA4854 provides an internal supply

voltage stabilizer for excellent stabilization of all internal

references. An internal gap reference, especially designed

for low-noise, is the reference for the internal horizontal

and vertical supply voltages. All internal reference currents

and drive current for the vertical output stage are derived

from this voltage via external resistors.

An internal discharge circuit allows a well defined

discharge of capacitors at BSENS. BDRV is active at a

LOW-level output voltage (see Figs 23 and 24), thus it

requires an external inverting driver stage.

If either the supply voltage is below 8.3 V or no data from

the I²C-bus has been received after power-up, the internal

soft start and protection functions do not allow any of those

outputs [HDRV, BDRV, VOUT1, VOUT2 and HUNLOCK

(see Fig.25)] to be active.

The B+ function block can be used for B+ deflection

modulators in many different ways. Two popular

application combinations are as follows:

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

For supply voltages below 8.3 V the internal I²C-bus will

not generate an acknowledge and the IC is in standby

mode. This is because the internal protection circuit has

generated a reset signal for the soft start

registers can be loaded. If the register SOFTST has

received a set from the I²C-bus, the internal soft start

procedure is released, which activates all mentioned

outputs.

When the protection mode is active, several pins of the

TDA4853; TDA4854 are forced into a defined state:

HDRV (horizontal driver output) is floating

BDRV (B+ control driver output) is floating

HUNLOCK (indicates, that the frequency-to-voltage

converter is out of lock) is floating (HIGH via external

pull-up resistor)

CLBL provides a continuous blanking signal

VOUT1 and VOUT2 (vertical outputs) are floating

The capacitor at HPLL2 is discharged.

If during normal operation the supply voltage has dropped

below 8.1 V, the protection mode is activated and

HUNLOCK (pin 17) changes to the protection status and is

floating. This can be detected by the microcontroller.

If the soft start procedure is activated via the I²C-bus, all of

these actions will be performed in a well defined sequence

(see Figs 25 and 26).

This protection mode has been implemented in order to

protect the deflection stages and the picture tube during

start-up, shut-down and fault conditions. This protection

mode can be activated as shown in Table 3.

Table 3 Activation of protection mode

ACTIVATION

RESET

Low supply voltage at

pin 10

increase supply voltage;

reload registers;

soft start via I²C-bus

Power dip, below 8.1 V

reload registers;

soft start via I²C-bus

X-ray protection (pin 2)

triggered, XSEL (pin 9) is

open-circuit or connected

to ground

reload registers;

soft start via I²C-bus

X-ray protection (pin 2)

triggered, XSEL (pin 9)

connected to V_CCvia an

external resistor

switch V_CCoff and on

again, reload registers;

soft start via I²C-bus

HPLL2 (pin 30) externally release pin 30

pulled to ground

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); all voltages measured with respect to ground.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V_CC

supply voltage

input voltage for pins:

BIN

−0.5

+16

V_i(n)

−0.5

+6.0

+6.5

+8.0

HSYNC, VSYNC, VREF, HREF, VSMOD and HSMOD

SDA and SCL

XRAY

V_o(n)

output voltage for pins:

VOUT2, VOUT1 and HUNLOCK

BDRV and HDRV

−0.5

−

+6.5

+16

+6.0

100

+10

−10

V_I/O(n)

I_o(HDRV)

I_i(HFLB)

I_o(CLBL)

I_o(BOP)

I_o(BDRV)

I_o(EWDRV)

I_o(FOCUS)

T_amb

input/output voltages at pins BOP and BSENS

horizontal driver output current

horizontal ﬂyback input current

video clamping pulse/vertical blanking output current

B+ control OTA output current

B+ control driver output current

EW driver output current

°C

−10

−

−5

focus driver output current

−

−5

operating ambient temperature

junction temperature

−20

−

+70

150

T_j

T_stg

storage temperature

−55

−150

+150 °C

+150

V_ESD

electrostatic discharge for all pins

note 1

note 2

−2000 +2000 V

Notes

1. Machine model: 200 pF; 0.75 µH; 10 Ω.

2. Human body model: 100 pF; 7.5 µH; 1500 Ω.

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

K/W

R_th(j-a)

thermal resistance from junction to ambient

in free air

QUALITY SPECIFICATION

In accordance with “URF-4-2-59/601”; EMC emission/immunity test in accordance with “DIS 1000 4.6” (IEC 801.6).

SYMBOL

PARAMETER

emission test

immunity test

CONDITIONS

MIN.

TYP.

1.5

2.0

MAX.

UNIT

V_EMC

note 1

−

Note

1. Tests are performed with application reference board. Tests with other boards will have different results.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

CHARACTERISTICS

V_CC= 12 V; T_amb= 25 °C; peripheral components in accordance with Figs 1 and 2; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Horizontal sync separator

INPUT CHARACTERISTICS FOR DC-COUPLED TTL SIGNALS: PIN HSYNC

V_i(HSYNC)

V_HSYNC(sl)

t_r(HSYNC)

sync input signal voltage

slicing voltage level

1.7

−

1.2

0.7

−

1.4

−

1.6

500

−

rise time of sync pulse

fall time of sync pulse

minimum width of sync pulse

input current

µs

µA

t_f(HSYNC)

−

t_{W(HSYNC)(min)}

I_i(HSYNC)

−

V_HSYNC= 0.8 V

_HSYNC= 5.5 V

−

−200

−

INPUT CHARACTERISTICS FOR AC-COUPLED VIDEO SIGNALS (SYNC-ON-VIDEO, NEGATIVE SYNC POLARITY)

V_HSYNC

sync amplitude of video input

signal voltage

R_source= 50 Ω

−

300

−

V_HSYNC(sl)

slicing voltage level

R_source= 50 Ω

120

150

(measured from top sync)

V_clamp(HSYNC)

I_ch(HSYNC)

top sync clamping voltage level R_source= 50 Ω

1.1

1.7

1.28

2.4

1.5

3.4

charge current for coupling

capacitor

V_HSYNC> V_clamp(HSYNC)

µA

t_{W(HSYNC)(min)}

R_source(max)

minimum width of sync pulse

maximum source resistance

differential input resistance

0.7

−

µs

Ω

duty cycle = 7%

during sync

−

1500

R_{i(diff)(HSYNC)}

−

Ω

Automatic polarity correction for horizontal sync

horizontal sync pulse width

related to line period

−

t_P(H)

-----------

t_H

t_d(HPOL)

delay time for changing polarity

0.3

1.8

Vertical sync integrator

t_int(V)integration time for generation f_H= 15.625 kHz;

µs

of a vertical trigger pulse

I_HREF= 0.52 mA

f_H= 31.45 kHz;

I_HREF= 1.052 mA

f_H= 64 kHz;

I_HREF= 2.141 mA

3.9

2.5

5.7

3.8

6.5

4.5

f_H= 100 kHz;

I_HREF= 3.345 mA

Vertical sync slicer (DC-coupled, TTL compatible): pin VSYNC

V_i(VSYNC)

V_VSYNC(sl)

I_i(VSYNC)

sync input signal voltage

slicing voltage level

input current

1.7

1.2

−

1.4

−

1.6

±10

0 V < V_SYNC< 5.5 V

µA

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Automatic polarity correction for vertical sync

t_{W(VSYNC)(max)}

t_d(VPOL)

maximum width of vertical sync

pulse

−

400

µs

delay time for changing polarity

0.45

1.8

Video clamping/vertical blanking output: pin CLBL

t_clamp(CLBL)

V_clamp(CLBL)

width of video clamping pulse

measured at V_CLBL= 3 V

0.6

0.7

0.8

µs

top voltage level of video

clamping pulse

4.32

4.75

5.23

TC_clamp

temperature coefﬁcient of

V_clamp(CLBL)

−

mV/K

ns/V

STPS_clamp

t_{d(HSYNCt-CLBL)}

steepness of slopes for

clamping pulse

R_L= 1 MΩ; C_L= 20 pF

130

delay between trailing edge of clamping pulse triggered

horizontal sync and start of

video clamping pulse

on trailing edge of

horizontal sync;

control bit CLAMP = 0;

measured at V_CLBL= 3 V

t_clamp1(max)

maximum duration of video

clamping pulse referenced to

end of horizontal sync

−

1.0

−

µs

t_{d(HSYNCl-CLBL)}

delay between leading edge of clamping pulse triggered

−

300

−

horizontal sync and start of

video clamping pulse

on leading edge of

horizontal sync;

control bit CLAMP = 1;

measured at V_CLBL= 3 V

t_clamp2(max)

maximum duration of video

clamping pulse referenced to

end of horizontal sync

−

0.15

2.1

V_blank(CLBL)

t_blank(CLBL)

top voltage level of vertical

blanking pulse

notes 1 and 2

1.7

1.9

width of vertical blanking pulse control bit VBLK = 0

220

305

−

260

350

300

395

−

µs

at pins CLBL and HUNLOCK

control bit VBLK = 1

µs

TC_blank

temperature coefﬁcient of

V_blank(CLBL)

mV/K

V_scan(CLBL)

TC_scan

output voltage during vertical

scan

I_CLBL= 0

0.59

0.63

0.67

temperature coefﬁcient of

V_scan(CLBL)

−

−2

−

mV/K

I_sink(CLBL)

I_L(CLBL)

internal sink current

external load current

2.4

−

−3.0

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Horizontal oscillator: pins HCAP and HREF

f_fr(H)

free-running frequency without R_HBUF= ∞;

30.53

31.45

32.39

kHz

PLL1 action (for testing only)

R_HREF= 2.4 kΩ;

C_HCAP= 10 nF; note 3

∆f_fr(H)

TC_fr

spread of free-running

frequency (excluding spread of

external components)

−

±3.0

temperature coefﬁcient of

free-running frequency

−100

+100

10⁻⁶/K

f_H(max)

V_HREF

maximum oscillator frequency

−

130

kHz

voltage at input for reference

current

2.43

2.55

2.68

Unlock blanking detection: pin HUNLOCK

V_{scan(HUNLOCK)}

low level voltage of HUNLOCK saturation voltage in case

of locked PLL1; internal

−

250

sink current = 1 mA

V_{blank(HUNLOCK)}

TC_blank

blanking level of HUNLOCK

external load current = 0

0.9

1.1

temperature coefﬁcient of

V_{blank(HUNLOCK)}

−

−0.9

−

mV/K

TC_sink

I_sink(int)

temperature coefﬁcient of

I_{sink(HUNLOCK)}

−

0.15

2.0

−

%/K

internal sink current

for blanking pulses;

PLL1 locked

1.4

2.6

I_L(max)

I_L

maximum external load current V_HUNLOCK= 1 V

leakage current V_HUNLOCK= 5 V in case of

−

−2

±5

µA

unlocked PLL1 and/or

protection active

PLL1 phase comparator and frequency-locked loop: pins HPLL1 and HBUF

t_{W(HSYNC)(max)}

maximum width of horizontal

sync pulse (referenced to line

period)

−

t_lock(HPLL1)

I_ctrl(HPLL1)

total lock-in time of PLL1

control currents

notes 4 and 5

locked mode, level 1

locked mode, level 2

−

µA

145

2.5

V_HBUF

buffered f/v voltage at HBUF

(pin 27)

minimum horizontal

frequency

maximum horizontal

frequency

−

0.5

−

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Phase adjustments and corrections via PLL1 and PLL2

HPOS

horizontal position (referenced register HPOS = 0

−

−13

−

to horizontal period)

−0.8

HPINBAL

horizontal pin unbalance

correction via HPLL2

(referenced to horizontal

period)

control bit HPC = 0; note 6

−

0.8

−

control bit HPC = 1; note 6

HPARAL

horizontal parallelogram

correction (referenced to

horizontal period)

control bit HBC = 0; note 6

−0.8

0.8

control bit HBC = 0; note 6

control bit HBC = 1; note 6

HMOIRE

relative modulation of

horizontal position by 0.5f_H;

phase alternates with 0.5f_V

control bit MOD = 0

0.05

HMOIRE_off

moire cancellation off

control bit MOD = 1

PLL2 phase detector: pins HFLB and HPLL2

φ_PLL2

PLL2 control (advance of

horizontal drive with respect to register HPINBAL = 07;

middle of horizontal ﬂyback)

maximum advance;

−

minimum advance;

−

I_ctrl(PLL2)

PLL2 control current

−

µA

Φ_PLL2

relative sensitivity of PLL2

phase shift related to horizontal

period

mV/%

V_{PROT(PLL2)(max)}

I_ch(PLL2)

maximum voltage for PLL2

protection mode/soft start

−

4.4

−

charge current for external

capacitor during soft start

V_HPLL2< 3.7 V

µA

HORIZONTAL FLYBACK INPUT: PIN HFLB

V_pos(HFLB)

V_neg(HFLB)

I_pos(HFLB)

I_neg(HFLB)

V_sl(HFLB)

positive clamping voltage

I_HFLB= 5 mA

−

5.5

−0.75

−

negative clamping voltage

positive clamping current

negative clamping current

slicing level

I_HFLB= −1 mA

−

−2

2.8

−

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Output stage for line driver pulses: pin HDRV

OPEN-COLLECTOR OUTPUT STAGE

V_sat(HDRV)

saturation voltage

I_HDRV= 20 mA

_HDRV= 60 mA

−

0.3

0.8

I_LO(HDRV)

output leakage current

V_HDRV= 16 V

µA

AUTOMATIC VARIATION OF DUTY CYCLE

t_HDRV(OFF)/t_H

relative t_OFFtime of HDRV

output; measured at

_HDRV= 3 V; HDRV duty cycle

is modulated by the relation

I_HREF/I_VREF

I_HDRV= 20 mA;

f_H= 31.45 kHz; see Fig.16

_HDRV= 20 mA;

45.5

48.5

51.5

f_H= 58 kHz; see Fig.16

I_HDRV= 20 mA;

f_H= 110 kHz; see Fig.16

X-ray protection: pins XRAY and XSEL

V_XRAY(sl)

slicing voltage level for latch

minimum width of trigger pulse

input resistance at pin 2

6.22

−

6.39

6.56

−

t_W(XRAY)(min)

R_i(XRAY)

−

µs

kΩ

−

V_XRAY< 6.38 V + V_BE

500

−

_XRAY> 6.38 V + V_BE

−

standby mode

−

XRAY_rst

reset of X-ray latch

pin 9 open-circuit or

connected to GND

set control bit SOFTST via

the I²C-bus

pin 9 connected to V_CCvia switch off V_CCthen re-apply

−

R_XSEL

V_CC

V_{CC(XRAY)(min)}

minimum supply voltage for

correct function of the X-ray

latch

pin 9 connected to V_CCvia

R_XSEL

−

V_{CC(XRAY)(max)}

R_XSEL

maximum supply voltage for

reset of the X-ray latch

pin 9 connected to V_CCvia

R_XSEL

no reset via I²C-bus

−

external resistor at pin 9

130

kΩ

Vertical oscillator [oscillator frequency in application without adjustment of free-running frequency f_fr(V)

]

f_fr(V)

free-running frequency

R_VREF= 22 kΩ;

C_VCAP= 100 nF

43.3

160

−

f_cr(V)

vertical frequency catching

range

constant amplitude; note 7 50

−

V_VREF

t_d(scan)

voltage at reference input for

vertical oscillator

−

3.0

delay between trigger pulse

and start of ramp at VCAP

(pin 24) (width of vertical

blanking pulse)

control bit VBLK = 0

control bit VBLK = 1

220

260

350

300

395

µs

305

I_VAGC

amplitude control current

control bit AGCDIS = 0

control bit AGCDIS = 1

±120

±200

±300

µA

−

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

C_VAGC

PARAMETER

CONDITIONS

MIN.

150

TYP.

MAX.

220

UNIT

external capacitor at VAGC

(pin 22)

−

Differential vertical current outputs

ADJUSTMENT OF VERTICAL SIZE INCLUDING VGA AND EHT COMPENSATION; see Fig.5

VSIZE

vertical size without VGA

overscan (referenced to

nominal vertical size)

bit VOVSCN = 0; note 8

−

bit VOVSCN = 0; note 8

−

100

−

VSIZE_VGA

vertical size with VGA overscan register VSIZE = 0;

(referenced to nominal vertical bit VOVSCN = 1; note 8

size)

−

115.9

116.8

117.7

bit VOVSCN = 1; note 8

VSMOD_EHT

EHT compensation on vertical I_VSMOD= 0

−

size via VSMOD (pin 21)

I_VSMOD= −120 µA

−7

(referenced to 100% vertical

size)

I_i(VSMOD)

input current (pin 21)

VSMOD = 0

−

µA

Ω

VSMOD = −7%

−

−120

−

R_i(VSMOD)

V_ref(VSMOD)

f_ro(VSMOD)

input resistance

300

−

500

−

reference voltage at input

roll-off frequency (−3 dB)

5.0

−

I_VSMOD= −60 µA

+ 15 µA (RMS)

−

MHz

ADJUSTMENT OF VERTICAL POSITION; see Fig.6

VPOS

vertical position (referenced to register VPOS = 0;

−

−11.5

11.5

−

100% vertical size)

control bit VPC = 0

control bit VPC = 1

ADJUSTMENT OF VERTICAL LINEARITY; see Fig.7

VLIN

vertical linearity (S-correction) register VLIN = 0;

control bit VSC = 0; note 8

−

control bit VSC = 0; note 8

−

control bit VSC = 1; note 8

−

δVLIN

symmetry error of S-correction maximum VLIN

−

±0.7

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

ADJUSTMENT OF VERTICAL LINEARITY BALANCE; see Fig.8

VLINBAL

vertical linearity balance

(referenced to 100% vertical

size)

control bit VLC = 0; note 8

−3.3

−2.5

−1.7

control bit VLC = 0; note 8

1.7

−

2.5

3.3

−

control bit VLC = 1; note 8

VMOIRE

modulation of vertical picture

position by ¹⁄₂vertical

frequency (related to 100%

vertical size)

control bit MOD = 0

−

control bit MOD = 0

−

0.08

−

moire cancellation off

control bit MOD = 1

−

Vertical output stage: pins VOUT1 and VOUT2; see Fig.29

∆I_{VOUT(nom)(p-p)}

nominal differential output

current (peak-to-peak value)

∆I_VOUT= I_VOUT1− I_VOUT2

nominal settings; note 8

;

0.76

0.54

0.85

0.6

0.94

0.66

I_o(VOUT)(max)

maximum output current at pins control bit VOVSCN = 1

VOUT1 and VOUT2

V_VOUT

allowed voltage at outputs

−

4.2

δI_{os(vert)(max)}

maximum offset error of vertical nominal settings; note 8

output currents

−

±2.5

δI_{lin(vert)(max)}

maximum linearity error of

vertical output currents

nominal settings; note 8

−

±1.5

EW drive output

EW DRIVE OUTPUT STAGE: PIN EWDRV; see Figs 9 to 12

V_const(EWDRV)

bottom output voltage at pin

EWDRV (internally stabilized)

1.05

1.2

1.35

V_{o(EWDRV)(max)}

I_L(EWDRV

maximum output voltage

load current

note 9

7.0

−

)

±2

600

10⁻⁶/K

TC_EWDRV

temperature coefﬁcient of

output signal

−

V_HPIN(EWDRV)

horizontal pincushion voltage

−

0.04

1.42

0.08

−

V_HCOR(EWDRV)

horizontal corner correction

voltage

control bit VSC = 0; note 8

−

−0.64

−

control bit VSC = 1; note 8

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V_HTRAP(EWDRV)

horizontal trapezium correction register HTRAP = 15;

−

−0.33

−

voltage

control bit VPC = 0; note 8

0.33

control bit VPC = 1; note 8

V_HSIZE(EWDRV)

horizontal size voltage

note 8

0.13

I_HSMOD= 0; note 8

−

3.6

−

V_HEHT(EWDRV)

EHT compensation on

horizontal size via HSMOD

(pin 31)

0.69

0.02

_HSMOD= −120 µA; note 8

I_i(HSMOD)

input current (pin 31)

V_HEHT= 0.02 V

V_HEHT= 0.69 V

−

µA

Ω

−120

−

R_i(HSMOD)

V_ref(HSMOD)

f_ro(HSMOD)

input resistance

300

−

500

−

reference voltage at input

roll-off frequency (−3 dB)

I_HSMOD= 0

5.0

−

I_HSMOD= −60 µA

+ 15 µA (RMS)

−

MHz

TRACKING OF EWDRV OUTPUT SIGNAL WITH HORIZONTAL FREQUENCY PROPORTIONAL VOLTAGE

f_H(MULTI)

horizontal frequency range for

tracking

−

kHz

V_PAR(EWDRV)

parabola amplitude at EWDRV I_HREF= 1.052 mA;

−

0.72

−

(pin 11)

f_H= 31.45 kHz;

control bit FHMULT = 1;

note 10

_HREF= 2.341 mA;

−

1.42

−

f_H= 70 kHz;

control bit FHMULT = 1;

note 10

function disabled;

control bit FHMULT = 0;

note 10

−

1.42

−

LE_EWDRV

linearity error of horizontal

frequency tracking

−

Output for asymmetric EW corrections: pin ASCOR

V_{HPARAL(ASCOR)}

vertical sawtooth voltage for

EW parallelogram correction

control bit HPC = 0; note 8

−

−0.825

0.825

0.05

−

control bit HPC = 0; note 8

control bit HPC = 1; note 8

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

−1.0

MAX.

UNIT

V_{HPINBAL(ASCOR)}vertical parabola voltage for pin register HPINBAL = 0;

−

unbalance correction

control bit HBC = 0; note 8

1.0

0.05

control bit HBC = 1; note 8

V_{o(ASCOR)(max)(p-p)}maximum output voltage swing

(peak-to-peak value)

V_{o(ASCOR)(max)}

V_c(ASCOR)

V_{o(ASCOR)(min)}

I_{o(ASCOR)(max)}

maximum output voltage

centre voltage

−

6.5

4.0

1.9

−1.5

−

minimum output voltage

maximum output current

_ASCOR≥ 1.9 V

µA

I_{o(sink)(ASCOR)(max)}maximum output sink current

Focus section: pin FOCUS; TDA4854 only

V_HFOCUS(p-p)

amplitude of horizontal

parabola (peak-to-peak value)

1.9 µs < t_fb< 5.5 µs

typical t_precor= 350 ns

−

0.06

3.2

350

−

t_precor

pre-correction of phase

µs

t_W(hfb)(min)

minimum horizontal ﬂyback

pulse width

1.9

t_W(hfb)(max)

maximum horizontal ﬂyback

pulse width

typical t_precor= 350 ns

typical t_d= 300 ns

−

5.5

12.5

−

µs

t_{W(hfb)(TV)(max)}

V_VFOCUS(p-p)

maximum horizontal ﬂyback

pulse width (TV)

−

amplitude of vertical parabola

(peak-to-peak value)

note 8

−

0.02

0.8

note 8

−

V_{o(FOCUS)(max)}

V_{o(FOCUS)(min)}

I_{o(FOCUS)(max)}

C_{L(FOCUS)(max)}

maximum output voltage

minimum output voltage

maximum output current

maximum capacitive load

I_FOCUS= 0

5.7

1.7

±1.5

−

6.3

2.3

−

B+ control section; see Figs 23 and 24

TRANSCONDUCTANCE AMPLIFIER: PINS BIN AND BOP

V_i(BIN)

input voltage pin 5

−

5.25

±1

I_i(BIN)(max)

V_ref(int)

maximum input current pin 5

−

µA

reference voltage at internal

non-inverting input of OTA

2.37

2.5

2.58

V_o(BOP)(min)

V_o(BOP)(max)

I_o(BOP)(max)

g_m(OTA)

minimum output voltage pin 3

−

0.5

5.6

−

maximum output voltage pin 3 I_BOP< 1 mA

maximum output current pin 3

5.0

−

5.3

±500

µA

transconductance of OTA

open-loop voltage gain

note 11

note 12

−

G_v(ol)

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

C_BOP(min)

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

minimum value of capacitor at

pin 3

−

VOLTAGE COMPARATOR: PIN BSENS

V_i(BSENS)

voltage range of positive

comparator input

−

V_i(BOP)

voltage range of negative

comparator input

I_{L(BSENS)(max)}

maximum leakage current

discharge disabled

−2

µA

OPEN-COLLECTOR OUTPUT STAGE: PIN BDRV

I_o(BDRV)(max)

I_LO(BDRV)

maximum output current

output leakage current

saturation voltage

−

µA

V_BDRV= 16 V

I_BDRV< 20 mA

V_sat(BDRV)

−

300

−

t_{off(BDRV)(min)}

t_d(BDRV-HDRV)

minimum off-time

−

250

500

delay between BDRV pulse

and HDRV pulse

measured at

V_HDRV= V_BDRV= 3 V

−

BSENS DISCHARGE CIRCUIT: PIN BSENS

V_STOP(BSENS)

discharge stop level

capacitive load;

0.85

1.0

1.15

_BSENS= 0.5 mA

I_dch(BSENS)

discharge current

V_BSENS> 2.5 V

fault condition

4.5

1.2

6.0

1.3

−

7.5

1.4

−

V_{th(BSENS)(restart)}

C_BSENS(min)

threshold voltage for restart

minimum value of capacitor at

BSENS (pin 4)

Internal reference, supply voltage, soft start and protection

V_CC(stab)

external supply voltage for

complete stabilization of all

internal references

9.2

−

I_CC

supply current

−

I_CC(stb)

standby supply current

STDBY = 1; V_PLL2< 1 V;

3.5 V < V_CC< 16 V

PSRR

power supply rejection ratio of f = 1 kHz

internal supply voltage

−

V_CC(blank)

supply voltage level for

activation of continuous

blanking

V_CCdecreasing from 12 V 8.2

8.6

9.0

V_{CC(blank)(min)}

minimum supply voltage level

for function of continuous

blanking

V_CCdecreasing from 12 V 2.5

3.5

8.3

4.0

8.7

V_on(VCC)

supply voltage level for

activation of HDRV, BDRV,

VOUT1, VOUT2 and

HUNLOCK

V_CCincreasing from below 7.9

typical 8 V

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

V_off(VCC)

PARAMETER

CONDITIONS

MIN.

7.7

TYP.

8.1

MAX.

8.5

UNIT

supply voltage level for

_CCdecreasing from

deactivation of BDRV, VOUT1, above typical 8.3 V

VOUT2 and HUNLOCK; also

sets register SOFTST

THRESHOLDS DERIVED FROM HPLL2 VOLTAGE

V_{HPLL2(blank)(ul)}

V_{HPLL2(bduty)(ul)}

V_{HPLL2(bduty)(ll)}

V_{HPLL2(hduty)(ul)}

V_{HPLL2(hduty)(ll)}

V_{HPLL2(stby)(ll)}

upper limit voltage for

continuous blanking

−

4.7

3.4

2.8

1.7

1.1

−

upper limit voltage for variation

of BDRV duty cycle

lower limit voltage for variation

of BDRV duty cycle

upper limit voltage for variation

of HDRV duty cycle

lower limit voltage for variation

of HDRV duty cycle

lower limit voltage for VOUT1

and VOUT2 to be active via

I²C-bus soft start

V_{HPLL2(stby)(ul)}

V_{HPLL2(stby)(ll)}

upper limit voltage for standby

voltage

−

lower limit voltage for VOUT1

and VOUT2 to be active via

external DC current

Notes

1. For duration of vertical blanking pulse see subheading ‘Vertical oscillator [oscillator frequency in application without

adjustment of free-running frequency f_fr(V)]’.

2. Continuous blanking at CLBL (pin 16) will be activated, if one of the following conditions is true:

a) No horizontal flyback pulses at HFLB (pin 1) within a line

b) X-ray protection is triggered

c) Voltage at HPLL2 (pin 30) is low during soft start

d) Supply voltage at V_CC(pin 10) is low

e) PLL1 unlocked while frequency-locked loop is in search mode.

3. Oscillator frequency is f_minwhen no sync input signal is present (continuous blanking at pins 16 and 17).

4. Loading of HPLL1 (pin 26) is not allowed.

5. Voltage at HPLL1 (pin 26) is fed to HBUF (pin 27) via a buffer. Disturbances caused by horizontal sync are removed

by an internal sample-and-hold circuit.

6. All vertical and EW adjustments in accordance with note 8, but VSIZE = 80% (register VSIZE = 63 and control

bit VOVSCN = 0).

7. Value of resistor at VREF (pin 23) may not be changed.

8. All vertical and EW adjustments are specified at nominal vertical settings; unless otherwise specified, which means:

a) VSIZE = 100% (register VSIZE = 127 and control bit VOVSCN = 0)

b) VSMOD = 0 (no EHT compensation)

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

c) VPOS centred (register VPOS = X and control

bit VPC = 1)

10. If f_Htracking is enabled, the amplitude of the complete

EWDRV output signal (horizontal pincushion + corner

correction + DC shift + trapezium) will be changed

proportional to I_HREF. The EWDRV low level of 1.2 V

remains fixed.

d) VLIN = 0 (register VLIN = X and control

bit VSC = 1)

e) VLINBAL = 0 (register VLINBAL = X and control

bit VLC = 1)

11. First pole of transconductance amplifier is 5 MHz

without external capacitor (will become the second

pole, if the OTA operates as an integrator).

f) FHMULT = 0

g) HPARAL = 0 (register HPARAL = X and control

bit HPC = 1)

V_BOP

12. Open-loop gain is

at f = 0 with no resistive load

-------------

V_BIN

and C_BOP= 10 nF [from BOP (pin 3) to GND].

h) HPINBAL = 0 (register HPINBAL = X and control

bit HBC = 1)

i) Vertical oscillator synchronized

j) HSIZE = 255.

9. The output signal at EWDRV (pin 11) may consist of

horizontal pincushion + corner correction + DC shift +

trapezium correction. If the control bit VOVSCN is set,

and the VPOS adjustment is set to an extreme value,

the tip of the parabola may be clipped at the upper limit

of the EWDRV output voltage range. The waveform of

corner correction will clip if the vertical sawtooth

adjustment exceeds 110% of the nominal setting.

Vertical and EW adjustments

MBG590

handbook, halfpage

MBG592

handbook, halfpage

VOUT1

VOUT2

(1)

∆l

(1) ∆I₁is the maximum amplitude setting at register VSIZE = 127,

control bit VOVSCN = 0, control bit VPC = 1,

control bit VSC = 1 and control bit VLC = 1.

∆I

VSIZE = ²× 100%

-------

(1) ∆I₁is the maximum amplitude setting at register VSIZE = 127

∆I₁

and control bit VPC = 1.

∆I

∆I₂– ∆I

VSMOD = ²× 100%

¹× 100%

-------

VPOS =

---------------------

∆I₁

2 × ∆I₁

Fig.5 Adjustment of vertical size.

Fig.6 Adjustment of vertical position.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

MGM068

handbook, halfpage

MBG594

handbook, halfpage

VOUT1

VOUT2

∆l /∆t

VOUT2

(1)

∆l

/∆t

(1)

∆I

(1) ∆I₁is the maximum amplitude setting at register VSIZE = 127

(1) ∆I₁is the maximum amplitude setting at register VSIZE = 127,

and control bit VLINBAL = 0.

and VLIN = 0%.

∆I₁– ∆I

VLIN =

²× 100%

---------------------

∆I₁

∆I₁– ∆I

VLINBAL =

²× 100%

---------------------

2 × ∆I₁

Fig.7 Adjustment of vertical linearity (vertical

S-correction).

Fig.8 Adjustment of vertical linearity balance.

MGM070

MGM069

handbook, halfpage

EWDRV

HCOR(EWDRV)

HPIN(EWDRV)

Fig.9 Adjustment of parabola amplitude at

pin EWDRV.

Fig.10 Influence of corner correction at

pin EWDRV.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

MGM072

MGM071

handbook, halfpage

EWDRV

HTRAP(EWDRV)

HSIZE(EWDRV)

HEHT(EWDRV)

Fig.12 Influence of HSIZE and EHT compensation

at pin EWDRV.

Fig.11 Influence of trapezium at pin EWDRV.

MGM073

handbook, halfpage

MGM074

ASCOR

c(ASCOR)

HPARAL(ASCOR)

HPINBAL(ASCOR)

Fig.13 Adjustment of parallelogram at pin ASCOR.

Fig.14 Adjustment of pin balance at pin ASCOR.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

Pulse diagrams

4.0 V

handbook, full pagewidth

automatic trigger level

3.8 V synchronized trigger level

vertical oscillator sawtooth

at VCAP (pin 24)

1.4 V

vertical sync pulse

inhibited

internal trigger

inhibit window

(typical 4 ms)

vertical blanking pulse

at CLBL (pin 16)

vertical blanking pulse

at HUNLOCK (pin 17)

VOUT1

differential output currents

VOUT1 (pin 13) and

VOUT2 (pin 12)

VOUT2

7.0 V maximum

EW drive waveform

at EWDRV (pin 11)

DC shift 3.6 V maximum

low-level 1.2 V fixed

MGM075

Fig.15 Pulse diagram for vertical part.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

handbook, full pagewidth

horizontal oscillator sawtooth

at HCAP (pin 29)

horizontal sync pulse

PLL1 control current

at HPLL1 (pin 26)

video clamping pulse

at CLBL (pin 16)

vertical blanking level

triggered on trailing edge

of horizontal sync

line flyback pulse

at HFLB (pin 1)

PLL2 control current

at HPLL2 (pin 30)

–

PLL2

control range

line drive pulse

at HDRV (pin 8)

45 to 52% of line period

horizontal focus parabola

at FOCUS (pin 32)

precor

MGM076

Fig.16 Pulse diagram for horizontal part.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

MGM077

handbook, full pagewidth

relative t

HDRV(OFF) H

(%)

15 30

110 130

(kHz)

Fig.17 Relative t_OFFtime of HDRV as a function of horizontal frequency.

composite sync (TTL)

handbook, full pagewidth

at HSYNC (pin 15)

internal integration of

composite sync

internal vertical

trigger pulse

PLL1 control voltage

at HPLL1 (pin 26)

clamping and blanking

pulses at CLBL (pin 16)

MGC947

a. Reduced influence of vertical sync on horizontal phase.

handbook, full pagewidth

composite sync (TTL)

at HSYNC (pin 15)

clamping and blanking

pulses at CLBL (pin 16)

MBG596

b. Generation of video clamping pulses during vertical sync with serration pulses.

Fig.18 Pulse diagrams for composite sync applications.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

I²C-BUS PROTOCOL

I²C-bus data format

S⁽¹⁾

SLAVE ADDRESS⁽²⁾

A⁽³⁾

SUBADDRESS⁽⁴⁾

A⁽³⁾

DATA⁽⁵⁾

A⁽³⁾

P⁽⁶⁾

Notes

1. S = START condition.

2. SLAVE ADDRESS (MAD) = 1000 1100.

3. A = acknowledge, generated by the slave. No acknowledge, if the supply voltage is below 8.3 V for start-up and 8.1 V

for shut-down procedure.

4. SUBADDRESS (SAD).

5. DATA, if more than 1 byte of DATA is transmitted, then no auto-increment of the significant subaddress is performed.

6. P = STOP condition.

It should be noted that clock pulses according to the 400 kHz specification are accepted for 3.3 and 5 V applications

(reference level = 1.8 V). Default register values after power-up are random. All registers have to be preset via software

before the soft start is enabled.

Important: If the register contents are changed during the vertical scan, this might result in a visible interference on the

screen. The cause for this interference is the abrupt change in picture geometry which takes effect at random locations

within the visible picture.

To avoid this kind of interference, the adjustment of the critical geometry parameters HSIZE, HPOS, VSIZE and VPOS

should be synchronized with the vertical flyback. This should be done in such a way that the adjustment change takes

effect during the vertical blanking time (see Fig.19).

For very slow I²C-bus interfaces, it might be necessary to delay the transmission of the last byte (or only the last bit) of

an I²C-bus message until the start of the vertical sync or vertical blanking.

handbook, full pagewivdethrtical

sync pulse

vertical

blanking pulse

SDA

parameter change takes effect

MGM088

Fig.19 Timing of the I²C-bus transmission for interference-free adjustment.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

Table 4 List of I²C-bus controlled switches; notes 1 and 2

CONTROL

FUNCTION

BIT

SAD

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

BLKDIS

0: vertical, protection and horizontal unlock blanking

available on pins CLBL and HUNLOCK

1: only vertical and protection blanking available on

pins CLBL and HUNLOCK

HBC

0: HPINBAL (parabola) waveform enabled

1: HPINBAL (parabola) waveform disabled

0: HPARAL (sawtooth) waveform enabled

1: HPARAL (sawtooth) waveform disabled

0: AGC in vertical oscillator active

D1 #

HPC

D2 #

AGCDIS

VSC

D3 #

1: AGC in vertical oscillator inhibited

0: VLIN and HCOR adjustments enabled

1: VLIN and HCOR adjustments forced to centre value

0: horizontal and vertical moire cancellation enabled

1: horizontal and vertical moire cancellation disabled

0: TV mode at f_minnot activated

D4 #

MOD

D5 #

TVMOD

FHMULT

VOVSCN

CLAMP

VBLK

D6 #

1: TV mode at f_minactivated

0: EW output independent of horizontal frequency

1: EW output tracks with horizontal frequency

0: vertical size 100%

D2 X

1: vertical size 116.8% for VGA350

0: trailing edge for horizontal clamp

D3 #

1: leading edge for horizontal clamp

0: vertical blanking = 260 µs

D4 #

1: vertical blanking = 340 µs

VLC

0: VLINBAL adjustment enabled

D5 #

1: VLINBAL adjustment forced to centre value

0: VPOS and HTRAP adjustments enabled

1: VPOS and HTRAP adjustments forced to centre value

0: ASCOR disconnected from PLL2

1: ASCOR internally connected with PLL2

0: internal power supply enabled

VPC

D6 #

ACD

D7 #

STDBY⁽³⁾

1: internal power supply disabled

SOFTST⁽³⁾0: soft start not released (pin HPLL2 pulled to ground)

D1 #

1: soft start is released (power-up via pin HPLL2)

Notes

1. X = don’t care.

2. # = this bit is occupied by another function. If the register is addressed, the bit values for both functions must be

transferred.

3. Bits STDBY and SOFTST can be reset by internal protection circuit.

1999 Jul 13

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Table 5 List of I²C-bus controlled functions and those accessible by pins; notes 1 and 2

SAD

(HEX)

CONTROL

BIT

FUNCTION

TRACKS WITH

FUNCTION

NAME

BITS

RANGE

D7 D6 D5 D4 D3 D2 D1 D0

Horizontal size

Vertical position

HSIZE

VPOS

D7 D6 D5 D4 D3 D2 D1 D0

−

0.1 to 3.6 V

HSMOD

VSMOD

D7 D6 D5 D4 D3 D2 D1

VPC

VLC

±11.5%

Vertical linearity

balance

VLINBAL

D6 D5 D4 D3

±2.5% of 100%

vertical size

VSIZE, VOVSCN,

VPOS and

VSMOD

Moire cancellation

via vertical

position

VMOIRE

HPIN

D2 D1 D0

MOD

−

0 to 0.08% of

vertical amplitude

−

Horizontal

pincushion

D5 D4 D3 D2 D1 D0

0 to 1.44 V

VSIZE, VOVSCN,

VPOS, HSIZE and

HSMOD

Moire cancellation

via horizontal

position

HMOIRE

D4 D3 D2 D1 D0

MOD

0 to 0.05% of

horizontal period

−

Horizontal

position

HPOS

VLIN

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4

−

±13% of horizontal

period

−

Vertical linearity

VSC

−2 to −46%

VSIZE, VOVSCN,

VPOS and

VSMOD

EW pin balance

Vertical size

HPINBAL

D3 D2 D1 D0 HBC and ±1% of

VSIZE, VOVSCN

and VPOS

ACD

horizontal period

VSIZE

HCOR

D7 D6 D5 D4 D3 D2 D1

−

60 to 100%

VSMOD

Horizontal corner

correction

D4 D3 D2 D1 D0

VSC

+6 to −46% of

parabola

VSIZE, VOVSCN,

VPOS, HSIZE and

HSMOD

amplitude

Horizontal

trapezium

correction

HTRAP

D7 D6 D5 D4

VPC

±0.33 V

VSIZE, VOVSCN,

VPOS, HSIZE and

HSMOD

Horizontal

parallelogram

HPARAL

D3 D2 D1 D0 HPC and ±1% of horizontal VSIZE, VOVSCN

ACD period and VPOS

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SAD

(HEX)

CONTROL

BIT

FUNCTION

TRACKS WITH

FUNCTION

TDA4854

NAME

BITS

RANGE

D7 D6 D5 D4 D3 D2 D1 D0

Vertical focus

VFOCUS

HFOCUS

D7 D6 D5

−

0 to 25%

0 to 100%

VSIZE, VOVSCN

and VPOS

Horizontal focus

D4 D3 D2 D1 D0

−

Notes

1. X = don’t care.

2. # = this bit is occupied by another function. If the register is addressed, the bit values for both functions must be transferred.

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

Start-up procedure

V_CC< 8.3 V:

START

• As long as the supply voltage is too low for correct

operation, the IC will give no acknowledge due to

internal Power-on reset (POR)

Power-down mode (XXXX XXXX)

no acknowledge is given by IC

all register contents are random

• Supply current is 9 mA or less.

V_CC> 8.3 V:

> 8.3 V

• The internal POR has ended and the IC is in standby

Standby mode (XXXX XX01)

mode

STDBY = 1

SOFTST = 0

all other register contents are random

• Control bits STDBY and SOFTST are reset to their start

values

• All other register contents are random

• Pin HUNLOCK is at HIGH-level.

Setting control bit STDBY = 0:

8CH

0DH

00H

A P

Protection mode (XXXX XX00)

• Enables internal power supply

STDBY = 0

SOFTST = 0

all other register contents are random

• Supply current increases from 9 to 70 mA

• When V_CC< 8.6 V register SOFTST cannot be set by

the I²C-bus

8CH

SAD

DATA A P

• Output stages are disabled, except the vertical output

• Pin HUNLOCK is at HIGH-level.

Protection mode (XXXX XX00)

Setting all registers to defined values:

STDBY = 0

SOFTST = 0

registers are pre-set

• Due to the hardware configuration of the IC

(no auto-increment) any register setting needs a

complete 3-byte I²C-bus data transfer as follows:

START - IC address - subaddress - data - STOP.

all registers defined?

Setting control bit SOFTST = 1:

yes

• Before starting the soft-start sequence a delay of

minimum 80 ms is necessary to obtain correct function

of the horizontal drive

8CH

0DH

02H

A P

Soft-start sequence (XXXX XX10)

• HDRV duty cycle increases

• BDRV duty cycle increases

• PLL1 and PLL2 are enabled.

STDBY = 0

SOFTST = 1

Operating mode (XXXX XX10)

IC in full operation:

STDBY = 0

SOFTST = 1

• Pin HUNLOCK is at LOW-level when PLL1 is locked

• Any change of the register content will result in

immediate change of the output behaviour

change/refresh of data?

yes

SOFTST = 0?

yes

• Setting control bit SOFTST = 0 is the only way (except

power-down via pin V_CC) to leave the operating mode.

(1)

8CH

SAD

DATA A P

Soft-down sequence:

MGM078

• See L4 of Fig.21 for starting the soft-down sequence.

(1) See Fig.21.

Fig.20 I²C-bus flow for start-up.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

Protection and standby mode

Soft-down sequence:

• Start the sequence by setting control bit SOFTST = 0

• BDRV duty cycle decreases

8CH

0DH

00H

A P

• HDRV duty cycle decreases.

Protection mode:

Soft-down sequence (XXXX XX00)

STDBY = 0

SOFTST = 0

• Pins HDRV and BDRV are floating

• Continuous blanking at pin CLBL is active

• Pin HUNLOCK is floating

Protection mode (XXXX XX00)

• PLL1 and PLL2 are disabled

STDBY = 0

SOFTST = 0

registers are set

• Register contents are kept in internal memory.

Protection mode can be left by 3 ways:

1. Entering standby mode by setting control

bit SOFTST = 0 and control bit STDBY = 1

STDBY = 1?

yes

SOFTST = 1?

yes

2. Starting the soft-start sequence by setting control

bit SOFTST = 1 (bit STDBY = don’t care);

see L3 of Fig.20 for continuation

(1)

3. Decreasing the supply voltage below 8.1 V.

8CH

0DH

01H

A P

Standby mode:

• Set control bit STDBY = 1

Standby mode (XXXX XX01)

• Driver outputs are floating (same as protection mode)

STDBY = 1

SOFTST = 0

• Supply current is 9 mA

all other register contents are random

• Only the I²C-bus and protection circuits are operative

• Contents of all registers except the value of bit STDBY

and bit SOFTST are lost

(1)

MBK382

• See L2 of Fig.20 for continuation.

(1) See Fig.20.

Fig.21 I²C-bus flow for protection and standby

mode.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

handbook, full pagewidth

(ANY Mode)

< 8.1 V

Power-Down Mode

a soft-down sequency followed by a

soft start sequence is generated

internally.

no acknowledge is given by IC

all register contents are random

8.6 V

8.1 V

IC enters standby mode.

8.6 V

8.1 V

(1)

MGM079

(1) See Fig.20.

Fig.22 I²C-bus flow for any mode.

Power-down mode

Power dip of V_CC< 8.6 V:

• The soft-down sequence is started first.

• Then the soft-start sequence is generated internally.

Power dip of V_CC< 8.1 V or V_CCshut-down:

• This function is independent from the operating mode, so it works under any condition.

• All driver outputs are immediately disabled

• IC enters standby mode.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

APPLICATION INFORMATION

handbook, full pagewidth

(1)

HDRV

HPLL2

BDRV

SOFT START

OTA

2.5 V

TR1

INVERTING

BUFFER

HORIZONTAL

OUTPUT

STAGE

DISCHARGE

horizontal

flyback pulse

BIN

BOP

BSENS

MGM080

BOP

>10 nF

EWDRV

For f < 50 kHz and C2 < 47 nF calculation formulas and behaviour of the OTA are the same as for an OP. An exception is the limited output current at

BOP (pin 3). See Chapter “Characteristics”, Row Head “B+ control section; see Figs 23 and 24”.

(1) The recommended value for R6 is 1 kΩ.

a. Feedback mode application.

handbook, full pagewidth

horizontal

flyback pulse

HDRV

BDRV

d(BDRV)

off(min)

= V

BSENS

BOP

RESTART(BSENS)

BSENS

STOP(BSENS)

MBG600

b. Waveforms for normal operation.

c. Waveforms for fault condition.

Fig.23 Application and timing for feedback mode.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

horizontal

flyback pulse

(1)

HDRV

HPLL2

INVERTING

BUFFER

SOFT START

OTA

HORIZONTAL

OUTPUT

STAGE

2.5 V

EHT

transformer

BDRV

5 I

DISCHARGE

MOSFET

TR1

EHT adjustment

BOP

BIN

MGM081

BSENS

TR2

BSENS

>2 nF

power-down

> 10 nF

BOP

(1) The recommended value for R4 is 1 kΩ.

a. Forward mode application.

handbook, full pagewidth

horizontal

flyback pulse

HDRV

BDRV

(discharge time of C

BSENS

)

off

d(BDRV)

BOP

BSENS

RESTART(BSENS)

STOP(BSENS)

MOSFET

MBG602

b. Waveforms for normal operation.

c. Waveforms for fault condition.

Fig.24 Application and timing for feed forward mode.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

Start-up sequence and shut-down sequence

handbook, full pagewidth

MGM082

8.6 V continuous blanking off

PLL2 soft start/soft-down enabled

(1)

8.3 V data accepted from I C-bus

video clamping pulse enabled if control bit STDBY = 0

3.5 V

continuous blanking (pin 16 and 17) activated

time

a. Start-up sequence.

MGM083

handbook, full pagewidth

8.6 V continuous blanking (pin 16 and 17) activated

(2)

PLL2 soft-down sequence is triggered

8.1 V no data accepted from I C-bus

video clamping pulse disabled

3.5 V continuous blanking disappears

time

b. Shut-down sequence.

(1) See Figs 20, 21, 22, 26 and 27.

(2) See Figs 26b and 27b.

Fig.25 Start-up sequence and shut-down sequence.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

PLL2 soft start sequence and PLL2 soft-down sequence

MGM084

handbook, full pagewidth

HPLL2

4.7 V continuous blanking off

PLL2 enabled

frequency detector enabled

HDRV/HFLB protection enabled

3.4 V BDRV duty cycle has reached nominal value

2.8 V BDRV duty cycle begins to increase

HDRV duty cycle has reached nominal value

duty cycle increases

1.7 V

HDRV duty cycle begins to increase

1 V

VOUT1 and VOUT2 enabled

time

a. PLL2 soft start sequence, via the I²C-bus, if V_CC> 8.6 V.

MGM085

handbook, full pagewidth

HPLL2

4.7 V continuous blanking (pin 16 and 17) activated

PLL2 disabled

frequency detector disabled

HDRV/HFLB protection disabled

(1)

3.4 V BDRV duty cycle begins to decrease

2.8 V BDRV floating

(1)

HDRV duty cycle begins to decrease

1.7 V HDRV floating

1 V

VOUT1 and VOUT2 floating

time

b. PLL2 soft-down sequence, via the I²C-bus, if V_CC> 8.6 V.

(1) HDRV, BDRV, VOUT2 and VOUT1 are floating for V_CC< 8.6 V.

Fig.26 PLL2 soft start sequence and PLL2 soft-down sequence via the I²C-bus.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

MHB108

handbook, full pagewidth

HPLL2

4.6 V continuous blanking off

PLL2 enabled

frequency detector enabled

HDRV/HFLB protection enabled

3.3 V BDRV duty cycle has reached nominal value

3.0 V BDRV duty cycle begins to increase

HDRV duty cycle has reached nominal value

1.7 V

HDRV duty cycle begins to increase

time

a. PLL2 soft start sequence by external DC current, if V_CC> 8.6 V.

MHB109

handbook, full pagewidth

HPLL2

4.6 V continuous blanking (pin 16 and 17) activated

PLL2 disabled

frequency detector disabled

HDRV/HFLB protection disabled

(1)

3.3 V BDRV duty cycle begins to decrease

3.0 V BDRV floating

(1)

HDRV duty cycle begins to decrease

1.7 V HDRV floating

time

b. PLL2 soft-down sequence by external DC current, if V_CC> 8.6 V.

(1) HDRV, BDRV, VOUT2 and VOUT1 are floating for V_CC< 8.6 V.

Fig.27 PLL2 soft start sequence and PLL2 soft-down sequence by external DC current.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

X-ray latch triggered

handbook, full pagewidth

XRAY

HUNLOCK

BDRV duty cycle

HDRV duty cycle

VOUT1, VOUT2

floating

approximately 25 ms

MGM087

Fig.28 Activation of the soft-down sequence via pin XRAY.

Vertical linearity error

(1)

handbook, halfpage

VOUT

MBG551

(µA)

+415

(2)

(3)

(4)

−415

VCAP

(1) I_VOUT= I_VOUT1− I_VOUT2

(2) I₁= I_VOUTat V_VCAP= 1.9 V.

(3) I₂= I_VOUTat V_VCAP= 2.6 V.

(4) I₃= I_VOUTat V_VCAP= 3.3 V.

₁– I₃

Which means: I₀

--------------

₁– I₂

I₂– I₃

Vertical linearity error = 1 – max

--------------

I₀

--------------

I₀

Fig.29 Definition of vertical linearity error.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

Printed-circuit board layout

further connections to other components

or ground paths are not allowed

handbook, full pagewidth

external components of

horizontal section

external components of

vertical section

pin 25 should be the 'star point'

for all small signal components

external components of

horizontal section

no external ground tracks

connected here

47 nF

2.2 nF

TDA4853; TDA4854

470 pF

100 µF

12 V

B-drive line in parallel

to ground

only this path may be connected

to general ground of PCB

MGM086

SMD

For optimum performance of the TDA4853; TDA4854 the ground paths must be routed as shown.

Only one connection to other grounds on the PCB is allowed.

Note: The tracks for HDRV and BDRV should be kept separate.

Fig.30 Hints for printed-circuit board (PCB) layout.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

INTERNAL PIN CONFIGURATION

SYMBOL

HFLB

INTERNAL CIRCUIT

1.5 kΩ

7 x

MBG561

XRAY

5 kΩ

6.25 V

MBG562

BOP

5.3 V

MBG563

BSENS

MBG564

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

BIN

INTERNAL CIRCUIT

MBG565

BDRV

MBG566

PGND

HDRV

power ground, connected to substrate

MGM089

XSEL

4 kΩ

MBK381

V_CC

MGM090

EWDRV

108 Ω

MBG570

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

VOUT2

INTERNAL CIRCUIT

MBG571

VOUT1

MBG572

VSYNC

100 Ω

2 kΩ

1.4 V

7.3 V

MBG573

HSYNC

1.28 V

85 Ω

7.3 V

1.4 V

MBG574

CLBL

MBG575

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

INTERNAL CIRCUIT

HUNLOCK

MGM091

SCL

MGM092

SDA

MGM093

ASCOR

480 Ω

MGM094

VSMOD

250 Ω

5 V

MGM095

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

VAGC

INTERNAL CIRCUIT

MBG581

VREF

3 V

MBG582

VCAP

MBG583

SGND

HPLL1

signal ground

4.3 V

MGM096

HBUF

5 V

MGM097

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

HREF

INTERNAL CIRCUIT

HCAP

2.525 V

76 Ω

7.7 V

MBG585

HPLL2

7.7 V

6.25 V

HFLB

MGM098

HSMOD

250 Ω

5 V

MGM099

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SYMBOL

INTERNAL CIRCUIT

FOCUS⁽¹⁾

120 Ω

200 Ω

120 Ω

MGM100

Note

1. This pin is internally connected for TDA4853.

Electrostatic discharge (ESD) protection

7.3 V

MBG559

7.3 V

MBG560

Fig.31 ESD protection for pins 4, 11 to 13,

16 and 17.

Fig.32 ESD protection for pins 2, 3, 5, 18 to 24

and 26 to 32.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

PACKAGE OUTLINE

SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)

SOT232-1

(e )

w M

pin 1 index

10 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

max.

(1)

UNIT

min.

max.

1.3

0.8

0.53

0.40

0.32

0.23

29.4

28.5

9.1

8.7

3.2

2.8

10.7

10.2

12.2

10.5

4.7

0.51

3.8

1.778

10.16

0.18

1.6

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

92-11-17

95-02-04

SOT232-1

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

SOLDERING

The total contact time of successive solder waves must not

exceed 5 seconds.

Introduction to soldering through-hole mount

packages

The device may be mounted up to the seating plane, but

the temperature of the plastic body must not exceed the

specified maximum storage temperature (T_stg(max)). If the

printed-circuit board has been pre-heated, forced cooling

may be necessary immediately after soldering to keep the

temperature within the permissible limit.

This text gives a brief insight to wave, dip and manual

soldering. A more in-depth account of soldering ICs can be

found in our “Data Handbook IC26; Integrated Circuit

Packages” (document order number 9398 652 90011).

Wave soldering is the preferred method for mounting of

through-hole mount IC packages on a printed-circuit

board.

Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the

package, either below the seating plane or not more than

2 mm above it. If the temperature of the soldering iron bit

is less than 300 °C it may remain in contact for up to

10 seconds. If the bit temperature is between

Soldering by dipping or by solder wave

The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact

with the joints for more than 5 seconds.

300 and 400 °C, contact may be up to 5 seconds.

Suitability of through-hole mount IC packages for dipping and wave soldering methods

SOLDERING METHOD

PACKAGE

DIPPING

WAVE

DBS, DIP, HDIP, SDIP, SIL

suitable

suitable⁽¹⁾

Note

1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

NOTES

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

NOTES

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I²C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

NOTES

1999 Jul 13

Philips Semiconductors – a worldwide company

Argentina: see South America

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399

Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. +61 2 9704 8141, Fax. +61 2 9704 8139

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. +64 9 849 4160, Fax. +64 9 849 7811

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210

Norway: Box 1, Manglerud 0612, OSLO,

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Pakistan: see Singapore

Belgium: see The Netherlands

Brazil: see South America

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 68 9211, Fax. +359 2 68 9102

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381, Fax. +1 800 943 0087

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Colombia: see South America

Czech Republic: see Austria

Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. +45 33 29 3333, Fax. +45 33 29 3905

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,

Tel. +27 11 471 5401, Fax. +27 11 471 5398

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. +358 9 615 800, Fax. +358 9 6158 0920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. +33 1 4099 6161, Fax. +33 1 4099 6427

South America: Al. Vicente Pinzon, 173, 6th floor,

04547-130 SÃO PAULO, SP, Brazil,

Tel. +55 11 821 2333, Fax. +55 11 821 2382

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. +49 40 2353 60, Fax. +49 40 2353 6300

Spain: Balmes 22, 08007 BARCELONA,

Tel. +34 93 301 6312, Fax. +34 93 301 4107

Hungary: see Austria

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,

Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,

Tel. +91 22 493 8541, Fax. +91 22 493 0966

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2741 Fax. +41 1 488 3263

Indonesia: PT Philips Development Corporation, Semiconductors Division,

Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,

Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. +66 2 745 4090, Fax. +66 2 398 0793

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,

ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),

Tel. +39 039 203 6838, Fax +39 039 203 6800

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +1 800 234 7381, Fax. +1 800 943 0087

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Uruguay: see South America

Vietnam: see Singapore

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Middle East: see Italy

Tel. +381 11 62 5344, Fax.+381 11 63 5777

For all other countries apply to: Philips Semiconductors,

Internet: http://www.semiconductors.philips.com

International Marketing & Sales Communications, Building BE-p, P.O. Box 218,

5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

SCA67

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

545004/02/pp60

Date of release: 1999 Jul 13

Document order number: 9397 750 05275

Philips Semiconductors: Product information on TDA4853; TDA4854, I²C-bus autosync deflection controllers for PC/TV monitors

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