74VHC125PW [NXP]
IC AHC/VHC/H/U/V SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14, Bus Driver/Transceiver;
| 型号： | 74VHC125PW |
| 厂家： | 
NXP |
| 描述： | IC AHC/VHC/H/U/V SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14, Bus Driver/Transceiver 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总15页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74VHC125; 74VHCT125
Quad buffer/line driver; 3-state
Rev. 02 — 13 October 2009
Product data sheet
1. General description
The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard JESD7-A.
The 74VHC125; 74VHCT125 provides four non-inverting buffer/line drivers with 3-state
outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH
at nOE causes the outputs to assume a high-impedance OFF-state.
The 74VHC125; 74VHCT125 are identical to the 74VHC126; 74VHCT126 but have active
LOW enable inputs.
2. Features
I Balanced propagation delays
I All inputs have a Schmitt-trigger action
I Inputs accepts voltages higher than VCC
I Input levels:
N The 74VHC125 operates with CMOS logic levels
N The 74VHCT125 operates with TTL logic levels
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74VHC125D
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74VHCT125D
74VHC125PW
74VHCT125PW
74VHC125BQ
74VHCT125BQ
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
SOT762-1
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
74VHC125; 74VHCT125
NXP Semiconductors
Quad buffer/line driver; 3-state
4. Functional diagram
1A
1Y
2Y
3Y
4Y
3
6
2
2
1
1OE
2A
1
5
3
6
8
1
5
EN1
2OE
3A
4
9
4
9
8
3OE
4A
10
12
10
12
13
nY
nA
11
11
4OE
13
nOE
mna229
mna227
mna228
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one buffer)
5. Pinning information
5.1 Pinning
74VHC125
74VHCT125
terminal 1
index area
74VHC125
74VHCT125
2
3
4
5
6
13
12
11
10
9
1A
4OE
4A
1
2
3
4
5
6
7
14
1Y
2OE
2A
1OE
1A
V
CC
13
12
11
10
9
4OE
4A
4Y
1Y
3OE
3A
(1)
GND
2OE
2A
4Y
2Y
3OE
3A
2Y
001aak045
GND
8
3Y
Transparent top view
001aak044
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
74VHC_VHCT125_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 October 2009
2 of 15
74VHC125; 74VHCT125
NXP Semiconductors
Quad buffer/line driver; 3-state
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1OE, 2OE, 3OE, 4OE
1A, 2A, 3A, 4A
1Y, 2Y, 3Y, 4Y
GND
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
7
output enable input (active LOW)
data input
data output
ground (0 V)
VCC
14
supply voltage
6. Functional description
Table 3.
Control
nOE
Function table[1]
Input
nA
L
Output
nY
L
L
H
H
Z
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−20
-
Max
+7.0
+7.0
-
Unit
V
supply voltage
input voltage
V
[1]
[1]
IIK
input clamping current
output clamping current
output current
VI < −0.5 V
mA
mA
mA
mA
mA
°C
IOK
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
±20
±25
75
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−75
−65
-
storage temperature
total power dissipation
SO14 package
+150
Tamb = −40 °C to +125 °C
[2]
[3]
[4]
-
-
-
500
500
500
mW
mW
mW
TSSOP14 package
DHVQFN14 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70 °C.
[3] Ptot derates linearly with 5.5 mW/K above 60 °C.
[4] Ptot derates linearly with 4.5 mW/K above 60 °C.
74VHC_VHCT125_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 October 2009
3 of 15
74VHC125; 74VHCT125
NXP Semiconductors
Quad buffer/line driver; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74VHC125
74VHCT125
Unit
Min
2.0
0
Typ
Max
5.5
Min
4.5
0
Typ
Max
5.5
5.5
VCC
+125
-
VCC
VI
supply voltage
input voltage
5.0
5.0
V
-
5.5
-
V
VO
output voltage
ambient temperature
0
-
VCC
+125
100
20
0
-
V
Tamb
∆t/∆V
−40
-
+25
−40
-
+25
°C
ns/V
ns/V
input transition rise
and fall rate
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
-
-
-
-
-
-
20
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
Min Typ Max
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Max
Min
Max
For type 74VHC125
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 3.0 V
2.1
2.1
2.1
VCC = 5.5 V
3.85
-
3.85
-
3.85
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
VCC = 3.0 V
VCC = 5.5 V
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −50 µA; VCC = 2.0 V
IO = −50 µA; VCC = 3.0 V
IO = −50 µA; VCC = 4.5 V
IO = −4.0 mA; VCC = 3.0 V
IO = −8.0 mA; VCC = 4.5 V
VI = VIH or VIL
1.9
2.9
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
4.4
4.4
4.4
2.58
3.94
2.48
3.8
2.40
3.70
-
VOL
LOW-level
output voltage
IO = 50 µA; VCC = 2.0 V
IO = 50 µA; VCC = 3.0 V
IO = 50 µA; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
VI = VIH or VIL;
-
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
V
V
0.1
0.1
0.1
V
0.36
0.36
±0.25
0.44
0.44
±2.5
0.55
0.55
±10.0
V
-
V
IOZ
OFF-state
-
µA
output current VO = VCC or GND;
CC = 5.5 V
V
II
input leakage VI = 5.5 V or GND;
current CC = 0 V to 5.5 V
-
-
-
-
0.1
2.0
-
-
1.0
20
-
-
2.0
40
µA
µA
V
ICC
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
V
74VHC_VHCT125_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 October 2009
4 of 15
74VHC125; 74VHCT125
NXP Semiconductors
Quad buffer/line driver; 3-state
Table 6.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
Min Typ Max
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Max
Min
Max
CI
input
capacitance
-
3.0
10
-
10
-
10
pF
pF
CO
output
-
4.0
-
-
-
-
-
capacitance
For type 74VHCT125
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −50 µA
4.4
4.5
-
-
-
4.4
3.8
-
-
4.4
-
-
V
V
IO = −8.0 mA
3.94
3.70
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 µA
-
-
-
0
-
0.1
0.36
±0.25
-
-
-
0.1
-
-
-
0.1
0.55
±10.0
V
IO = 8.0 mA
0.44
±2.5
V
IOZ
OFF-state
per input pin; VI = VIH or VIL;
-
µA
output current VCC = 5.5 V; IO = 0 A
VO = VCC or GND;
other pins at VCC or GND
II
input leakage VI = 5.5 V or GND;
-
-
-
-
-
-
0.1
2.0
-
-
-
1.0
20
-
-
-
2.0
40
µA
µA
mA
current
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
per input pin;
VCC = 0 V to 5.5 V
ICC
∆ICC
V
additional
1.35
1.5
1.5
supply current VI = VCC − 2.1 V; IO = 0 A;
other pins at VCC or GND;
V
CC = 4.5 V to 5.5 V
CI
input
capacitance
-
-
3.0
4.0
10
-
-
-
10
-
-
-
10
-
pF
pF
CO
output
capacitance
74VHC_VHCT125_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 October 2009
5 of 15
74VHC125; 74VHCT125
NXP Semiconductors
Quad buffer/line driver; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see Figure 8.
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max Min
Max
Min
Max
For type 74VHC125
[2]
[2]
[2]
[3]
tpd
propagation nA to nY; see Figure 6
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
CL = 50 pF
-
-
4.4
8.0
1.0
1.0
9.5
1.0
1.0
11.5
14.5
ns
ns
6.2 11.5
13.0
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.0
4.3
5.5
7.5
1.0
1.0
6.5
8.5
1.0
1.0
7.0
9.5
ns
ns
CL = 50 pF
ten
enable time nOE to nY; see Figure 7
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
4.7
8.0
1.0
1.0
9.5
1.0
1.0
11.5
14.5
ns
ns
CL = 50 pF
6.8 11.5
13.0
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.3
4.7
5.1
7.1
1.0
1.0
6.0
8.0
1.0
1.0
6.5
9.0
ns
ns
CL = 50 pF
tdis
disable time nOE to nY; see Figure 7
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
6.7
9.7
1.0
1.0
11.5
15.0
1.0
1.0
12.5
16.5
ns
ns
CL = 50 pF
9.6 13.2
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
-
4.8
6.8
10
6.8
8.8
-
1.0
1.0
-
8.0
10.0
-
1.0
1.0
-
8.5
11.0
-
ns
ns
pF
CL = 50 pF
CPD
power
dissipation
capacitance
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
74VHC_VHCT125_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 October 2009
6 of 15
74VHC125; 74VHCT125
NXP Semiconductors
Quad buffer/line driver; 3-state
Table 7.
Dynamic characteristics …continued
GND = 0 V; For test circuit see Figure 8.
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max Min
Max
Min
Max
For type 74VHCT125
[2]
tpd
propagation nA to nY; see Figure 6
delay
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
-
-
3.0
4.3
5.5
7.5
1.0
1.0
6.5
8.5
1.0
1.0
7.0
9.5
ns
ns
ten
enable time nOE to nY; see Figure 7
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.4
4.9
5.1
7.3
1.0
1.0
6.0
8.3
1.0
1.0
6.5
9.5
ns
ns
CL = 50 pF
[2]
[3]
tdis
disable time nOE to nY; see Figure 7
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
-
4.5
6.5
12
6.8
8.8
-
1.0
1.0
-
8.0
10.0
-
1.0
1.0
-
8.5
11.0
-
ns
ns
pF
CL = 50 pF
CPD
power
dissipation
capacitance
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL
ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
.
.
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
11. Waveforms
V
I
V
nA input
M
GND
t
t
PHL
PLH
V
OH
V
nY output
M
V
OL
mna230
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Propagation delay input (nA) to output (nY)
74VHC_VHCT125_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 October 2009
7 of 15
74VHC125; 74VHCT125
NXP Semiconductors
Quad buffer/line driver; 3-state
V
I
nOE input
GND
V
M
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna362
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Enable and disable times
Table 8.
Type
Measurement points
Input
VM
Output
VM
VX
VY
74VHC125
0.5VCC
0.5VCC
0.5VCC
VOL + 0.3 V
VOL + 0.3 V
V
V
OL − 0.3 V
74VHCT125
1.5 V
OL − 0.3 V
74VHC_VHCT125_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 October 2009
8 of 15
74VHC125; 74VHCT125
NXP Semiconductors
Quad buffer/line driver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 8. Load circuit for switching times
Table 9.
Type
Test data
Input
Load
S1 position
tPHL, tPLH
open
VI
tr, tf
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74VHC125
VCC
3.0 V
≤ 3.0 ns
≤ 3.0 ns
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74VHCT125
open
GND
VCC
74VHC_VHCT125_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 October 2009
9 of 15
74VHC125; 74VHCT125
NXP Semiconductors
Quad buffer/line driver; 3-state
12. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 9. Package outline SOT108-1 (SO14)
74VHC_VHCT125_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 October 2009
10 of 15
74VHC125; 74VHCT125
NXP Semiconductors
Quad buffer/line driver; 3-state
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 10. Package outline SOT402-1 (TSSOP14)
74VHC_VHCT125_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 October 2009
11 of 15
74VHC125; 74VHCT125
NXP Semiconductors
Quad buffer/line driver; 3-state
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 11. Package outline SOT762-1 (DHVQFN14)
74VHC_VHCT125_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 October 2009
12 of 15
74VHC125; 74VHCT125
NXP Semiconductors
Quad buffer/line driver; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
LSTTL
ESD
Description
Complementary Metal Oxide Semiconductor
Low-power Schottky Transistor-Transistor Logic
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
CDM
Charge-Device Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
20091013
Data sheet status
Change notice
Supersedes
74VHC_VHCT125_2
Modifications:
Product data sheet
-
74VHC_VHCT125_1
• Errata in features list corrected.
74VHC_VHCT125_1
20090630
Product data sheet
-
-
74VHC_VHCT125_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 October 2009
13 of 15
74VHC125; 74VHCT125
NXP Semiconductors
Quad buffer/line driver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74VHC_VHCT125_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 October 2009
14 of 15
74VHC125; 74VHCT125
NXP Semiconductors
Quad buffer/line driver; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 October 2009
Document identifier: 74VHC_VHCT125_2
相关型号：
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