74VHC125SJ [FAIRCHILD]
Quad Buffer with 3-STATE Outputs; 四路缓冲带3态输出
| 型号： | 74VHC125SJ |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad Buffer with 3-STATE Outputs |
| 文件： | 总8页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1993
Revised February 2005
74VHC125
Quad Buffer with 3-STATE Outputs
General Description
Features
The VHC125 contains four independent non-inverting buff-
ers with 3-STATE outputs. It is an advanced high-speed
CMOS device fabricated with silicon gate CMOS technol-
ogy and achieves the high-speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
■ High Speed: tPD 3.8 ns (typ) at VCC 5V
■ Lower power dissipation: ICC A (max) at TA 25 C
4
■ High noise immunity: VNIH VNIL 28% VCC (min)
■ Power down protection is provided on all inputs
■ Low noise: VOLP 0.8V (max)
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
■ Pin and function compatible with 74HC125
Ordering Code:
Package
Order Number
Package Description
Number
74VHC125M
M14A
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC125MX_NL
(Note 1)
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC125SJ
M14D
MTC14
MTC14
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC125MTC
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC125MTCX_NL
(Note 1)
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74VHC125N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDED J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS011632
www.fairchildsemi.com
Logic Symbol
Connection Diagram
IEEE/IEC
Function Table
Pin Descriptions
Inputs
Output
On
Pin Names
Description
An
Bn
An, Bn
On
Inputs
Outputs
L
L
L
H
X
L
H
Z
H
H
L
Z
X
HIGH Voltage Level
LOW Voltage Level
HIGH Impedance
Immaterial
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Input Diode Current (IIK
Output Diode Current (IOK
DC Output Current (IOUT
DC VCC/GND Current (ICC
)
0.5V to 7.0V
0.5V to 7.0V
0.5V to VCC 0.5V
20 mA
)
Supply Voltage (VCC
Input Voltage (VIN
Output Voltage (VOUT
Operating Temperature (TOPR
)
2.0V to 5.5V
0V to 5.5V
0V to VCC
)
)
)
)
)
20 mA
)
40 C to 85 C
)
25 mA
Input Rise and Fall Time (tr, tf)
VCC 3.3V 0.3V
)
50 mA
0
100 ns/V
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
65 C to 150 C
VCC 5.0V 0.5V
0 20 ns/V
Note 2: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
260 C
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
V
T
25 C
Typ
T
A
40 C to 85 C
Max
CC
A
Symbol
Parameter
Units
Conditions
(V)
Min
Max
Min
1.50
0.7 V
V
V
V
HIGH Level Input
Voltage
2.0
1.50
IH
V
V
3.0 5.5 0.7 V
2.0
CC
CC
LOW Level Input
Voltage
0.50
0.50
0.3 V
IL
3.0 5.5
0.3 V
CC
CC
HIGH Level Output
Voltage
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
5.5
1.9
2.0
3.0
4.5
1.9
2.9
V
V
V I
IH OH
50 A
OH
IN
2.9
4.4
V
V
V
or V
IL
4.4
2.58
3.94
2.48
3.80
I
I
4 mA
8 mA
OH
OH
V
LOW Level Output
Voltage
0.0
0.0
0.0
0.1
0.1
0.1
0.1
V I
IH OL
50 A
OL
IN
or V
IL
0.1
0.1
0.36
0.36
0.25
0.44
0.44
2.5
I
I
4 mA
8 mA
OL
OL
V
A
I
I
I
3-STATE Output
Off-State Current
Input Leakage
Current
V
V
or V
IL
OZ
IN
IH
V
V
V or GND
CC
OUT
IN
0
5.5
0.1
4.0
1.0
A
A
5.5V or GND
IN
Quiescent Supply
Current
5.5
40.0
V
V
or GND
CC
IN
CC
Noise Characteristics
V
T
25 C
Limits
CC
A
Symbol
Parameter
Units
Conditions
(V)
Typ
V
Quiet Output Maximum
5.0
0.5
0.8
0.8
3.5
1.5
V
V
V
V
C
C
C
C
50 pF
50 pF
50 pF
50 pF
OLP
L
L
L
L
(Note 4)
Dynamic V
OL
V
Quiet Output Minimum
Dynamic V
5.0
5.0
5.0
0.5
OLV
(Note 4)
OL
V
Minimum HIGH Level
Dynamic Input Voltage
Maximum HIGH Level
Dynamic Input Voltage
IHD
(Note 4)
V
ILD
(Note 4)
Note 4: Parameter guaranteed by design.
3
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AC Electrical Characteristics
V
T
25 C
Typ
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
ns
Conditions
(V)
Min
Max
8.0
11.5
5.5
7.5
8.0
11.5
5.1
7.1
13.2
8.8
1.5
1.0
10
Min
Max
9.5
t
Propagation Delay
Time
3.3 0.3
5.6
8.1
3.8
5.3
5.4
7.9
3.6
5.1
9.5
6.1
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
C
C
C
C
C
C
C
C
C
C
C
C
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
50 pF
50 pF
50 pF
50 pF
PLH
L
L
L
L
L
L
L
L
L
L
L
L
t
13.0
6.5
PHL
5.0 0.5
3.3 0.3
5.0 0.5
ns
8.5
t
3-STATE Output
Enable Time
9.5
R
R
1 k
1 k
PZL
L
ns
t
13.0
6.0
PZH
ns
8.0
t
3-STATE Output
Disable Time
3.3 0.3
5.0 0.5
3.3 0.3
5.0 0.5
15.0
10.0
1.5
PLZ
L
ns
t
PHZ
t
Output to Output Skew
(Note 5)
OSLH
ns
t
1.0
OSHL
C
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance
4
6
10
pF
pF
pF
V
V
Open
5.0V
IN
CC
CC
C
OUT
PD
C
14
(Note 6)
Note 5: Parameter guaranteed by design. t
|t
t
|; t
|t
t
|.
PHLmin
OSLH
PLHmax
PLHmin OSHL
PHLmax
Note 6: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained by the equation: I (OPR.)
CC
C
* V * f
I
/4 (per bit).
PD
CC
IN
CC
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4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
相关型号：
74VHC126BQ
AHC/VHC/H/U/V SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PQCC14, 2.50 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT762-1, DHVQFN-14
NXP
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