74LVC2G241DP,125 [NXP]
74LVC2G241 - Dual buffer/line driver; 3-state TSSOP 8-Pin;型号: | 74LVC2G241DP,125 |
厂家: | NXP |
描述: | 74LVC2G241 - Dual buffer/line driver; 3-state TSSOP 8-Pin PC 驱动 光电二极管 输出元件 逻辑集成电路 |
文件: | 总18页 (文件大小:94K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LVC2G241
Dual buffer/line driver; 3-state
Rev. 09 — 10 June 2008
Product data sheet
1. General description
The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The
3-state outputs are controlled by the output enable inputs 1OE and 2OE:
• A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state.
• A LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC2G241 as a translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant input/output for interfacing with 5 V logic
I High noise immunity
I Complies with JEDEC standard:
N JESD8-7 (1.65 V to 1.95 V)
N JESD8-5 (2.3 V to 2.7 V)
N JESD8-B/JESD36 (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I ±24 mA output drive (VCC = 3.0 V)
I CMOS low power consumption
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I Inputs accept voltages up to 5 V
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC2G241DP
74LVC2G241DC
74LVC2G241GT
74LVC2G241GD
74LVC2G241GM
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
VSSOP8
XSON8
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
XSON8U plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
XQFN8U plastic extremely thin quad flat package; no leads;
SOT902-1
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
4. Marking
Table 2.
Marking codes
Type number
74LVC2G241DP
74LVC2G241DC
74LVC2G241GT
74LVC2G241GD
74LVC2G241GM
Marking code
V241
V41
V41
V41
V41
5. Functional diagram
1OE
1Y
1A
1
EN1
2OE
2Y
2A
2
EN2
001aah844
001aah845
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
2 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
6. Pinning information
6.1 Pinning
74LVC2G241
1OE
1A
1
2
3
4
8
7
6
5
V
CC
2OE
1Y
74LVC2G241
2Y
1
2
3
4
8
7
6
5
1OE
1A
V
CC
2OE
1Y
GND
2A
2Y
GND
2A
001aab570
Transparent top view
001aab569
Fig 3. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 4. Pin configuration SOT833-1 (XSON8)
74LVC2G241
terminal 1
index area
2OE
1
7
6
5
1OE
1A
74LVC2G241
1OE
1A
1
2
3
4
8
7
6
5
V
CC
1Y
2A
2
3
2OE
1Y
2Y
2Y
GND
2A
001aaf057
001aai247
Transparent top view
Transparent top view
Fig 5. Pin configuration SOT996-2 (XSON8U)
Fig 6. Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT505-2, SOT765-1,
SOT902-1
SOT833-1 and SOT996-2
1OE
1
7
output enable input (active LOW)
data input
1A, 2A
GND
2, 5
4
6, 3
4
ground (0 V)
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
3 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
Table 3.
Symbol
Pin description …continued
Pin
Description
SOT505-2, SOT765-1,
SOT902-1
SOT833-1 and SOT996-2
1Y, 2Y
2OE
6, 3
7
2, 5
1
data output
output enable input (active HIGH)
supply voltage
VCC
8
8
7. Functional description
Table 4.
Function table[1]
Input
1OE
L
Output
1A
L
2OE
H
2A
L
1Y
L
2Y
L
L
H
H
H
H
Z
H
Z
H
X
L
X
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
VI
+6.5
±50
VCC + 0.5
+6.5
+6.5
±50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
enable mode
mA
V
[1]
[1]
VO
−0.5
−0.5
−0.5
-
disable mode
V
[1][2]
Power-down mode
VO = 0 V to VCC
V
IO
output current
mA
mA
mA
°C
mW
ICC
IGND
Tstg
Ptot
supply current
-
ground current
−100
−65
-
storage temperature
total power dissipation
+150
300
[3]
Tamb = −40 °C to +125 °C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 packages: above 55 °C the value of Ptot derates linearly at 2.5 mW/K.
For VSSOP8 packages: above 110 °C the value of Ptot derates linearly at 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45 °C the value of Ptot derates linearly at 2.4 mW/K.
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
4 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
9. Recommended operating conditions
Table 6.
Operating conditions
Symbol Parameter
Conditions
Min
Max
5.5
5.5
VCC
5.5
5.5
+125
20
Unit
V
VCC
VI
supply voltage
input voltage
output voltage
1.65
0
V
VO
VCC = 1.65 V to 5.5 V; enable mode
VCC = 1.65 V to 5.5 V; disable mode
VCC = 0 V; Power-down mode
0
V
0
V
0
V
Tamb
ambient temperature
−40
°C
ns/V
ns/V
∆t/∆V
input transition rise and fall rate VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
-
-
10
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1] Max
Unit
Tamb = −40 °C to +85 °C
VIH
HIGH-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
2.0
-
0.7 × VCC
-
VIL
LOW-level input voltage
-
-
-
-
0.35 × VCC
0.7
0.8
0.3 × VCC
VOL
LOW-level output voltage VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
V
V
V
V
V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
0.45
0.3
0.4
0.55
0.55
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
V
1.2
1.9
2.2
2.3
3.8
-
V
IO = −8 mA; VCC = 2.3 V
V
IO = −12 mA; VCC = 2.7 V
V
IO = −24 mA; VCC = 3.0 V
V
IO = −32 mA; VCC = 4.5 V
V
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
±0.1 ±5
µA
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
5 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
OFF-state output current VI = VIH or VIL; VO = 5.5 V or GND;
CC = 3.6 V
power-off leakage current VI or VO = 5.5 V; VCC = 0 V
supply current VI = 5.5 V or GND; IO = 0 A;
CC = 1.65 V to 5.5 V
additional supply current per pin; VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
Min
Typ[1] Max
Unit
IOZ
-
±0.1 ±10
µA
V
IOFF
ICC
-
-
±0.1 ±10
µA
µA
0.1
10
500
-
V
∆ICC
-
-
5
µA
V
CI
input capacitance
2
pF
Tamb = −40 °C to +125 °C
VIH HIGH-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
2.0
-
0.7 × VCC
-
VIL
LOW-level input voltage
-
-
-
-
0.35 × VCC
0.7
0.8
0.3 × VCC
VOL
LOW-level output voltage VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
V
V
V
V
V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
0.70
0.45
0.60
0.80
0.80
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
V
0.95
1.7
1.9
2.0
3.4
-
-
V
IO = −8 mA; VCC = 2.3 V
-
V
IO = −12 mA; VCC = 2.7 V
-
V
IO = −24 mA; VCC = 3.0 V
-
V
IO = −32 mA; VCC = 4.5 V
-
V
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
±20
±20
µA
µA
IOZ
OFF-state output current VI = VIH or VIL; VO = 5.5 V or GND;
CC = 3.6 V
-
V
IOFF
ICC
power-off leakage current VI or VO = 5.5 V; VCC = 0 V
supply current VI = 5.5 V or GND; IO = 0 A;
CC = 1.65 V to 5.5 V
additional supply current per pin; VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
-
-
-
-
±20
µA
µA
40
V
∆ICC
-
-
5
mA
V
[1] Typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
6 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[2]
[3]
[3]
[4]
[4]
tpd
propagation delay nA to nY; see Figure 7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
1.0
0.5
1.0
0.5
0.5
4.5
2.8
2.8
2.6
2.1
8.8
4.9
4.7
4.3
3.7
1.0
0.5
1.0
0.5
0.5
11.0
6.3
5.9
5.4
4.6
ns
ns
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
ten
enable time
1OE to 1Y; see Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.5
0.5
0.5
5.2
3.1
3.2
2.7
2.0
9.9
5.6
5.5
4.7
3.8
1.5
1.0
1.5
0.5
0.5
12.4
7.0
6.9
5.9
4.8
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
2OE to 2Y; see Figure 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
1.0
1.0
1.0
0.5
4.3
2.7
2.7
2.5
1.9
8.8
4.7
4.6
4.1
3.3
1.0
1.0
1.0
1.0
0.5
11.0
5.9
5.8
5.1
4.1
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
1OE to 1Y; see Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
tdis
disable time
1.0
0.5
1.0
1.0
0.5
3.2
2.2
2.8
2.6
2.0
11.6
5.8
4.6
4.4
3.4
1.0
0.5
1.0
1.0
0.5
14.1
7.6
5.9
5.7
4.6
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
2OE to 2Y; see Figure 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
0.5
1.5
1.0
0.5
3.6
2.0
3.2
2.8
2.0
12.5
5.2
4.9
4.2
3.3
1.0
0.5
1.5
1.0
0.5
15.2
6.9
6.3
5.4
4.4
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
7 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[5]
CPD
power dissipation per buffer; VI = GND to VCC
capacitance
output enabled
-
-
20
5
-
-
-
-
-
-
pF
pF
output disabled
[1] Typical values are measured at nominal VCC and at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL
[3] ten is the same as tPZH and tPZL
[4] tdis is the same as tPLZ and tPHZ
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of outputs.
12. Waveforms
V
I
V
nA input
M
GND
t
t
PHL
PLH
V
OH
V
nY output
M
V
OL
mna230
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. The data input (nA) to output (nY) propagation delays
Table 9.
Measurement points
Supply voltage
VCC
Input
Output
VM
VM
VX
VY
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
1.5 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.3 V
V
OH − 0.15 V
OH − 0.15 V
OH − 0.3 V
OH − 0.3 V
OH − 0.3 V
V
V
V
V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 × VCC
0.5 × VCC
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
8 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
V
I
1OE input
V
M
t
GND
t
PLZ
PZL
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna730
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. Enable and disable times for input 1OE
V
I
2OE input
V
M
t
GND
t
PLZ
PZL
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna731
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9. Enable and disable times for input 2OE
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
9 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Load circuit for measuring switching times
Table 10. Test data
Supply voltage
Input
VI
Load
CL
VEXT
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2 × VCC
2 × VCC
6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
500 Ω
open
GND
open
GND
3.0 V to 3.6 V
4.5 V to 5.5 V
open
GND
6 V
open
GND
2 × VCC
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
10 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig 11. Package outline SOT505-2 (TSSOP8)
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
11 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 12. Package outline SOT765-1 (VSSOP8)
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
12 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
1
L
L
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
07-11-14
07-12-07
SOT833-1
- - -
MO-252
Fig 13. Package outline SOT833-1 (XSON8)
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
13 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A
1
detail X
terminal 1
index area
e
1
C
M
M
v
C A
C
B
b
e
L
1
y
y
w
C
1
1
4
L
2
L
8
5
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
L
v
w
y
y
1
1
2
max
0.05 0.35
0.00 0.15
2.1
1.9
3.1
2.9
0.5
0.3
0.15
0.05
0.6
0.4
mm
0.5
0.5
1.5
0.1
0.05 0.05
0.1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
- - -
JEDEC
JEITA
07-12-18
07-12-21
SOT996-2
- - -
Fig 14. Package outline SOT996-2 (XSON8U)
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
14 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
XQFN8U: plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
SOT902-1
D
B
A
terminal 1
index area
E
A
A
1
detail X
e
L
1
e
C
y
y
C
1
L
M
M
v
C A
C
B
4
w
5
6
7
3
2
metal area
not for soldering
e
1
b
e
1
1
terminal 1
index area
8
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
v
w
y
y
1
1
max
0.05 0.25 1.65 1.65
0.00 0.15 1.55 1.55
0.35 0.15
0.25 0.05
mm
0.5
0.55
0.5
0.1
0.05 0.05 0.05
REFERENCES
OUTLINE
VERSION
EUROPEAN
ISSUE DATE
PROJECTION
IEC
JEDEC
MO-255
JEITA
05-11-25
07-11-14
SOT902-1
- - -
- - -
Fig 15. Package outline SOT902-1 (XQFN8U)
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
15 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
14. Abbreviations
Table 11. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
Release date
20080610
Data sheet status
Change notice
Supersedes
74LVC2G241_9
Modifications:
Product data sheet
-
74LVC2G241_8
• Added type number 74LVC2G241GD (XSON8U package)
74LVC2G241_8
74LVC2G241_7
74LVC2G241_6
74LVC2G241_5
74LVC2G241_4
74LVC2G241_3
74LVC2G241_2
74LVC2G241_1
20080312
20071005
20060922
20050202
20040922
20030311
20030129
20021030
Product data sheet
Product data sheet
Product data sheet
Product specification
Product specification
Product specification
Product specification
Product specification
-
-
-
-
-
-
-
-
74LVC2G241_7
74LVC2G241_6
74LVC2G241_5
74LVC2G241_4
74LVC2G241_3
74LVC2G241_2
74LVC2G241_1
-
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
16 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC2G241_9
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 09 — 10 June 2008
17 of 18
74LVC2G241
NXP Semiconductors
Dual buffer/line driver; 3-state
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 June 2008
Document identifier: 74LVC2G241_9
相关型号:
74LVC2G241DP-Q100
LVC/LCX/Z SERIES, DUAL 1-BIT DRIVER, TRUE OUTPUT, PDSO8, 3 MM, PLASTIC, SOT505-2, TSSOP-8
NXP
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