74LVC16240ADGG-Q100_技术文档

74LVC16240A-Q100

16-bit buffer/line driver with 5 V tolerant inputs/outputs;

inverting; 3-state

Rev. 1 — 19 May 2014

Product data sheet

1. General description

The 74LVC16240A-Q100 is a 16-bit inverting buffer/line driver with 3-state outputs. The

device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device

features four output enables (1OE, 2OE, 3OE and 4OE), each controlling four of the

3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance

OFF-state.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices in mixed

3.3 V and 5 V applications.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing the damaging backflow current through the device

when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 5 V tolerant inputs/outputs for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low power consumption

 MULTIBYTE flow-through standard pinout architecture

 Low inductance multiple power and ground pins for minimum noise and ground

bounce

 Direct interface with TTL levels

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V

 JESD8-5A (2.3 V to 2.7 V

 JESD8-C/JESD36 (2.7 V to 3.6 V

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

74LVC16240A-Q100

NXP Semiconductors

16-bit buffer/line driver; 5 V tolerant; inverting; 3-state

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC16240ADGG-Q100 40 C to +125 C

TSSOP48

plastic thin shrink small outline package;

48 leads; body width 6.1 mm

SOT362-1

4. Functional diagram

47

36

35

33

2

13

14

16

17

1A0

1Y0

3A0

3A1

3A2

3Y0

3Y1

3Y2

3Y3

46

3

1A1

1Y1

44

5

1A2

1Y2

43

6

32

25

1A3

1Y3

3A3

1

1OE

3OE

41

30

29

27

8

19

20

22

23

2A0

2Y0

4A0

4A1

4A2

4Y0

4Y1

4Y2

4Y3

40

9

2A1

2Y1

38

11

2A2

2Y2

2Y3

37

12

26

24

2A3

4A3

48

2OE

4OE

001aaa439

Fig 1. Logic symbol

74LVC16240A-Q100

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Product data sheet

Rev. 1 — 19 May 2014

2 of 15

74LVC16240A-Q100

NXP Semiconductors

16-bit buffer/line driver; 5 V tolerant; inverting; 3-state

1

48

25

24

1EN

2EN

3EN

4EN

1OE

2OE

3OE

4OE

2

47

46

44

43

41

40

38

37

36

35

33

32

30

29

27

26

1A0

1A1

1A2

1A3

2A0

2A1

2A2

2A3

3A0

3A1

3A2

3A3

4A0

4A1

4A2

4A3

1Y0

1Y1

1Y2

1Y3

2Y0

2Y1

2Y2

2Y3

3Y0

3Y1

3Y2

3Y3

4Y0

4Y1

4Y2

4Y3

1

2

3

4

3

5

6

8

9

11

12

13

14

16

17

19

20

22

23

001aaa442

Fig 2. IEC logic symbol

74LVC16240A-Q100

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Product data sheet

Rev. 1 — 19 May 2014

3 of 15

74LVC16240A-Q100

NXP Semiconductors

16-bit buffer/line driver; 5 V tolerant; inverting; 3-state

5. Pinning information

5.1 Pinning

ꢀꢁ/9&ꢂꢃꢄꢁꢅ$ꢆ4ꢂꢅꢅ

ꢀ2(

ꢀ<ꢂ

ꢀ<ꢀ

*1'

ꢀ<ꢁ

ꢀ<ꢃ

ꢀ

ꢁ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢄꢈ ꢁ2(

ꢄꢇ ꢀ$ꢂ

ꢄꢆ ꢀ$ꢀ

ꢄꢅ *1'

ꢄꢄ ꢀ$ꢁ

ꢄꢃ ꢀ$ꢃ

9

ꢄꢁ

9

&&

ꢁ<ꢂ

ꢁ<ꢀ

ꢄꢀ ꢁ$ꢂ

ꢄꢂ ꢁ$ꢀ

ꢃꢉ *1'

ꢃꢈ ꢁ$ꢁ

ꢃꢇ ꢁ$ꢃ

ꢃꢆ ꢃ$ꢂ

ꢃꢅ ꢃ$ꢀ

ꢃꢄ *1'

ꢃꢃ ꢃ$ꢁ

ꢃꢁ ꢃ$ꢃ

*1' ꢀꢂ

ꢁ<ꢁ ꢀꢀ

ꢁ<ꢃ ꢀꢁ

ꢃ<ꢂ ꢀꢃ

ꢃ<ꢀ ꢀꢄ

*1' ꢀꢅ

ꢃ<ꢁ ꢀꢆ

ꢃ<ꢃ ꢀꢇ

9

&&

ꢀꢈ

ꢃꢀ

&&

ꢄ<ꢂ ꢀꢉ

ꢄ<ꢀ ꢁꢂ

*1' ꢁꢀ

ꢄ<ꢁ ꢁꢁ

ꢄ<ꢃ ꢁꢃ

ꢄ2( ꢁꢄ

ꢃꢂ ꢄ$ꢂ

ꢁꢉ ꢄ$ꢀ

ꢁꢈ *1'

ꢁꢇ ꢄ$ꢁ

ꢁꢆ ꢄ$ꢃ

ꢁꢅ ꢃ2(

DDDꢀꢁꢂꢁꢂꢃꢄ

Fig 3. Pin configuration TSSOP48

5.2 Pin description

Table 2.

Name

1OE

Pin description

Description

1

output enable input (active LOW)

output enable input (active HIGH)

output enable input (active LOW)

ground (0 V)

2OE

48

3OE

25

4OE

24

GND

4, 10, 15, 21, 28, 34, 39, 45

7, 18, 31, 42

2, 3, 5, 6

V_CC

supply voltage

1Y[0:3]

2Y[0:3]

3Y[0:3]

4Y[0:3]

data output

8, 9, 11, 12

13, 14, 16, 17

19, 20, 22, 23

data output

74LVC16240A-Q100

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Product data sheet

Rev. 1 — 19 May 2014

4 of 15

74LVC16240A-Q100

NXP Semiconductors

16-bit buffer/line driver; 5 V tolerant; inverting; 3-state

Table 2.

Name

Pin description …continued

Description

data input

1A[0:3]

2A[0:3]

3A[0:3]

4A[0:3]

47, 46, 44, 43

41, 40, 38, 37

36, 35, 33, 32

30, 29, 27, 26

6. Functional description

Table 3.

Function table^[1]

Input

nOE

L

Output

nAn

L

nYn

H

L

H

L

H

X

Z

[1] H = HIGH voltage level

L = LOW voltage level

X = don’t care

Z = high-impedance OFF-state

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

0.5

50

0.5

-

Max

+6.5

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0 V

mA

V

[1]

V_I

+6.5

50

V_CC+ 0.5

+6.5

50

100

-

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0 V

output HIGH or LOW state

output 3-state

mA

V

[2]

V_O

0.5

-

V

I_O

output current

V_O= 0 V to V_CC

mA

C

I_CC

I_GND

T_stg

P_tot

supply current

-

ground current

100

65

-

storage temperature

total power dissipation

+150

500

[3]

T_amb= 40 C to +125 C

mW

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2] The output voltage ratings may be exceeded if the output current ratings are observed.

[3] Above 60 C, the value of P_totderates linearly with 5.5 mW/K.

74LVC16240A-Q100

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Product data sheet

Rev. 1 — 19 May 2014

5 of 15

74LVC16240A-Q100

NXP Semiconductors

16-bit buffer/line driver; 5 V tolerant; inverting; 3-state

8. Recommended operating conditions

Table 5.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

1.65

1.2

0

Typ

Max

3.6

-

Unit

V

supply voltage

-

functional

V

V_I

input voltage

5.5

V_CC

5.5

+125

20

V

V_O

output voltage

output HIGH or LOW state

output 3-state

0

V

0

V

T_amb

ambient temperature

in free air

40

-

C

ns/V

t/V

input transition rise and

fall rate

V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 3.6 V

-

10

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

Min Max

Typ^[1]

1.08

40 C to +125 C

Min Max

1.08

Unit

V_IH

HIGH-level

V_CC= 1.2 V

-

V

input voltage

V_CC= 1.65 V to 1.95 V

0.65  V_CC

-

0.65  V_CC

V_CC= 2.3 V to 2.7 V

1.7

-

1.7

V_CC= 2.7 V to 3.6 V

V_CC= 1.2 V

2.0

-

2.0

V_IL

LOW-level

-

0.12

-

0.12

input voltage

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_IHor V_IL

0.35  V_CC

0.7

0.35  V_CC

0.7

0.8

V_OH

HIGH-level

output

I_O= 100 A;

V_CC= 1.65 V to 3.6 V

V_CC 0.2

-

V_CC 0.3

-

V

voltage

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 18 mA; V_CC= 3.0 V

I_O= 24 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

1.2

1.8

2.2

2.4

2.2

-

1.05

1.65

2.05

2.25

2.0

-

V

V_OL

LOW-level

output

voltage

I_O= 100 A;

-

0.2

-

0.3

V

V_CC= 1.65 V to 3.6 V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

-

0.45

0.6

-

0.65

0.8

V

-

V

-

0.4

0.6

V

-

0.55

5

0.8

V

I_I

input leakage V_CC= 3.6 V; V_I= 5.5 V or GND

current

0.1

20

A

74LVC16240A-Q100

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Product data sheet

Rev. 1 — 19 May 2014

6 of 15

74LVC16240A-Q100

NXP Semiconductors

16-bit buffer/line driver; 5 V tolerant; inverting; 3-state

Table 6.

Static characteristics …continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C

Min Max

20

Unit

Min

Typ^[1]

Max

I_OZ

OFF-state

output

V_I= V_IHor V_IL; V_CC= 3.6 V;

V_O= 5.5 V or GND;

-

0.1

5

-

A

current

I_OFF

power-off

leakage

current

V_CC= 0 V; V_Ior V_O= 5.5 V

0.1

10

20

A

I_CC

supply

current

V_CC= 3.6 V; V_I= V_CCor GND;

I_O= 0 A

-

0.1

5

20

-

80

A

I_CC

additional

supply

current

per input pin;

V_CC= 2.7 V to 3.6 V;

V_I= V_CC 0.6 V; I_O= 0 A

500

5000

C_I

input

V_CC= 0 V to 3.6 V;

-

5.0

-

pF

capacitance V_I= GND to V_CC

[1] All typical values are measured at V_CC= 3.3 V (unless stated otherwise) and T_amb= 25 C.

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit, see Figure 6.

Symbol Parameter

Conditions

T_amb= 40 C to +85 C 40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

[2]

[3]

t_pd

propagation

delay

nAn to nYn; see Figure 4

V_CC= 1.2 V

-

12.0

5.1

2.7

2.3

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.0

0.5

1.0

11.0

5.5

5.2

4.2

1.0

0.5

1.0

11.7

6.1

6.5

5.5

V_CC= 3.0 V to 3.6 V

nOE to nYn; see Figure 5

V_CC= 1.2 V

t_en

enable time

-

18.0

6.6

3.8

3.5

3.0

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

1.0

1.5

1.0

12.8

6.8

5.8

5.0

1.5

1.0

1.5

1.0

13.5

7.5

6.5

V_CC= 3.0 V to 3.6 V

nOE to nYn; see Figure 5

V_CC= 1.2 V

t_dis

disable time

-

11.0

4.7

2.6

3.5

3.2

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.9

1.0

1.5

-

9.2

5.0

5.1

4.9

1.0

2.9

1.0

1.5

-

9.7

5.6

6.5

1.5

V_CC= 3.0 V to 3.6 V

t_sk(o)

output skew

time

74LVC16240A-Q100

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Product data sheet

Rev. 1 — 19 May 2014

7 of 15

74LVC16240A-Q100

NXP Semiconductors

16-bit buffer/line driver; 5 V tolerant; inverting; 3-state

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V). For test circuit, see Figure 6.

Symbol Parameter

Conditions

T_amb= 40 C to +85 C 40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

[4]

C_PD

power

dissipation

capacitance

per input; V_I= GND to V_CC

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

-

4.8

8.3

-

pF

V_CC= 3.0 V to 3.6 V

11.4

[1] Typical values are measured at T_amb= 25 C and V_CC= 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.

[2] t_pdis the same as t_PLHand t_PHL

t_enis the same as t_PZLand t_PZH

t_disis the same as t_PLZand t_PHZ

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] _PDis used to determine the dynamic power dissipation (P_Din W).

.

C

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in Volts

N = number of inputs switching

(C_L V_CC² f_o) = sum of the outputs

11. Waveforms

V

I

nAn input

GND

V

M

t

PHL

PLH

V

OH

90 %

V

M

nYn output

M

10 %

V

OL

t

THL

TLH

mgu781

V_M= 1.5 V at V_CC 2.7 V;

V_M= 0.5  V_CCat V_CC< 2.7 V.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 4. The input nAn to output nYn propagation delays

74LVC16240A-Q100

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Product data sheet

Rev. 1 — 19 May 2014

8 of 15

74LVC16240A-Q100

NXP Semiconductors

16-bit buffer/line driver; 5 V tolerant; inverting; 3-state

V

I

nOE input

GND

V

M

t

PZL

PLZ

V

CC

output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PHZ

PZH

V

OH

V

Y

output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

enabled

outputs

disabled

mna362

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 5. 3-state enable and disable times

Table 8.

Measurement points

Supply voltage

V_CC

Input

Output

V_M

V_X

V_Y

1.2 V

0.5  V_CC

1.5 V

0.5  V_CC

1.5 V

V_OL+ 0.1 V

V_OL+ 0.3 V

V_OH 0.1 V

V_OH 0.3 V

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

3.0 V to 3.6 V

1.5 V

74LVC16240A-Q100

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Product data sheet

Rev. 1 — 19 May 2014

9 of 15

74LVC16240A-Q100

NXP Semiconductors

16-bit buffer/line driver; 5 V tolerant; inverting; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

EXT

R

V

CC

L

V

O

I

G

DUT

R

T

C

L

R

L

001aae331

Test data is given in Table 9.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 6. Test circuit for measuring switching times

Table 9.

Test data

Supply voltage

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

2  V_CC

t_PHZ, t_PZH

GND

1.2 V

V_CC

2.7 V

 2 ns

 2.5 ns

30 pF

50 pF

1 k

500 

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

open

GND

open

GND

open

GND

3.0 V to 3.6 V

open

GND

74LVC16240A-Q100

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Product data sheet

Rev. 1 — 19 May 2014

10 of 15

74LVC16240A-Q100

NXP Semiconductors

16-bit buffer/line driver; 5 V tolerant; inverting; 3-state

12. Package outline

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT362-1

D

E

A

X

c

v

A

H

E

y

Z

48

25

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

24

detail X

w

b

p

e

0

5 mm

2.5

scale

Dimensions (mm are the original dimensions)

(1)

(2)

Unit

max

A

b

c

D

E

e

H

L

1

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

°

8

0

0.15 1.05

0.05 0.85

0.28 0.2 12.6 6.2

0.17 0.1 12.4 6.0

8.3

7.9

0.8 0.50

0.4 0.35

0.8

mm nom 1.2

min

0.25

0.5

0.25 0.08 0.1

°

0.4

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

sot362-1_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

03-02-19

13-08-05

SOT362-1

MO-153

Fig 7. Package outline SOT362-1 (TSSOP48)

74LVC16240A-Q100

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Product data sheet

Rev. 1 — 19 May 2014

11 of 15

74LVC16240A-Q100

NXP Semiconductors

16-bit buffer/line driver; 5 V tolerant; inverting; 3-state

13. Abbreviations

Table 10. Abbreviations

Acronym

CDM

DUT

ESD

HBM

MIL

Description

Charged Device Model

Device Under Test

ElectroStatic Discharge

Human Body Model

Military

MM

Machine Model

TTL

Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

74LVC16240A_Q100 v.1 20140519

Product data sheet

-

74LVC16240A-Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 May 2014

12 of 15

74LVC16240A-Q100

NXP Semiconductors

16-bit buffer/line driver; 5 V tolerant; inverting; 3-state

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

15.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

74LVC16240A-Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 May 2014

13 of 15

74LVC16240A-Q100

NXP Semiconductors

16-bit buffer/line driver; 5 V tolerant; inverting; 3-state

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74LVC16240A-Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 May 2014

14 of 15

74LVC16240A-Q100

NXP Semiconductors

16-bit buffer/line driver; 5 V tolerant; inverting; 3-state

17. Contents

1

2

3

4

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

Functional description . . . . . . . . . . . . . . . . . . . 5

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12

7

8

9

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 13

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 14

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 19 May 2014

Document identifier: 74LVC16240A-Q100


型号：	74LVC16240ADGG-Q100
厂家：	NXP
描述：	LVC/LCX/Z SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT362-1, TSSOP-48 驱动光电二极管输出元件
文件：	总15页 (文件大小：262K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LVC16240ADGG-Q100 [NXP]

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