74LV125PW,118 [NXP]
74LV125 - Quad buffer/line driver; 3-state TSSOP 14-Pin;
| 型号： | 74LV125PW,118 |
| 厂家： | 
NXP |
| 描述： | 74LV125 - Quad buffer/line driver; 3-state TSSOP 14-Pin 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总15页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LV125
Quad buffer/line driver; 3-state
Rev. 03 — 7 April 2009
Product data sheet
1. General description
The 74LV125 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC125 and 74HCT125.
The 74LV125 provides four non-inverting buffer/line drivers with 3-state outputs. The
3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE
causes the outputs to assume a high-impedance OFF-state.
2. Features
I Wide operating voltage: 1.0 V to 5.5 V
I Optimized for low voltage applications: 1.0 V to 3.6 V
I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
I Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
I Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 °C
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LV125N
74LV125D
−40 °C to +125 °C
−40 °C to +125 °C
DIP14
SO14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
SOT108-1
plastic small outline package; 14 leads;
body width 3.9 mm
74LV125DB
74LV125PW
−40 °C to +125 °C
−40 °C to +125 °C
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
SOT402-1
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74LV125
NXP Semiconductors
Quad buffer/line driver; 3-state
4. Functional diagram
1A
1Y
2Y
3Y
4Y
3
6
2
2
1
1OE
2A
1
5
3
6
1
5
EN1
2OE
3A
4
9
4
9
8
8
3OE
4A
10
12
10
12
13
nY
nA
11
11
4OE
13
nOE
mna229
mna227
mna228
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one buffer)
5. Pinning information
5.1 Pinning
74LV125
1
2
3
4
5
6
7
14
13
12
11
10
9
1OE
1A
V
CC
74LV125
4OE
4A
1
2
3
4
5
6
7
14
13
12
11
10
9
1OE
1A
V
CC
1Y
4OE
4A
2OE
2A
4Y
1Y
2OE
2A
4Y
3OE
3A
3OE
3A
2Y
2Y
8
GND
3Y
GND
8
3Y
001aaj961
001aaj921
Fig 4. Pin configuration DIP14, SO14
Fig 5. Pin configuration SSOP14, TSSOP14
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
2 of 15
74LV125
NXP Semiconductors
Quad buffer/line driver; 3-state
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1OE, 2OE, 3OE, 4OE,
1A, 2A, 3A, 4A
1Y, 2Y, 3Y, 4Y
GND
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
7
output enable input (active LOW)
data input
data output
ground (0 V)
VCC
14
supply voltage
6. Functional description
Table 3.
Function table[1]
Control
Input
nA
L
Output
nY
nOE
L
L
L
H
H
Z
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7.0
±20
±50
±35
70
Unit
V
supply voltage
−0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
-
mA
mA
mA
mA
mA
°C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−70
−65
-
storage temperature
total power dissipation
+150
[2]
Tamb = −40 °C to +125 °C
DIP14
-
-
750
500
mW
mW
SO14, SSOP14, TSSOP14
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO14 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
3 of 15
74LV125
NXP Semiconductors
Quad buffer/line driver; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
Parameter
supply voltage[1]
Conditions
Min
Typ
Max
5.5
Unit
V
1.0
3.3
VI
input voltage
0
-
VCC
VCC
+125
500
200
100
50
V
VO
output voltage
0
-
V
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
−40
+25
°C
VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 5.5 V
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
ns/V
[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level input voltage
VCC = 1.2 V
0.9
-
-
-
-
-
-
-
-
-
0.9
-
V
V
V
V
V
V
V
V
VCC = 2.0 V
1.4
-
-
1.4
-
-
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.2 V
2.0
2.0
0.7VCC
-
0.7VCC
-
VIL
LOW-level input voltage
HIGH-level output voltage
-
-
-
-
0.3
0.6
0.8
0.3VCC
-
-
-
-
0.3
0.6
0.8
0.3VCC
VCC = 2.0 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL
VOH
IO = −100 µA; VCC = 1.2 V
IO = −100 µA; VCC = 2.0 V
IO = −100 µA; VCC = 2.7 V
IO = −100 µA; VCC = 3.0 V
IO = −100 µA; VCC = 4.5 V
IO = −8 mA; VCC = 3.0 V
IO = −16 mA; VCC = 4.5 V
-
1.2
2.0
2.7
3.0
4.5
2.82
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
1.8
2.5
2.8
4.3
2.4
3.6
1.8
2.5
2.8
4.3
2.2
3.5
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
4 of 15
74LV125
NXP Semiconductors
Quad buffer/line driver; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 100 µA; VCC = 1.2 V
IO = 100 µA; VCC = 2.0 V
IO = 100 µA; VCC = 2.7 V
IO = 100 µA; VCC = 3.0 V
IO = 100 µA; VCC = 4.5 V
IO = 8 mA; VCC = 3.0 V
IO = 16 mA; VCC = 4.5 V
VI = VCC or GND;
-
-
-
-
-
-
-
-
0
0
-
-
-
-
-
-
-
-
-
-
V
0.2
0.2
0.2
0.2
0.40
0.55
1.0
0.2
0.2
0.2
0.2
0.50
0.65
1.0
V
0
V
0
V
0
V
0.20
0.35
-
V
V
II
input leakage current
µA
VCC = 5.5 V
IOZ
OFF-state output current
VI = VIH or VIL;
-
-
5
-
10
µA
VO = VCC or GND;
V
CC = 5.5 V
VI = VCC or GND; IO = 0 A;
CC = 5.5 V
per input; VI = VCC − 0.6 V;
CC = 2.7 V to 3.6 V
ICC
∆ICC
CI
supply current
-
-
-
-
-
20
500
-
-
-
-
160
850
-
µA
µA
pF
V
additional supply current
input capacitance
V
3.5
[1] Typical values are measured at Tamb = 25 °C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter Conditions −40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Typ[1] Max
Min
Max
[2]
tpd
propagation delay nA to nY; see Figure 6
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
-
-
-
-
-
-
55
19
14
9
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
24
18
-
31
23
-
[3]
[3]
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
nOE to nY; see Figure 7
VCC = 1.2 V
10
-
14
12
18
15
[2]
ten
enable time
-
-
-
-
-
75
26
19
14
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 2.0 V
31
23
18
15
39
29
23
19
VCC = 2.7 V
[3]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
5 of 15
74LV125
NXP Semiconductors
Quad buffer/line driver; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter
Conditions
−40 °C to +85 °C
Min
Typ[1] Max
−40 °C to +125 °C
Unit
Min
Max
[2]
tdis
disable time
nOE to nY; see Figure 7
VCC = 1.2 V
-
-
-
-
-
-
65
24
18
14
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
pF
VCC = 2.0 V
32
24
20
17
-
39
29
24
21
-
VCC = 2.7 V
[3]
[4]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CPD
power dissipation CL = 50 pF; fi = 1 MHz;
capacitance VI = GND to VCC; VCC = 3.3 V
22
[1] All typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL
ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
.
.
.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V).
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fI = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
11. Waveforms
V
I
V
nA input
M
GND
t
t
PHL
PLH
V
OH
V
nY output
M
V
OL
mna230
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. The input (nA) to output (nY) propagation delays
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
6 of 15
74LV125
NXP Semiconductors
Quad buffer/line driver; 3-state
V
I
nOE input
GND
V
M
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna362
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Enable and disable times
Table 8. Measurement points
Supply voltage
VCC
Input
VM
Output
VM
VX
VY
< 2.7 V
0.5VCC
1.5 V
0.5VCC
0.5VCC
1.5 V
VOL + 0.1VCC
VOL + 0.3 V
V
V
V
OH − 0.1VCC
2.7 V to 3.6 V
≥ 4.5 V
OH − 0.3 V
0.5VCC
VOL + 0.1VCC
OH − 0.1VCC
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
7 of 15
74LV125
NXP Semiconductors
Quad buffer/line driver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Load circuit for measuring switching times
Table 9.
Test data
Supply voltage Input
Load
CL
VEXT
VCC
VI
tr, tf
RL
tPHL, tPLH
open
tPZH, tPHZ
GND
tPZL, tPLZ
2VCC
< 2.7 V
VCC
2.7 V
VCC
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
50 pF
1 kΩ
2.7 V to 3.6 V
≥ 4.5 V
15 pF, 50 pF 1 kΩ
50 pF 1 kΩ
open
GND
2VCC
open
GND
2VCC
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
8 of 15
74LV125
NXP Semiconductors
Quad buffer/line driver; 3-state
12. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
14
8
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2.2
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT27-1
050G04
MO-001
SC-501-14
Fig 9. Package outline SOT27-1 (DIP14)
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
9 of 15
74LV125
NXP Semiconductors
Quad buffer/line driver; 3-state
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 10. Package outline SOT108-1 (SO14)
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
10 of 15
74LV125
NXP Semiconductors
Quad buffer/line driver; 3-state
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
7
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT337-1
MO-150
Fig 11. Package outline SOT337-1 (SSOP14)
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
11 of 15
74LV125
NXP Semiconductors
Quad buffer/line driver; 3-state
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 12. Package outline SOT402-1 (TSSOP14)
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
12 of 15
74LV125
NXP Semiconductors
Quad buffer/line driver; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
74LV125_3
Release date
20090407
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LV125_2
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name when appropriate.
74LV125_2
74LV125_1
19980428
Product specification
-
74LV125_1
19970203
Product specification
-
-
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
13 of 15
74LV125
NXP Semiconductors
Quad buffer/line driver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
14 of 15
74LV125
NXP Semiconductors
Quad buffer/line driver; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 April 2009
Document identifier: 74LV125_3
相关型号：
74LV125PW-T
LV/LV-A/LVX/H SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14
NXP
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